Development of improved i v characteristics models for nanometer size mesfets by Md Papon

) (amp)

ds simulated ds experimental

Current deviation (I -I

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DRAIN TO SOURCE VOLTAGE Vds (volt)

0.06 0.05 0.04

Vgs=0V -1V -2V -3V -4V -5V -6V -7V -8V -9V

0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 0

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0.8

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Experimental Proposed mo

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for SiC substrate for Sapphire substrate

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Development of Improved I-V Characteristics Models for Nanometer Size MESFETs CHAPTER 1 INTRODUCTION TO MESFET In this chapter, the MESFET is being introduced. This chapter includes what is MESFET, what it stands for. The history of the MESFET is also discussed briefly here.

1.1 Introduction

MESFET stands for Metal Semiconductor Field Effect Transistor. The metal-semiconductor field effect transistor was first introduced by Mead in 1966 and subsequently fabricated by Hooper and Lehrer using a GaAs epitaxial layer on semi insulating GaAs substrate. MESFET is a unipolar device, a converse of bipolar transistor. The difference of these two is apparent that, in bipolar device the current conducting results for both minority carrier electron in p region and minority carrier hole in n region on p-n junction while the in a MESFET the current conduction results only from the majority carrier. Like in a n type MESFET, electrons are the particles that give rise current and in p type MESFET same operation is done by majority carrier holes in the conduction channel. MESFET offers certain processing and performance advantages, such as low temperature formation of the metal-semiconductor barrier (as compared to a p-n junction made by diffusion or grown process), low resistance and low IR drop along the channel width and good heat dissipation for power devices (the rectifying contact also serve as an efficient thermal contact to heat sink). The operation of Junction Field Effect Transistor (JFET) and MESFET is apparently same. MESFET offers superior performance in some processing realm than JFET, especially in RF microwave operation that makes RF amplifier more efficient.

There are various types of MESFET fabricated by different semiconductors. The family tree of MESFET is given below—

Figure 1.1: Family tree of MESFET from ref [2] The main concern of this publication is proposing an I-V Characteristics for a typical MESFET. Before we move to the main topic, we must look for the history of MESFET.

1.2 History It was early 1925 when FET model was proposed. Since 1925, advent of advanced technology led to more sophisticated devices. At one stage at 1966 MESFET model was proposed. A brief timeline of the history of MESFET has been given. •

1925 Austrian- Hungarian physicist Julius Edgar Lilienfeld has first proposed field-effect transistor principle. This principle was patented by Canada.

•

1934 German physicist Dr. Oskar Heil patented another field-effect transistor

•

Lilienfeld and Heil did not construct any devices.

•

1939 William Shockley and a co-worker at Bell Labs, Gerald Pearson, had built operational versions from Lilienfeld's patents

•

1943 Ralph Bray, a fresh graduate student of PURDUE University had observed the minority carrier injection but this phenomenon was not being recognized then and it was taken as anomaly

•

1948 effect of minority carrier injection realized by Bell Labs and they Constructed first transistor

•

1949 Bipolar junction transistor by Brattain, Bardeen and Shockley of Bell Laboratories

•

1950 spacistor type transistor was developed

•

1951 alloy junction transistor, Grown junction transistor had been developed

•

1952 William Shockley along with his co-workers proposed the principle of Junction Field Effect Transistor.

•

1954 Morris Tanenbaum et al. at Bell Laboratories were the first to develop a working silicon transistor

•

1955 A superior method was developed by Morris Tanenbaum and Calvin S. Fuller at Bell Laboratories by the gaseous diffusion of donor and acceptor impurities into single crystal silicon chips.

•

1958 First Integrated Circuit by Jack Kilby of Texas Instrument

•

1959 Si planar process: Procedure resembles integrated circuits of today by Robert Noyce of Fairchild

•

1960 p-channel Si MOSFET was described by Dawon Kahng, a member of Atallai group

•

1966 The first Gallium-Arsenide Schottky-gate field-effect transistor (MESFET) was made by Carver Mead and reported in 1966

A brief timeline of the above discussion is given below—

Figure 1.2: Timeline of history of MESFET

1.3 Application of the MESFET The MESFET is used in many RF amplifier applications. The MESFET semiconductor technology provides for higher electron mobility and in addition to this the semi-insulating substrate there are lower levels of stray capacitance. This combination makes the MESFET ideal as an RF amplifier. In this role MESFETs may be used as microwave power amplifiers, high frequency low noise RF amplifiers, oscillators, and within mixers. MESFET semiconductor technology has enabled amplifiers using these devices that can operate up to 50 GHz and more, and some to frequencies of 100 GHz. The GaAs MESFET has a number of differences and advantages when compared to bipolar transistors. The MESFET has a very much higher input as a result of the non-conducting diode junction. In addition to this it also has a negative temperature co-efficient which inhibits some of the thermal problems experienced with other transistors. When compared to the more common silicon MOSFET, the GaAs FET or MESFET does not have the problems associated with oxide traps. Also a MESFET has better channel length control than a JFET. The reason for this is that the JFET requires a diffusion process to create the gate and this process is far from well defined. The more exact geometries of the GaAs MESFET provide a much better and more repeatable product, and this enables very small geometries suited to RF microwave frequencies to cater for. In many respects GaAs technology is less well developed than silicon. The huge ongoing investment in silicon technology means that silicon technology is much cheaper. However GaAs technology is able to benefit from many of the developments and it is easy to use in integrated circuit fabrication processes. The GaAs MESFET is widely used as an RF amplifier device. The small geometries and other aspects of the device make it ideal in this application. Typically a supply voltage of around 10 volts will be used. However care must be taken when designing the bias arrangements because if current flows in the gate junction, it will destroy the GaAs FET. Similarly care must be taken when handling the devices as they are static sensitive. In addition to this, when used as an RF amplifier connected to an antenna, the device must be protected against static received during electrical storms. If these precautions are observed, the GaAs MESFET will perform exceedingly well. The MESFET is an electronics component that is relatively cheap, and will perform well. Numerous MESFET fabrication possibilities have been explored for a wide variety of semiconductor systems. Application of MESFET can be summarized as below— • RF Amplifiers •

Microwave Power Amplifiers

•

Oscillators

•

Mixers

•

Military communications

•

Military radar devices

•

Commercial optoelectronics

•

Satellite communications

In this study both SiC and GaAs MESFETs has been discussed. Specific application of the SiC and GaAs MESFET is discussed in the next section.

1.3.1 Application of SiC MESFET SiC MESFET has some advantages. SiC MESFET device is wide energy band gap device. It exhibits high breakdown electric device. It has also high electrical and thermal conductivity. It also exhibits high saturation electron velocity. Its melting point is high and it is chemically inert. The major applications include •

Wireless Communication

•

Microwave Circuits

•

High Power

•

High Frequency

•

Power Amplifiers 1.3.2 Application of GaAs MESFET

GaAs MESFET has some advantages over Si MESFET. The room temperature mobility of the GaAs MESFET is five times than that of Si. As a result the saturation velocity of the GaAs MESFET is about twice of the Si MESFET. Moreover semi insulating (SI) GaAs MESFET can be fabricated which eliminates the problem of absorbing microwave power in the substrate due to free carrier absorption. The major applications include: •

Radar

•

Cellular phone

•

Satellite Receivers

•

Microwave Devices

•

High Frequency

CHAPTER 2 MESFET OPERATION

The Chapter is introduced by the operation principle of MESFET under equilibrium and non equilibrium state. The modes of operation and I-V characteristics are also discussed here. For predicting I-V characteristics the drain current equation is derived and above all some processing descriptions are given as well.

2.1 Operation of MESFET

2.1.1. Equilibrium State

Earlier it has been said that MESFET is a unipolar device, which means only the majority carrier particle is responsible for the conduction of the MESFET. MESFET is operation is very similar to JFET & MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this section operation of the MESFET is main concern. A schematic diagram of a MESFET is shown in Figure 2.1. MESFET is fabricated on a semi insulating substrate. On the top of the semi insulating layer there is light n (n MESFET) or light p (p MESFET) implant. Then source and drain are of highly doped n region (for n MESFET) or highly doped p region (for p MESFET). These source and drain terminal are indicated as S and D respectively. The gate terminal is metal deposited. This region acts as a Schottky diode. Figure 2.1: n-MESFET with no voltage at gate electrode

Gate

The active region where current conduction takes place is between source and drain and type of particle flow or the direction of current depends on what type of MESFET is used, whether n or p type. Let it’s a n MESFET, light n implant is diffused in the semi insulating substrate and then high n implant is given to form the source and drain region. On the top of the highly doped source and drain, metal is given. This is ohmic contact. There is a junction between gate metal and the light n region under the gate. This junction controls the current in the active region. When no voltage source is given at any terminal then there exist a depletion barrier between light n region and gate t metal due to intrinsic potential barrier. This interface between gate and light n region under it, behave almost like a p+-n interface. It can be thought as a single sided abrupt p-n junction. So the depletion width is along the lightly doped n implant i.e. the active region according to the following equation. …………………………………………….……….………………..(2.1) is the almost the whole depletion width t, then built in potential can be found as— ……………………………………………………………………………(2.2) Here we are tactically assuming that thickness of channel length is greater than the depletion region, which is actually the case for a depletion type MESFET. However extensive study is going on this depletion type MESFET due to having some advantages over other type MESFET. The band diagram of the junction of gate and channel is like below at equilibrium condition— (a) (b)

Figure 2.2: (a) ideal metal and semiconductor before making any contact (b) metal- semiconductor band diagram after contact is made and voltage is not given at gate electrode In Figure 2.2 (a), the vacuum level is used as reference level. The parameter : Lower conduction band energy of semiconductor : Upper valance band energy of semiconductor : Fermi level of semiconductor : Intrinsic Fermi Energy, : Metal work function : Semiconductor work function : Electron affinity : Ideal barrier height of semiconductor contact :

Here we have assumed that , the ideal thermal equilibrium metal-semiconductor energy band diagram, for this situation, is shown in Figure 2.2 (b). Before the contact, the Fermi level in the semiconductor was above that in the metal. In order for the Fermi level to become a constant through the system in thermal equilibrium, electrons from the semiconductor flow into the lower energy states in the metal. Positively charged donor atoms remain in the semiconductor, creating a space charge region. potential barrier is seen by the electrons in the metal trying to move into the semiconductor. This barrier is known as Schottky barrier and is given by, ideallyâ&#x20AC;&#x201D; (2.3) On the semiconductor side, is the built in potential barrier. This barrier, similar to the case of p-n junction, is barrier seen by electrons in the semiconductor in the conduction band trying to move into the metal. The built in potential barrier is given byâ&#x20AC;&#x201D; (2.4) This makes the potential be a function of doping concentration. 2.1.2 Non equilibrium state From Figure 2.1 itâ&#x20AC;&#x2122;s obvious that the channel length can be varied by varying the depletion region. Now to control the depletion region we can reverse bias the p+-n junction, i.e. the gate and light n region, under gate, Interface. This is illustrated in the schematic of Figure 2.3. Figure 2.3: Depletion type MESFET

VGS

under negative voltage at gate electrode VDS

Gate

The source is connected to ground and to reverse bias the Schottky diode a negative voltage is given with respect to source at gate. As its being reverse biased, so the depletion width will

increase. By varying this depletion region one can control the effective channel length to flow the current conducting particle. To flow the electron here (n type MESFET), positive voltage is given with respect to the drain. As drain is at positive voltage, drain part of Schottky diode is more reversed bias than the source part, so depletion region extends as moving from the source to drain. Due to drain is in more positive potential than the source, the electron will flow from the source to drain along the channel length. Now if more negative voltage with respect to gate, then the depletion width will increase and eventually stops the channel. So it’s apparent that the threshold voltage for depletion type MESFET is negative. Assuming that voltage is dropped across the depletion region when it just cover the whole channel thickness (), can be calculated as below— (2.5)

So the threshold voltage is (2.6) The energy band diagram of the junction of gate-channel under reverse bias is shown below— Figure 2.4: MESFET band diagram under reverse bias V R: Reverse bias voltage applied at gate electrode As negative voltage is given at the gate metal, so the Fermi of metal moves upward and that of semiconductor moves downward. The difference between these two Fermi energies is the amount of reverse bias voltage applied. As reverse bias voltage is given, it effectively increases the barrier height seen by electrons tend to flow from metal to semiconductor.

2.1.3 Velocity Saturation Before moving to the derivation of drain current and I-V characteristics, the velocity saturation phenomenon should be described briefly to support the I-V characteristics section. Most famous MESFET in recent time is GaAs MESFET. Now just scheme through the velocity versus electric field curve below for some semiconductor materials—

Figure 2.5: Drift Velocity vs. Electric Field curve of some semiconductors This electric field is along the channel length. For a n-MESFET this electric field is in negative X-axis direction. From the curve, it has been seen for low electric field the velocity increases with the field linearly. If is velocity of particle (here electron) and E is the electric field then velocity can be written as(2.7) Here µ is mobility and a proportional constant. For GaAs this mobility is higher than Si, as the slope curve is steeper for lower electric field. As one increases the voltage at drain terminal and it thus increase the electric field E and after some time the velocity of the particle will be saturated. In this region constant mobility term is not met. Often mobility has been assumed constant in the operation of JFET, MOSFET etc. But for MESFET channel length is less than others, which results higher electric field for relatively smaller voltage, as E depends on—

(2.8)

So in short channel GaAs MESFET saturation in current is achieved when velocity is saturated resulting from application of certain voltage at drain terminal.

2.1.4 Drain Current Equation Derivation In this section, the current flowing between drain and source while giving enough voltage on gate (greater than threshold voltage) will be deduced. For the derivation, the cross section of MESFET, It is assumed that a MESFET bar is taken of width W. after initial fabrication process of producing light n region over semi insulating substrate, high n region drain and source region are formed and gate is formed by depositing and etching the metal. The length of the channel is the length of the gate is L. It is also assumed that in initial fabrication process the depth of implanting light n region is . The whole diagrammatic structure is shown in Figure 2.6

n+ Source

Figure 2.6: Situation

MESFET

Current VGS

VDS

Conducting Gate

Now positive bias is given on drain side, and negative voltage is given to the gate side, as it makes the junction between gate and channel a reversed bias. So a depletion region is formed. Proper voltage application on the gate ensures that the channel is not fully depleted. As a voltage is applied to the drain so there will be an electric field in the direction of the drain to source. So the electron will be attracted to the drain and will flow in a direction from source to drain through the undepleted region and this makes the conducting current to give rise. As the depletion region is dependent on the Schottky metal gate, so the current through the channel also depends on it. It should be mentioned here that the application of the voltage on the drain side (), it is uniformly distributed throughout the length of the channel. This voltage varies from 0 V at the source to the at the drain. For this distribution of voltage, the depletion region created under biasing tends to be more at the drain side. Assuming the length of channel is along +ve x direction, voltage is distributed to the x axis uniformly. So the thickness of the depletion region is a function n+ Drain of and it can be written as the uniform voltage distribution is The current in the channel can written as n- active layer

Substrate Depletion region A

: drain current (A) : Electron concentration (for n-MESFET) (per m3) : Electron charge (1.602Ă&#x2014;C) : drift velocity of electron through the channel (m/sec)

(2.9)

: Cross section of the channel through which electron passing (m2)

From the section 2.1.3 it has been seen that for low electric field, the drift velocity of the electron is proportional to the electric field applied it can be written as

(2.10)

Here is the electron mobility of the device which depends on material of the device. And the area through which current is flowing can be written as

(2.11)

Here is the depth of the light n region as depicted earlier and is the depth of the depletion region. So effective undepleted region along which electron can pass through is . These are illustrated in Figure 2.6.

Let the doping concentration at the light n region is then equation (2.10) and (2.11) can be substituted in equation (2.9) and it looks like belowâ&#x20AC;&#x201D;

(2.12)

In this equation (2.12) negative sign actually means that direction of current and direction of drift velocity of electron is opposite.

From the definition of potential it can be written as (2.13) So equation (2.12) becomes

(2.14)

Now the expression of d and should be derived. The derivation is beyond this publication and this derivation can be seen from any solid state device book and it is as follows

For a p-n junction reverse bias by applying a voltage , the depletion region extends both on p and n region and the part of the depletion region at the n region is given as

(2.15)

: Permittivity of semiconductor : built in potential (V) : reverse bias voltage (V) : Hole concentration (1/m3) : Electron concentration (1/m3) : Electron charge (1.602Ă&#x2014;C)

The derivation of equation (2.15) can be found in ref [13] In our study, we are dealing with an abrupt one sided interface and it can be thought as a p+ - n interface between gate and the channel. So , so equation (2.15) can be written as (2.16)

Now let voltage is required to reverse bias our MESFET bar such that depletion region covers the whole thickness , this voltage is also known as pinch off voltage, so from equation (2.16) (2.17) Assuming, , and equation (2.17) can alternatively be written as

(2.18)

Now the threshold voltage of the device will be the voltage required to fully deplete the light n region and that will be

(2.19)

For the expression of we can see that the effective reverse bias voltage along the interface between gate and channel is and from equation (2.17) we can write

(2.20)

Now recalling equation (2.14) and putting the value of from (2.20)

(2.21) (2.22) From equation (2.18), using the terms and integratin on both sides of equation (2.22)-

(2.23)

Assuming, Then

and

for , for ,

Equation (2.23) can be written as

(2.24) (2.25) For This equation (2.25) found for the Typical MESFET device is valid for the region,

For the grater drain voltage the current saturates, the drain voltage at which drain current saturatesâ&#x20AC;&#x201D;

Drain saturation current will be given asâ&#x20AC;&#x201D;

(2.26) For As we know, (2.27)

The equation is modified as below (2.28) For

This is the drain current equation of a MESFET. It’s derived on some assumption •

It assumed that electron mobility is constant

•

Electric field along the channel doesn’t increase further than saturated electric field

This equation holds good for these constraints imposed but unsatisfactory result may occur if these criteria are not met. So, for proper I-V modeling there are different approaches of deducing drain current equation. Here, our main goal is to establish a drain current equation and compare its I-V characteristics with other models.

2.1.5 I-V characteristics of MESFET

An I-V characteristic of a typical MESFET is similar to that of a MOSFET and JFET. An I-V characteristic of a typical MESFET is shown in Figure 2.7. In this Figure the drain current is plotted against drain-source voltage. Drain current is also a function of gate source voltage. So the individual curve in the Figure represents the dependency of drain current on drain- source voltage for a particular value of gate- source voltage. In this Figure the I-V characteristics of a depletion type MESFET has been shown. Form the Figure 2.7, it is seen there are two modes of operation of MESFET. There is another mode which is breakdown mode due to excessive application of drain- source voltage.

Figure 2.7: I-V characteristics of MESFET As in discussion of operation of a MESFET in section 2.1 it has been mentioned that necessary voltage should be given at the gate electrode. By applying more negative voltage at the gate electrode makes junction of gate-channel more reversed biased. So the depletion width increases. At one stage of increasing of negative voltage at gate electrode, makes the channel fully depleted, then no current flows. So the voltage at the gate electrode should be such that it is greater than the minimum value of gate voltage that makes the phenomenon of full depletion, namely threshold voltage. In the Figure it is seen that the current ID is very low for lower . If we further increase the negative voltage on gate the channel will stop. It can be said from intuition that the threshold voltage of the Figure 2.7 is near the lowest VGS curve. So for current conducting region or modes are valid for , be threshold voltage. Now the individual modes of current conduction are explained below.

2.1.5.1 Linear Region () This region is valid for low value of . From fig 2.7, it is seen that for low value of , drain current ID which flows from drain to source depends almost linearly on V DS for a particular value of .

As the dependency of on is linear, so the region is called linear region. The region is also called a triode region. This region is applicable for the value of less than where (2.29) The is not same for all value of . This change has been shown by the dotted locus. With the decrease of , the value of also decreases as shown in the Figure 2.7 It was noted earlier that the drain current can be written as below— (2.30) Where : Drain current (A) : Electron concentration (for n-MESFET) (per m3) : Electron charge (1.602×C) : Drift velocity of electron through the channel (m/sec) : Cross section of the channel through which electron passing (m2)

From Figure 2.7 one can see that with the increase in the cross section decreases, so it is expected to decrease in current with the increase in but such is not the case. Because of the presence of drift velocity . With the increase of voltage , electric field E X also increases and for low EX, with the increase of EX drift velocity of v increases linearly and it overpowers the decrease in cross section A. So with the increase in voltage , increases in linear region.

2.1.5.2 Saturation Region () In linear region, with increase of , increases. But after a certain value of , with the increase in , the value of does not change considerably. Normally this saturation of current is reached at , which is shown in Figure 2.7. Though saturation is achieved, drain current still tends to increase. This is due to the fact that the pinch off point shifts toward the source from the drain; this effectively decreases the channel length. As the channel length is decreased, so current increases. Saturation may occur in two different ways for a MESFET depending upon the material used. They are discussed below—

2.1.5.2.1 Saturation by pinch off In the MESFET device fabricated by the material like Si which has reasonable high saturation electric field value, saturates by pinching off the channel between source and drain. This is illustrated in Figure 2.8. High saturation electric field value means, the drift velocity of carrier saturates at a higher value of electric field along the channel. The case is such that, the mobility may be considered as constant throughout the process and with the increase in voltage, depletion on drain side increases. At a certain value of this depletion on drain side pinches off the channel, so at this stage this part of channel posses a high impedance and carrier cannot be passed through. But with the high electric field

some of the carriers are swept off to the drain side and thus saturates the current. In the following Figure (Figure 2.8) the case of pinch off is shown while applying voltage greater than Figure 2.8: Current Saturation in a

MESFET due to pinch off VGS

VDS

2.1.5.2.2 Saturation by velocity

saturation

Gate We have discussed about the velocity saturation of some semiconductors in section 2.1.3. From the section of 2.1.3 it has been seen that the drift velocity of the carrier saturates comparably at a lower electric field for the material like GaAs. As beyond the saturation a greater value of is applied, so the electric field is high. For this high electric field the velocity of the carriers through the channel saturates. The phenomenon is also likely to happen if the device has short channel as it ensures greater strength of the electric field. In this type of device the saturation in drain current occurs due to the velocity saturation of the carrier. For an example, it can be approximated that the saturated electric field for GaAs is about 4 kVcm-1 (estimated from Figure 2.5) and let the channel length of a MESFET in consideration is 1 µm then the voltage required to saturate the carrier drift velocity is

Pinch off

=4kVcm-1×1µm=0.4 V

(2.31)

For pinching off the voltage required can be written as— (2.32) Note that this pinch off voltage alternatively can be written as threshold voltage, this is the voltage required to fully deplete the channel region. Where : Electron charge (1.602×10-19C) : Doping concentration for n MESFET : Total width of the active channel : Permittivity of the semiconductor used : built in potential Typical values of these parameters may be— =3×1023 m-3 = 0.15µm ϵ=13 =0.8 V So pinch off voltage, (2.33)

So it has been seen before pinch off occurs, the drift velocity of carrier will saturate and thus it saturates the drain current . Figure 2.9 illustrates the phenomenon—

Figure 2.9: Current Saturation VGS saturation

MESFET

due

velocity

VDS

Gate 2.1.5.3 Breakdown If one keeps increasing the voltage, expecting a regulatory response of drain current the breakdown may occur. If this occurs, device fails to operate and act as short circuit medium. With a small change of , large current of flows. This mode is not expected obviously and each device is provided by its breakdown voltage by manufacturer.

2.1.5.4 Summary Table 2.1: Overview of different regions of operation of a MESFET Region Linear

Range

Device Cross section

I-V Curve

Saturation (due to velocity saturation) Saturation (due to pinch off)

2.1.6 Equivalent Circuit of a MESFET From the discussion of the operation and modes of operation of a MESFET, it is possible to predict an equivalent circuit of the MESFET. The component of the circuit are superimposed on the cross sectional view of a MESFET in the following diagram

Figure 2.10: Equivalent circuit component imposed on sectional view of MESFET Here we have assumed that the MESFET be an n-MESFET. Each element is intended to represent the electrical character of a particular region of the device. •

Cgs: Capacitance represents the charge storage in the depletion region at source gate region

•

Cgd: Capacitance represents the charge storage in the depletion region at gate drain region

•

Rs: Resistance represents the bulk resistance of N-layer in the source gate region together with any contact resistance at the source ohmic metallization

•

Rd: Resistance represents the bulk resistance of N-layer in the gate drain region together with any contact resistance at the drain ohmic metallization

•

Rg: parasitic resistance at the gate

•

Ri: internal source-gate resistance

•

gm0v: represents the drain current flow along the channel from drain to source

•

r0: substrate resistance

•

C0: substrate capacitance

•

v: the direction of voltage is along gate to source

For the circuit behavior analysis of the above modeling of components the following circuit can be considered-Figure 2.11: Equivalent Circuit of MESFET Typical range of the values of the component is shown below Table 2.2: Typical values of the circuit components of MESFET Component Value Rg

0.5-3 Ω

Cgs

0.15-0.4 pF

2-10 Ω

1-5 Ω

Cgd

0.01-0.03 pF

gm0

20-40 mS

0.05-0.1 pF

250-500 Ω

2.2 Processing of MESFET There are various ways to fabricated MESFET but two most popular methods are

• Ion Implantation • Epitaxial Growth As fabrication technique of MESFET is not the main concern of this paper. But one should have a basic knowledge of fabricating the device. So here a brief description of fabrication of MESFET is given. For further study see ref

2.2.1 Ion Implantation In this fabrication process the MESFET is produced from a single wafer of a semi insulating semiconductor substrate like GaAs. The whole process is shown schematically from top to bottom. At the top a semi insulating Substrate is taken. In this substrate lightly n doped layer is given by ion diffusion. Then the highly doped n region is given by ion implantation. And finally metal contact is given to the gate, source and drain.

Figure 2.12: (top to bottom): semi insulating substrate, diffusion of n - implant, n+ ion implantation, contact given 2.2.2 Epitaxial Growth: In this process a lightly doped n region is fabricated epitaxial on the semi insulating substrate. It is also described schematically—

Figure 2.13 (left to right): semi insulating sub, n - region epitaxial grown, n+ ion implantation, etching and contact given

From left to right, at most left corner, a semi insulating substrate is taken. Then lightly doped n region is epitaxial formed over the semi insulating surface. Then highly doped region is given by ion implantation. After that except the source and drain region, its being etched and finally gate contact as well as drain, source contacts are given.

2.2.3 Summary of Fabrication The fabrication of a GaAs MESFET can be summarized by the following procedures—

Figure 2.14: MESFET fabrication

2.3 Types of MESFET There are 2 types of MESFET depending upon the fabrication. They are stated below— • Depletion MESFET • Enhancement MESFET Each type is discussed below—

2.3.1 Depletion MESFET In Depletion type MESFET the depletion width of the gate- channel junction due to the built in potential is less than the channel depth i.e. . This is depicted in the following Figure— Figure 2.15: Depletion type MESFET In depletion type of MESFET, the device is normally ON. The depletion width is varied by varying the voltage at the gate electrode. Suppose it is an n- MESFET then negative voltage is needed at the gate electrode to increase the depletion width. At one moment of increase of the negative voltage at gate electrode the depletion width fully covers the channel region. This specifies the threshold voltage and thus the threshold voltage for depletion MESFET is negative. Typical I-V curve of Depletion type MESFET—

Figure 2.16: I-V characteristics of Depletion type MESFET It is seen that here is negative and also the threshold voltage is negative and curves shift upward with the increase of

2.3.2 Enhancement MESFET In Enhancement MESFET the depletion width of the gate-channel junction due to built in potential is greater than the channel width i.e. . In this type of MESFET, as the depletion width fully covers the channel region, so the device is normally OFF device. Assume that this is an n-MESFET then if positive voltage is given at gate electrode, it makes the junction between gate and channel be forward biased. Due to forward biasing, the depletion width along the channel will be reduced and at

certain value of the current will conduct through the channel. So here the threshold voltage is positive and giving more positive voltage at the gate electrode the drain current increases. This is depicted in the following Figure— Figure 2.17: enhancement type MESFET

Typical I-V characteristics of an enhancement type MESFET has been shown below. It is clear that the I-V characteristics for both depletion and enhancement type are same i.e. with the increase in current increases. Figure 2.18: I-V characteristics of enhancement type MESFET

2.4 Structure of MESFET There are 2 types of structure of MESFET, they are— •

Self aligned source and drain MESFET

•

Non Self aligned source and drain MESFET

2.4.1 Self aligned source and drain This form of structure reduces the length of the channel and the gate contact covers the whole length. This can be done because the gate is formed first, but in order that the annealing process required after the formation of the source and drain areas by ion implantation, the gate contact must be able to withstand the high temperatures and this results in the use of a limited number of materials being suitable. The diagram below shows this type of structure—

Gate

Figure 2.19: Self aligned MESFET 2.4.2 Non-self aligned source and drain For this form of MESFET, the gate is placed on a section of the channel. The gate contact does not cover the whole of the length of the channel. This arises because the source and drain contacts are normally formed before the gate. Following Figure illustrates such structure—

Gate

Figure 2.20: Non self aligned MESFET

CHAPTER 3 LITERATURE REVIEW Since 1966 of the proposal of first MESFET device by Mead, there are different models are introduced to establish the I-V characteristics of MESFET which suits best with the practical values. Among many of the models, some of them are highlighted. The comparison of these models is also given later in the chapter.

3.1 Importance and Specification of I-V model

3.1.1 Importance In any integrated circuit design one usually starts with a computer simulation of the circuit to be built. In order to construct the device, one has to design the circuit by considering the I-V characteristics of devices. So a reasonable and practical I-V model is often needed by a designer. Some of the importances of I-V model are mentioned below •

Significant aids to integrated circuit design

•

Eliminates the delay of cut and try design approaches

•

I-V model opens the door to PC analysis and simulation of the device

•

Due to the analysis and simulation in PC is possible, manual gross approximation can be eliminated which often leads to invalidity

3.1.2 Specification When one wants to model I-V characteristics, he has to remind some factors. The I-V model should be such that it nearly follows the practical values. Some of the specifications of I-V model are given below— •

It should be simple

•

It should be compact

•

It should have minimum number of variables

•

It should be such that it takes less CPU execution time

•

It should predict the device characteristics regardless of size

•

It may be changed during fabrication

•

Simulated result should match the actual measurement

3.2 Existing I-V Models for MESFET There are different models proposed by different scholars. Among them, Curtice model which is very preliminary but still is widely used in educational purpose. Before Curtice, Schichman-Hodges proposed another model which is stated below. Along with Curtice model there are Kacprzak-Materka model, Statz model , Rodriguez model and most recent Mansoor model. There may be other models, but here we are discussing about these models and will compare these models in the next section. Before we move to the description of various models, the notation of the symbols should be stated in table 3.1 Table 3.1: Notation of the symbols are used in the following discussion Symbol Notation Drain Current Gate to Source Voltage Pinch-off Voltage Drain to Source Voltage Modulation factor Transconductance parameter Simulates the dependency of on Measure of doping profile extending to the insulating part Saturation Current () Simulated the dependency of on

3.2.1 Schichman-Hodges Model From the very beginning of the production of MESFET, it was very vital to establish an equation for the drain current of the device, and thus enabling the I-V characteristics analysis. The earliest I-V model for MESFET device may be Schichman-Hodges Model. This model was established in the year of 1968. As we know the introduction of MESFET in modern technology has been arrived on 1966. So in early days of MESFET technology the I-V model is used is SchichmanHodges Model. This model implies the following drain current equation— (3.1)

(3.2) (3.3) This model is separated by boundary region. The equation of drain current consists of 3 parts. The device is not turned on if the is lower than the threshold voltage. When is sufficiently larger than the threshold voltage VT0 then the drain current will conduct if a voltage is applied between drain and source terminal, it be . This drain current is divided in two parts. First part when the is greater than 0 but lower than the , in this case the region is in linear region as described in section 2.1.5. In this region drain current increases almost linearly with the increase of . When is sufficiently large, nominally larger than then the device is in saturation region. Current will increase with a small slope (almost constant) with the increase of . This model of MESFET drain current is almost obsolete, because further advancement of modeling has made the equation unique for all regions. Further this model has only considered the modulation factor, the factor by which drain current depends on in saturation region. In modern modeling more factors has been considered like there are dependency factor of I D on in the linear region which is not included here. Dependency of VT0 on VDS is also neglected. 3.2.2 Curtice Model The most simplified model and probably the most famous one is Curtice model. Curtice has proposed his I-V model of MESFET in the year of 1980, a decade after Schichman-Hodges. The drain current equation for the Curtice model is as belowâ&#x20AC;&#x201D; (3.4) (3.5) Obviously lower than the , threshold voltage; the device is in OFF state. In this state, sufficient voltage is not applied to overcome the underlying depletion region. As the gets higher than threshold voltage , the device is ON. In this stage, if drain-source voltage, V DS is applied the current will flow. The interesting part of this model is that the both linear and saturation region is modeled in the same equation. Composing of linear region and saturation region in the same equation has been possible for the introduction of the tan hyperbolic function. Curtice has tactically included the tan hyperbolic function. If we look at the tan hyperbolic function of , it will be seen that with the small value of , is approximately linear. That means with low value of , tanh(x) follows . with the greater value of , function approaches unity. This is shown below graphically. Figure 3.1: plot of vs. So it can be summarizedâ&#x20AC;&#x201D; (3.6) (3.7) In Curtice model for lower value of , the drain current follows . As the function t becomes with low value of . In this case the device is in linear region and I D follows linearly approximately. When the is high enough that the function becomes unity, then the current saturates and fixed at the value . In this model Curtice has included a new parameter Îą, which determines at which value of , will saturate.

Curtice is simplest one but its accuracy is poor overall and deteriorates considerably with reduced I D. Further specification will be seen in the next section where a brief comparison is done. 3.2.3 Statz Model After Curtice, Hermann Statz has realized that the hyperbolic function inclusion makes CPU to take more time for calculation. So Hermann Statz has proposed a model in 1987 and he removed the hyperbolic function and deduced equation separately for different regions. The drain current equation stated in Statz model is – (3.8) For VGS> VT0 (3.9) (3.10) In this model it’s seen that an extra parameter is being included which is . Statz has fooled thoroughly the vs curve, where he had seen for low , the drain current approximately follows the square law with the . It’s being clear from equation as for low denominator is negligible. Statz also stated that for higher value of the curve of vs is a square root law. But while simulating, it’s found that it is more fits with the practical values if the dependency of is linear with . So for higher value of , denominator term is greater than unity and a linear relation between and established. He also has included the parameter . This parameter actually depends on the fabrication process. Statz has mentioned about the gradual change of doping concentration from the channel to the insulating part. For the gradual change of doping profile due to diffusion the vs curve of other models do not fit well. With that empirical equation including b, it’s possible for track the practical value more. Furthermore b actually represents the uncertainty of source and drain parasitic resistors in a bare transistor. As a whole b is a measure of doping profile extending to the insulating part and depends on fabrication .Typical value of for an abrupt profile with pinch off voltage V P=0.5 and 1×20µm gate. Apart from Curtice, Statz has introduced another term instead of tan hyperbolic function which is . This is approximated polynomial instead of tan hyperbolic function. This considerably reduces the computational time for CPU simulation. In the equation the part for which is for saturation region and is for linear region.

3.2.4 Kacprzak-Materka Model The error produced in both linear and saturation region is considerable in the previous models. To improve the response of I-V characteristics to fit with the actual values, Kacprzak and Materka had proposed a model in 1983, which is known as Kacprzak-Materka model and as follows — (3.11) For VGS>VT0 (3.12) The model proposes a more complex term of tan hyperbolic function and another parameter has been included here. Actually the inclusion of makes to more follows the practical values of . In previous models the dependency of on bias voltage has not been considered. In this model it is being considered and gives rise to more accuracy. Kacprzak- Materka had stated that the gross assumptions of abrupt transition to substrate and zero substrate conductivity are not valid for a non ideal device.

Typically the MESFET is produced epitaxial on the semi insulating substrate. This substrate posses some conductivity, so some injection of electron in substrate takes place. If the channel is thin then the number of electron injected is not negligible compared to the number of electrons in residual channel. Moreover, large drain voltage beyond saturation gives rise to holes generation by impact ionization within the high field domain and injection of these carriers into substrate. The injected electrons and holes are the leakage current flowing in the substrate from source to drain and shunting the main path of drain current in the channel. So the increase of drain source voltage beyond saturation increases leakage and effectively decreasing the channel current which can be modeled by shifting the effective pinch off potential which is drain voltage, dependent. Here Kacprzak- Materka has used the Taki formula [20] which is (3.13)

Kacprzak- Materka has modified the pinch off voltage by . The pinch off voltage is the almost equal to threshold voltage.

3.2.5 Rodriguez Model J.Rodriguez- Tllez has proposed a model by simplifying the complex Materka model. Form the point of view of accuracy, Materka model and Rodriguez model is almost same. In fact about 12% improvement in Rodriguez model has been seen from the Materka model. Rodriguez model proposes the drain equation as belowâ&#x20AC;&#x201D; (3.14) For VGS>VT0 (3.15) Objective of the Rodriguez model was to achieve a model which imposes less error than the practical one and simultaneously take less CPU processing time. For the better accuracy, initially the dependency of are investigated. and are the parasitic resistances in the source and drain region. It was seen that and does not depend on the bias. The most dependency factor on is which is actually taken consider in all of the previous models. But , has small dependency on bias voltage. Rodriguez put himself to obtain the most accurate and less taking CPU time model by considering this dependency of , on and he reached to a solution by including a parameter which represents the dependency of on . For CPU to take less time Rodriguez did not make the tan hyperbolic function a complex term and the function of tan hyperbolic function is same as depicted in section 3.2.2.

3.2.6 Mansoor Model Mansoor M. Ahmed has proposed an I-V model suitable for nonlinear small-signal circuit design in 1997. Kacprzak-Materka who started the prediction of behavior of submicron devices, Mansoor model takes this a one step further. Mansoor proposed a model by including a new concept of shift in threshold voltage. Drain current equation of this model is as followsâ&#x20AC;&#x201D; (3.16) For VGS>VT0 (3.17)

Mansoor M. Ahmed started with analysis of Kacprzak-Materka model. He has seen the KacprzakMaterka model is not suitable for submicron devices and well for large signal analysis. He started to modify the model of Materka to make suitable for small signal analysis. He found two factors that may be the reason of discrepancy of Materka model between the observed and simulated characteristics. Two factors are— •

The shift in VT0 due to submicron geometry of the device

•

The poor control in simulating the output conductance, especially at V GS=0

In this model threshold voltage is redefined as --(3.18) is the geometrical shift in the threshold voltage and it’s given as (3.19)

: Gate length : Active channel thickness Finally Mansoor M. Ahmed has reached to the above DC model where , , can be determined readily by knowing the doping density and geometry of the device and others are empirical constants.

3.3 Comparison of Models Form the above section, a summary of all models are tabulated as below Table 3.2: Summary of the different models proposed Model Expressions Curtice [6] Statz [7]

Materka [8] Rodriguez [22] Mansoor [1]

The nonlinear I-V models which are discussed above, each has its own merits demerits. With the advent of new technology, it is necessary to establishing a new model which best fits for the current situation. One of the earliest models is Curtice model which is not accurate with low channel length device. This obsolescence of Curtice model is due to the advance of modern technology. Obviously Curtice model and other earlier models are very important because these models have formed the base to the further analysis of MESFET modeling.

Comparison of different models described in previous section is given in a tabular format. It has to remind that the comparison of the following table has made with respect to the 5 models discussed in section 3.2 Table 3.3: Comparison of the different models discussed in section 3.2 Specification Model Curtice

Statz

Accuracy at Poor but 40% Poorest linear region better than with low ID Statz Accuracy at poorest saturation region under high current

Poor better Curtice

Overall Accuracy

poor

Poor

CPU Execution time

next best Statz

Continues model

YES

to smallest

Materka

Rodriguez

Mansoor

Most accurate, Moderate High 62% better accurate, 50% Accuracy than Statz better than Statz but More accurate than than Curtice and Statz but not good enough

Accuracy is Most accurate higher than the previous three models

Moderate

Good

Best

highest

Moderate

YES

Higher

Moderate

Less

Error increase Highest, with device lesser size decrease Statz

but Highest than

Error in the Highest large devices

Highest

Less

Less but not Less less than Materka

CV model worse accuracy

best

moderate

good

Error at Pinch worse off

worse

good

best

Before Mansoor proposed his model, Rodriguez had compared the remaining four models. He investigated the four models Curtice, Statz, Materka and Rodriguez by varying the finger and gate width by keeping channel length at 0.5µm. the table has shown below—

Table 3.4: I-V Error as function of pinch off voltage, number of fingers and gate width (normalized at VDS=4V, VGS=0V) from ref [11] MODEL PinchError2 CPU off seconds voltage 1×25µ 1×100µm 2×25µm 2×100µm 4×75µm 6×150µm m Curtice

-2

0.46

2.11

1.05

4.75

8.30

24.52

2.578125

Statz

Rodriguez

Materka

-1

0.52

1.23

0.43

1.79

4.29

5.50

-2

0.47

2.29

1.03

4.78

9.21

28.30

-1

0.46

0.65

0.46

1.65

4.05

7.10

-2

0.21

0.93

0.56

2.38

4.10

15.66

-1

0.18

1.17

0.22

0.92

1.38

2.59

-2

0.40

1.49

0.48

1.68

2.12

7.97

-1

0.81

2.00

1.18

4.50

7.16

9.27

1.152344

2.628906

2.640625

The pinch off voltage has a strong bearing on the accuracy of all models with the lower (-2 V) pinch off device providing the large model error as seen in the table 3.3. Possible reasons for this may be due to thermal effects which become more important with the lower pinch-off devices (-2 V) because of the increased current density. This may also be the reason why the error of each model increases with increasing device size. The number of finger does not disturb this pattern. We have also investigated four models (Curtice, Materka, Rodriguez and Mansoor model) for 4×25µm wide and 0.2µm long GaAs with 192 mA .. As it is seen that the channel length is very low, so from above discussion it’s expected that the error due to Curtice, Materka, and Rodriguez model should be high. Mansoor model is more consistent in the reduced channel length. From computer simulation following result has been achieved—

Table 3.5: Simulation result of different models proposed, RMS error= Model

RMS error

Avg. RMS error

VGS (V) 0

0.5

1.5

Curtice

122.6431

116.6551

77.8200

5.4965

103.2513

72.2841

Materka

49.0615

9.5671

13.1202

19.9934

14.8648

18.1546

Rodriguez

47.6307

12.7764

7.4384

14.0555

9.3331

15.6136

Mansoor

0.6376

2.1696

4.9546

8.5496

10.0398

3.9901

The table 3.5 is a gross result. It is often needed to see which part of the model exhibit more errors. So with the values of as depicted in table 3.4 and for different values of the square of the error between the simulated and actual I D has been plotted for the four devices. This shows that Mansoor model is best accurate in all regions than others. It was expected because we have chosen 0.2µm channel length device. For such low submicron devices other models show greater error. (3.20)

Error2 is plotted with varying and Figure 3.2: Comparison of error in drain current from simulated and actual characteristics for individual VGS and VDS voltage (a) Curtice Model (b) Materka Model (c) Rodriguez Model (d) Mansoor Model for 4×25µm wide and 0.2µm long GaAs CHAPTER 4 DC I-V CHARACTERISTIC MODEL FOR NANOMETER RANGE GaAs MESFETS An improved non-linear five parameter I-V characteristics model is proposed here for nanometer range GaAs MESFETs. The effect of bias voltage on drain current as well as on conductance is also analyzed. The developed model was also compared to the existing models employing the root mean square (RMS) error technique.

4.1 Introduction Gallium arsenide (GaAs) is a compound of two elements, gallium and arsenic. Its band gap is 1.42 eV. It is an important semiconductor and is used to make devices such as microwave frequency integrated circuits, infrared light-emitting diodes, laser diodes and solar cells. Key advantages of GaAs are: • Higher saturated electron velocity • Higher electron mobility (8500 cm2/V-s) • GaAs devices generate less noise • Breakdown voltage is higher (4·105 V/cm) • It is a direct band gap material • Higher mobility leads to a higher current, trans-conductance and transit frequency of the device. Gallium arsenide is used in the manufacture of light-emitting diode s (LEDs), which are found in optical communications and control systems. Gallium arsenide can replace silicon in the manufacture of linear ICs and digital ICs. Linear (also called analog ) devices include oscillators and amplifier s. Digital devices are used for electronic switching, and also in computer systems. It is possible to fabricate semi-insulating (SI) GaAs substrates which eliminate the problem of absorbing microwave power in the substrate due to free carrier absorption.

4.2 Properties of GaAs Some electronic and physical properties of GaAs are listed below in table 4.1 Table 4.1: properties of GaAs [28] Property Value

Units

Electron Mobility

4000

cm2V-1s-1

Electron saturation velocity

1.4 x 107

cm2s-1

Hole mobility

250

cm2V-1s-1

(ND=1017 cm-3)

(ND=1017 cm-3) Dielectric Constant

12.6

Intrinsic resistivity

109

Ohm cm

Energy gap

1.43 (Direct)

Schottky barrier height

0.7-0.8

Thermal conductivity

0.9

W cm-1 K-1

4.3 Model development To simulate the I-V characteristics as a function of and of a uniformly doped GaAs MESFET, the following relationship has been reported in Ahmed et al. model [1]: (4.1)

Here, = saturation current at = 0V. = parameter that determines the drain voltage where the drain current characteristic saturates. = parameter that simulates the effective threshold voltage displacement as a function of . = threshold voltage and = the geometric shift in threshold voltage. The and are defined by (4.2) And (4.3)

Respectively in Where, = channel doping density, = electronic charge, = permittivity of GaAs, = Schottky barrier height, = the active channel thickness and = the gate length. In the sub-threshold region (lower values of ), the I-V curves are not linear rather it has some nonlinear behavior. Furthermore the curve transitions from the triode to saturation region are not sharp. The experimental data shows that the drain current characteristics saturation depends not only on , but also on . These facts should be considered for the development of I-V characteristics of MESFETs. Hence the term in equation (4.1) has been modified to . Another parameter is introduced which determines the gate voltage where the drain current characteristic saturates. In equation (4.1), the effect of on output conductance in the saturation region has been excluded. When the gate is more negatively biased, the depletion layer under the gate expands as shown in figure 4.1. Therefore, more positive charge is stored under the gate in response to the increase in gate bias, i.e. the depletion layer exhibits charge storage properties which can be described in electrical terms by a capacitance. The depleted electron due to positive charge storage is transported to the drain. The gate shaded region of figure 4.1 can be treated as the combined properties of depletion layer capacitance and channel resistance [4]. So the output conductance also varies with the variation of and this change of output conductance occurs both before and after saturation for nanometer GaAs MESFETs.

Figure 4.1: The effect of on depletion layer for constant . (Solid line for more negative bias, ) Therefore, the output conductance not only depends on but also on . For submicron MESFETs, the dependencies of output conductance on and are also reported in. The value of output conductance (), is the most unpredictable parameter in the device characteristics and is considered one of the major variables which generate discrepancy in simulated and the observed characteristics, specially in submicron devices [22-25]. In order to add the above mentioned effects on output conductance, the term in equation (4.1) has been modified to . Another parameter is introduced. The following expression is proposed for the simulation of I-V characteristics in nanometer GaAs MESFETs [16]: (4.4)

The I-V characteristics of MESFETs are modeled for in out experiment, i.e. for depletion mode MESFETs (DMESFETs). Therefore, dependence in , using equation (4.4) has been discussed for DMESFETs. However, equations (4.1) and (4.4) can also be utilized for the modeling of enhancement mode MESFETs (EMESFETs). 4.4 The Algorithm

A simulator was designed using MATLAB to employ expressions given in previous equations to simulate the I-V characteristics. The optimum values of the parameters were found out by comparing the simulated results with the experimented results. The set of parameter values were used for which the root mean square error (RMSE) is minimized. The RMSE can be expressed by the formula 4.5 (4.5) Where

= drain to source current found from the simulation = drain to source current found from experimental analysis = total number of entities

The algorithm that calculates the optimum values for the parameters is shown in figure 4.2

Figure 4.2: Flowchart for the optimization of proposed model [16] parameters

The algorithm is designed as to choose the best possible set of values for the parameters resulting minimum RMSE. At first an approximate initial value is set to each parameter. Then the simulator calculates the drain current for all possible combinations of these parameters within the defined range. This process is repeated for different set of data for different values of gate to source voltage (). The simulated values of the drain current are then compared with the experimented results. The deviation is measured in terms of RMSE and the minimum value of RMSE searches out the best possible combination of parameters (). This calculates the optimal output characteristics

4.5 Measured and Modeled Characteristics In order to demonstrate the validity of the proposed model a wide range of GaAs MESFETs with different aspect ratios were selected. Since these devices have different aspect ratios, their I-V characteristics are also different. The nominal gate lengths of the devices are 200-230 nm. For simulation purposes, data is generated on a PC by employing an algorithm. The values of , and are attained from the terminal measurements of the device, and empirical constants were estimated by computing Root Mean Square Errors (RMSE) from the observed and the simulated characteristics. The same algorithm has also been used for the optimization of model parameters of Ahmed et al. model (equation 4.1). Figure 4.2 shows both the simulated and the observed I-V characteristics of four different GaAs MESFETs.

Figure 4.3: Observed and simulated output characteristics of GaAs MESFETs. (The solid circles represent the experimental data (Figs. 4.3 (a), 4.3 (b), 4.3 (c) from [27], & 4.3 (d) from [26]), dotted lines show the simulated characteristics using Ahmed et al.[1] model and solid lines show the simulated characteristics using the proposed model) Table 4.1: the optimum values of the parameters used in the Mansoor et al. model and proposed model Ahmed et al. model[1] Proposed Model [16]

Device of

1.8

0.08

-0.08

1.77

0.38

-0.36

0.09

-1.31

1.4

0.11

-0.26

1.35 1

-0.005 -0.246 0.11

-0.52

1.27

0.07

-0.31

1.14

0.09

-0.44

-0.6

1.287 0

0.021 0

-0.3580 1.2

-0.2

-0.151 0.01 5

Fig. 4.3 (a) Device of Fig. (b)

4.3

Device of Fig. 4.3 (c) Device of Fig. (d)

4.3

0.07 7

-0.19

4.6 Transconductance and Output Conductance

4.6.1 Transconductance Trans-conductance () represents the change of drain-current with respect to gate-to-source voltage . Equation of () is found by differentiating the equation of with respect to

Transconductance derived from Mansoor et al. model [1]: (4.6)

Transconductance derived from proposed model [16] (differentiating equation 4.4 with respect to )

(4.7)

The comparison in performance to calculate the transconductance between the existing Mansoor et al. model and the proposed model is shown below with the help of figure 4.3

IDS = 192mA/mm VT+Î&#x201D;VT = -2.0 V

Experimental data Ahmed [1] model Proposed model

TRANSCONDUCTANCE gm (mS/mm)

250

200

150

100

-50 -3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

GATE TO SOURCE VOLTAGE VGS (V)

Figure 4.4: Observed and simulated transconductance characteristics of GaAs MESFETs. (The solid circles represent the experimental data (Figs. 4.3 (a) from [27]), dotted lines show the simulated characteristics using Ahmed et al.[1] model and solid lines show the simulated characteristics using the proposed model) 4.6.2 Output conductance Output conductance () represents the change of drain-current ID with respect to drain-tosource voltage VDS. Equation of () is found by differentiating the equation of ID with respect to . In equation (4.4), the value of simulates the finite output conductance of nanometer MESFETs in the saturation region of operation. The magnitudes of output conductance (), can be evaluated from (4.4) and is expressed as follows: Output conductance derived from Mansoor et al. model [1].

(4.8) Output conductance derived from proposed model [16].

(4.9) The output conductance was measured for all the test devices and the comparison is showed in figure 4.4. It is obvious from the figure that the prediction of the experimental result using the proposed model is more accurate.

Figure 4.5: Observed and simulated output conductance characteristics of GaAs MESFETs. (The solid circles represent the experimental data (Figs. 4.3 (a), 4.3 (b), 4.3 (c) from [27], & 4.3 (d) from [26]), dotted lines show the simulated characteristics using Ahmed et al.[1] model and solid lines show the simulated characteristics using the proposed model) 4.7 Result Analysis

The RMS error for the four devices for different bias conditions as well as the average error for the overall analysis is compared between the proposed model and Mansoor et al. model. The comparison is shown in table 4.2 Table 4.2: a comparative list of RMS errors for four devices VGS Ahmed et al. Model [1] (Volts) Device of 0.0 Fig. 4. 3(a) -0.5 -01 -1.5 -02 Device of 0.0 Fig.4. 3(b) -.75 -1.5 -2.25 Device of 0.0 Fig.4. 3(c) -0.87 -1.75 -2.63 -3.5 Device of 0.0 Fig.4. 3(d) -0.7 -1.4 -2.1 -2.8

RMS Error

Avg. Error

0.6376 2.1696 4.9546 8.5496 10.0398 0.2017 1.5221 6.5649 .2780 2.1088 3.4199 6.4474 0.6360 12.8857 12.9505 0.4333

3.9901

0.9191 7.2179 24.3297

4.7426

7.8314

11.4001

Proposed Model [16]

RMS RMS Error 5.0816 0.4371 0.0543 0.7323 0.7109 0.1547 2.5223 4.9784 1.0830 4.7644 1.1636 4.0356 1.3365 4.4781 6.4343 6.1966

Avg. Error

RMS

1.6522

3.3827

4.4013

4.8620

0.2497 6.3223 6.6529

The accuracy of predicting the transconductance and the output conductance with the proposed model is also revealed here. And for better perception of the model the results are also compared with the existing model. Table 4.3: RMSE in predicting transconductance () for the four deice and a comparison with the previous model:

Ahmed et al Model[1]

Proposed Model [16]

Device of Fig. 4. 3(a)

27.2537

10.4828

Device of Fig. 4. 3(b)

33.0719

32.3289

Device of Fig. 4. 3(c)

41.3609

41.5176

Device of Fig. 4. 3(d)

32.1028

27.9737

Table 4.4: RMSE in predicting output conductance () for the four deice and a comparison with the previous model: Ahmed et al Model[1] Proposed Model [16] Device of Fig. 4. 3(a)

8.3814

6.1343

Device of Fig. 4. 3(b)

13.4570

13.7368

Device of Fig. 4. 3(c)

30.9387

29.8947

Device of Fig. 4. 3(d)

99.6479

91.1625

As in our proposed model we consider the effects of gate bias, V GS; in saturation region this model infers better precision. Furthermore in hyperbolic function, considering the effect of V GS; in subthreshold region simulated denouement is more akin to observed result. And on the whole the RMS errors for I-V characteristics are abated for all devices. Even for output conductance and transconductance better upshot is obtained. From table of errors, it is obtrusive that proposed model predict I-V model of GaAs MESFETs with paramount efficacy.

CHAPTER 5 NONLINEAR I-V CHARACTERISTIC MODEL OF SiC MESFETS In this chapter, an improved DC I-V characteristic model for high power SiC MESFETs has been developed. The accuracy of the proposed model to predict the behavior of the device is also demonstrated with necessary comparison with the experimented data.

5.1 INTRODUCTION Silicon Carbide (SiC) has been known investigated since 1907 when Captain H. J. Round demonstrated yellow and blue emission by applying bias between a metal needle and a SIC crystal. In 1923, a Russian scientist, Oleg Losev, discovered two types of light emission from SiC - the emission that we would now call "pre-breakdown" light and the electroluminescent emission. The potential of using SiC in semiconductor electronics was already recognized about a half of century ago. The most remarkable SiC properties are: •

Wide band gap (3 to 3.3 eV for different poly types )

•

Very large avalanche breakdown field (2.5 - 5 MV/cm)

•

High thermal conductivity (3 ~ 4.9 W/cm K)

â&#x20AC;˘

High maximum operating temperature (up to 1,000 "C)

â&#x20AC;˘

Chemical inertness and radiation hardness

The first commercial SiC devices - power switching Schottky diodes and high temperature MESFETs - are now on the market.

For nitride based devices, silicon carbide has become a substrate of choice, because of its excellent thermal conductivity and decent lattice match. This includes both electronic and blue light emitting diodes and lasers, and, together with nitride based semiconductors, silicon carbide is now in the forefront of the semiconductor research. They have demonstrated their suitability for Phased Array Radar (PAR) applications by nature of their high power performance and good pulse stability. These latest results confirm their performance and demonstrate improved device stability and therefore process maturity.

SiC based power MESFET has attracted considerable attention for applications in high power and high frequency electronic devices. Though there are some existing models to express the DC characteristics of SiC MESFETs, they have their limitations. An improved compact non-linear DC IV characteristic model for SiC MESFETs is proposed here. This is the slightly modified version of an existing model proposed by M.M Ahmed known as Ahmed et al. model. [1] But this model was developed for GaAs MESFETs. The model is adapted for SiC MESFETs by incorporating the self heating effects. With limited number of model parameters, the model is now capable to predict the DC I-V characteristics of high power SiC MESFETs with pulse-gate condition as well as self-heating effects. And the results were compared with the experimented observation which proves the accuracy of the model.

5.2 Self Heating of SiC devices Self heating effects in high power SiC devices have been investigated by electro-thermal simulations. Self-heating is a local increase of crystal temperature due to dissipated Joule electric power. The self-heating effects reduce the electron mobility at the drain-side gate edge, thus degrading the device performance and causing the Negative Differential Conductance (NDC) in the I-V curves. In table 5.1 the thermal conductivity of different materials is given.

Table 5.1: Thermal conductivity of materials (Unit: W/cmK). GaN AlGaN AlN SiC

Sapphire

1.30

0.33

2.86

4.0

4.9

To estimate the full thermal characteristics, it is important to calibrate the lumped external thermal resistance, (K/Wcm2). In other words, the current produced in the devices generates some heat which reduces the current carrying capability of the device. So the current reduces changing the amount of generated heat with it. The NDC depends on the substrate material. A comparison between SiC and Sapphire substrate is shown below in figure 5.1.

Figure 5.1: comparison of drain current and transconductance with gate-to-source voltage for SiC and Sapphire devices As observer from the above I-V curve and transconductance characteristics, the Sapphire substrate exhibit stronger NDC compared to the SiC, because the Sapphire thermal conductivity is smaller.

5.3 Pulse Gate condition In this approach, a pulse voltage is applied to the gate of the device. The duration of this pulse is normally small and it can not generate a necessary amount of heat that can change the mobility of the device material. In this case the current is not degraded as it was suppose to while simulating a high power SiC device due to self heating effect. So the SiC MESFETs will act as conventional MOSFETs under pulse gate condition.

5.4 MODEL DEVELOPMENT To simulate the I-V characteristics as a function of and of a uniformly doped GaAs MESFET, the following relationship has been reported in Ahmed et al. model [1]: (5.1) Where = the drain saturation current when = 0V = threshold voltage = the geometric shift in threshold voltage. Îą = parameter that determines the drain voltage where the drain current characteristic saturates Îť = parameter that determines the slope of the I-V curve in saturation region. Îł = parameter that simulates the effective threshold voltage displacement as a function of

The above model was modified in order to express the characteristics of SiC MESFETs. Some necessary points were kept in mind while changing the parameters such as i.

The high drain operation voltage derived from high critical breakdown voltage

ii.

The knee voltage varied greatly with the applied gate voltage due to wide linear operation region

iii.

The large pinch-off voltage designed mostly to allow wide signal swing

iv.

Self heating effect generated from high power application in spite of SiC material has high thermal conductivity.

The proposed DC I-V characteristics model [14] for SiC MESFETs is presented by the following relationship: (5.2) (5.2.1) (5.2.2) (5.2.3) (5.2.4) (5.2.5) (5.2.6) (5.2.7) (5.2.8)

Where = effective gate to source voltage , , , , , = the model fitting parameters that are found from the simulation without considering the self heating effect .These are the parameters with optimum values found from the simulations assuming pulse gate condition = drain saturation current when = 0V = threshold voltage at =0 Volt = parameter that simulates the effective threshold voltage displacement as a function of = parameter that determines the voltage where the drain current saturates = the non-zero drain conductance = the parameter to present modification of gate-source voltage to consider the effect of p-buffer layer and substrate , , , , , = temperature dependent parameters considering the self heating effect. = thermal resistance = temperature raise induced by self-heating effect

5.5 Measured and Modeled I-V Characteristics A simulator was designed using MATLAB to employ expressions given in previous equations to simulate the I-V characteristics. The optimum values of the parameters were found out by comparing the simulated results with the experimented results. The set of parameter values were used for which the root mean square error (RMSE) is minimized. The RMSE can be expressed by the formula 5.3

(5.3) Where

= drain to source current found from the simulation = drain to source current found from experimental analysis N = total number of entities

5.6 The Algorithm behind the Model Equation The algorithm that calculates the optimum values for the parameters is shown in figure 5.2 Figure 5.2: Flowchart for the optimization of proposed model [14] parameters

5.6.1 Pulse gate condition The algorithm is designed as to choose the best possible set of values for the parameters resulting minimum RMSE. The manipulation is done in two steps. The first part determines the optimum values for , , , , , . This section simulates the I-V characteristics without considering the self heating effect. At first an approximate initial value is set to each parameter. Then the simulator calculates the drain current for all possible combinations of these parameters within the defined range. This process is repeated for different set of data for different values of gate to source voltage (). The simulated values of the drain current are then compared with the experimented results. The deviation is measured in terms of RMSE and the minimum value of RMSE searches out the best possible combination of , , , , , . This calculates the optimal output characteristics. Figure 5.3 is the IV characteristics comparison between the proposed model and the experimental data under different gate bias. (a) pulsed-gate I-V characteristics without self-heating effect and (b) static I-V characteristics with self-heating effect

Figure 5.3 (a): I-V characteristics sample device for pulse gate condition (compared with the experimental data [10]) Figure 5.3 (b): I-V characteristics sample device for static condition (compared with the experimental data [10] 5.6.2 Static Condition In the next step, these optimum values are used to generate the remaining parameters , , , , , . The simulated result was compared to the static I-V curves with self heating effect. A new parameter is introduced here. It is termed as thermal resistance. The rest of the parameters were extracted using simple iteration process for different values of . As seen in the equation, the value of depends on some parameters which are function of where itself depends on . This is known as a self consisting equation. The solution was to presume an arbitrary value of which will generate a corresponding value of . This value of was used to calculate the resultant value of . Iterating the value of and observing the deviation with respect to the presumed value will sort out the solution of the equation. The obtained result is plotted for different values of bias voltage (). Compared with the pulse-gate I-V curves, the static I-V characteristics have obvious negative differential conductance induced by self-heating effect. The optimized model parameters are shown in Table 5.2.

Table 5.2: the optimum parameter values obtained from the proposed model [14] Parameters Optimum Value

5.7 Error comparison

It can be seen that the proposed model has excellent agreement with experimental data in a wide and operation regime for both pulse and static conditions. In order to have a better understanding on the accuracy of the proposed model, The deviation of the drain current is also plotted with respect to drain to source voltage () under different bias () conditions. The plot is given below in figure 5.4(a) pulsed-gate condition without self-heating effect and (b) static condition with self-heating effect. It is shown that the proposed model has a small deviation in the whole region for both pulse and static conditions and the saturation region has better accuracy than the linear region.

Figure 5.4(a): drain current deviation of the proposed model [14] with the experimented value for pulsed-gate condition Figure 5.4(b): drain current deviation of the proposed model with the experimented value for static condition According to the above analysis, it can be expected that, combined with models of parasitic, capacitance and diode, the proposed DC I-V model can be used to accurately predict large- and smallsignal characteristics for high power SiC MESFETs.

5.8 Result Analysis The proposed model has better accuracy in the saturation region. The I-V characteristic curve explains that the model approximates the drain current of almost exact value as obtained from the experimental analysis. The error curves shows that the deviation is smaller for larger negative gate voltage. The RMSE for different values of gate voltage is shown in table5.3 for both pulse gate and static condition. Table 5.3: Root mean square error against different gate voltage for both pulsed-gate and static condition Gate to source voltage = (volt) Pulse gate condition static condition (without self heating (considering self effect) heating effect) 0

0.020013

-1

0.015074

-2

0.014931

-3

0.015809

0.0179

-4

0.016247

0.009958

-5

0.014976

0.007821

-6

0.012048

0.007511

-7

0.009742

0.008188

-8

0.008824

0.012418

-9

0.005218

0.005663

The table explains better accuracy of the model for larger gate bias condition. According to the above analysis, it can be projected that the proposed DC I-V model can be used to accurately predict largeand small-signal characteristics for high power SiC MESFETs.

CHAPTER 6 CONCLUSIONS AND SUGGESTIONS This chapter reviews the gist of this dissertation and mentions some of the future aspects of the effort. 6.1 Conclusions In this dissertation, numerous models of MESFETs have been analyzed and by modifying the Ahmed et al. model, two different models have been developed for the modeling of I-V characteristics of nanometer range GaAs MESFETs and SiC MESFETs. For this purpose two algorithms have been developed for two different models. Both of these algorithms have been used root mean square (RMS) error to compare the simulated results with observed values. Using these algorithms, data were generated and optimum sets of model parameters have been determined for different devices of GaAs and SiC MESFETs. Simulations have been done for devices with contrasting aspect ratios and bias voltages. For the GaAs MESFETs, emphasize has been given on the effect of on the drain current and output conductance. I-V characteristic has been predicted precisely in saturation region considering the effect of . Also the effect of gate-to-source voltage is considered for output conductance and higher accuracy is achieved from modified model. For the SiC MESFETs the I-V characteristic has been deduced considering both the self-heating effect and pulse gate condition. Due to self-heating, the performance of devices degrades and this effect has been taken into account in the model. The results of proposed models are compared with the experimental results and fine harmony has been found. Therefore, these models can be used in future to design nanometer range MESFETs.

6.2 Suggestions for Future Work Some specific recommendations based on the present work are as follows:

1. The present study can be well extended for GaN MESFETs that has a much higher switching frequency with low losses.

2. A lot of scope lies in studying the junction capacitance. 3. The characteristics of the device in sub threshold region can be considered into the present model

4. The model can be analyzed to make it more compact with less number of parameters while maintaining the accuracy.

References [1]

M. M. Ahmed, H. Ahmed and P. H. Ladbrooke, “An improved DC model for circuit analysis programs for submicron GaAs MESFETs,” IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 360-363, March ,1997

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[10]

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[12]

Curtice, W.R. Ettenberg, M.,”A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers”, Microwave Symposium Digest, MTT-S International, Jun 1985 Volume: 85, Issue: 1,On page(s): 405- 408

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[14]

M. S. Islam, Muhymin Islam, Raziul Hasan and S. M. Naeemul Islam, ”An Improved DC I-V Characteristics Model for SiC MESFETs Incorporating Self-Heating Effect “

[15]

Arns, R.G.: The other transistor: early history of the metal–oxide–semiconductor field-effect transistor. Engineering Science and Education Journal Volume 7, Issue 5, Oct 1998 Page(s):233 - 240

[16]

M. S. Islam, Muhymin Islam, Mohammad Raziul Hasan and S. M. Naeemul Islam, ”An Improved Nonlinear I-V Characteristics Model for Nanometer Range GaAs MESFETs “

[17]

A.G. Baca, Carol Iris Hill Ashby, “Fabrication of GaAs devices”, Institution of Electrical Engineers, Chap 8

[18]

Shur, M.S., “Analytical model of GaAs MESFET's”, Electron Devices, IEEE Transactions on Jun 1978,Volume: 25, Issue: 6,On page(s): 612- 618

[19]

E.F. Schubert, “JFETs and MESFETs”, Rensselaer Institute, 2003

[20]

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[21]

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[22]

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Ladbrooke PH, MMIC Design: GaAs FETs and HEMTs, Artech House, Boston and London 1989; 99-127.

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M. M. Ahmed, "Optimization of active channel thickness of mm-wavelength GaAs MESFETs by using a nonlinear I-V model, "IEEE Trans. Electron Devices, vol. 47, pp. 299-303, Feb. 2000

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[29]

Evaluation of Commercially Available SiC MESFETs for Phased Array Radar Applications, Mark G. Walden & Mathew Knight, Roke Manor Research Ltd., Roke Manor, Old Salisbury Lane

MESFETs

List of publications 1. M. S. Islam, M. Islam, M. R. Hasan, S. M. N. Islam, “An Improved DC I-V Characteristics Model for SiC MESFETs Incorporating Self-Heating Effect” Proc. IEEE Regional Symposium on Micro and Nano Electronics, 2009 (IEEE-RSM2009), Kota Bahru, Malaysia, pp: 204-208, 2009.

2. M. S. Islam, M. Islam, M. R. Hasan, S. M. N. Islam, “An Improved Nonlinear DC I-V Characteristics Model for Nanometer Range GaAs MESFETs”, TENCON 2009, November 23-26, 2009, Singapore (accepted). Appendix Sample MATLAB codes used for simulation: Optimization of parameter of SiC MESFET model for pulse gate condition: Vgs1=[…]; % [……] means array of data either found experimentally or in simulation Vds1=[…..]; Ids_prac=[…..]; row=length(Vds1(:,1)); %i col=length(Vds1(1,:)); %j ers=10; for alpha_0=1.7:.01:1.85 for n_0=-.035:.001:-0.03 for Y_0=-.07:.01:-0.05 for lambda_0=4e-3:1e-3:6e-3 for vt_0=-12.3:.01:-12.2 for Idss_0=1.4:0.01:1.48 for i=1:row for j=1:col Vgs=Vgs1(i); Vds=Vds1(i,j); Vgseff=Vgs*(1+tanh(n_0*Vgs)); R=alpha_0*Vds/(Vgs-vt_0); Ids(i,j)=Idss_0*(1-(Vgseff/(vt_0+Y_0*Vds)))^2*tanh(R)*(1+lambda_0*Vds); err(i,j)=(Ids_prac(i,j)-Ids(i,j))^2; errr(i,j)=(Ids_prac(i,j)-Ids(i,j)); end end sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end error=(sum/(row*col))^.5; if ers>error ers=error; Ybest=Y_0; nbest=n_0; alphabest=alpha_0; vtbest=vt_0; lambdabest=lambda_0; Idssbest=Idss_0; end end end end end end

end for i=1:row for j=1:col Vgs=Vgs1(i); Vds=Vds1(i,j); Vgseff=Vgs*(1+tanh(nbest *Vgs)); R= alphabest *Vds/(Vgs- vtbest); Ids(i,j)= Idssbest *(1-(Vgseff/(vtbest + Ybest *Vds)))^2*tanh(R)*(1+ lambdabest*Vds); err(i,j)=(Ids_prac(i,j)-Ids(i,j))^2; errr(i,j)=(Ids(i,j)-Ids_prac(i,j)); end end sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end error=(sum/(row*col))^.5; plot(Vds1,Ids) plot(Vds1,Ids_prac) plot(Vds1,errr) Optimization of parameter of SiC MESFET model for static condition: Vgs2=[…..]; Vds2=[…..]; Ids_prac2=[…..]; row=length(Vds2(:,1)); col=length(Vds2(1,:)); ers=0.2; alpha_0= alphabest n_0 =nbest; Y_0= Ybest lambda_0= lambdabest vt_0= vtbest Idss_0= Idssbest for alpha_T=0.01:0.01:0.055 for n_T=0:0.5e-6:2e-6 for Y_T=8e-4:1e-4:10e-4 for lambda_T=-5e-5:1e-5:-3e-5 for vt_T=-0.07:0.01:-0.05 for Idss_T=-5e-3:1e-3:-3e-3 for Rth=2.40:0.01:2.45 for i=1:row for j=1:col Vgs=Vgs2(i); Vds=Vds2(i,j); deviation=1; for Ids_temp=0.001:0.01:1 Tsh=Ids_temp*Vds*Rth; alpha=alpha_0+alpha_T*Tsh;

n=n_0+n_T*Tsh; Y=Y_0+Y_T*Tsh; lambda=lambda_0+lambda_T*Tsh; vt=vt_0+vt_T*Tsh; Idss=Idss_0+Idss_T*Tsh; Vgseff=Vgs*(1+tanh(n*Vgs)); R=alpha*Vds/(Vgs-vt); Ids_final=Idss*(1-(Vgseff/(vt+Y*Vds)))^2*tanh(R)*(1+lambda*Vds); if ( abs(Ids_temp-Ids_final)<deviation ) Ids(i,j)=Ids_final; deviation=abs(Ids_temp-Ids_final); end end err(i,j)=(Ids_prac2(i,j)-Ids(i,j))^2; errr(i,j)=(Ids(i,j)-Ids_prac2(i,j)); end end sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end error=(sum/(row*col))^.5; if ers>error ers=error; Ybest=Y_T; nbest=n_T; alphabest=alpha_T; vtbest=vt_T; lambdabest=lambda_T; Idssbest=Idss_T; Rthbest=Rth; end end end end end end end end for i=1:row for j=1:col Vgs=Vgs2(i); Vds=Vds2(i,j); deviation=1; for Ids_temp=0.001:0.001:1 Tsh=Ids_temp*Vds*Rthbest; alpha=alpha_0+ alphabest*Tsh; n=n_0+ nbest*Tsh; Y=Y_0+ Ybest*Tsh; lambda=lambda_0+ lambdabest*Tsh; vt=vt_0+ vtbest*Tsh;

Idss=Idss_0+ Idssbest*Tsh; Vgseff=Vgs*(1+tanh(n*Vgs)); R=alpha*Vds/(Vgs-vt); Ids_final=Idss*(1-(Vgseff/(vt+Y*Vds)))^2*tanh(R)*(1+lambda*Vds); if ( abs(Ids_temp-Ids_final)<deviation ) Ids(i,j)=Ids_final; deviation=abs(Ids_temp-Ids_final); end end err(i,j)=(Ids_prac2(i,j)-Ids(i,j))^2; errr(i,j)=(Ids(i,j)-Ids_prac2(i,j)); end end sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end error=(sum/(row*col))^.5; plot(Vds2,Ids) plot(Vds2,Ids_prac2) plot(Vds2,errr) Optimization of parameter of GaAs MESFET model: Vgs1=[…..]; Vds1=[…..]; Ids_prac=[…..]; Idss=192; vt0=-1; delvt=-1;

%device configuration

row=length(Vds1(:,1)); col=length(Vds1(1,:)); ers=100; for T=-1.35:.01:-1.25 for alpha=1.72:.01:1.8 for lambda=.08:.01:.10 for gamma=-.4:.01:-.30 for X=.34:0.01:.4 for i=1:row for j=1:col Vgs=Vgs1(i); Vds=Vds1(i,j); Ids(i,j)=Idss*((1-(Vgs/ (vt0+delvt+gamma*Vds)))^2)*tanh(alpha*Vds+T*Vgs*Vds)*(1+lambda*Vds+X*Vgs); err(i,j)=(Ids_prac(i,j)-Ids(i,j))^2; end end

sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end error=(sum/(row*col))^.5; if ers>error ers=error; alphabest=alpha; lambdabest=lambda; gammabest=gamma; Xbest=X; Tbest=T; end end end end end end for i=1:row for j=1:col Vgs=Vgs1(i); Vds=Vds1(i,j); Ids(i,j)=Idss*(1-(Vgs/(vt0+delvt+ gammabest *Vds)))^2*tanh(alphabest *Vds+ Tbest *Vgs*Vds)*(1+ lambdabest *Vds+ Xbest *Vgs); err(i,j)=(Ids_prac(i,j)-Ids(i,j))^2; end end sum=0; for i=1:row for j=1:col sum=sum+err(i,j); end end plot(Vds1,Ids); plot(Vds1,Ids_prac);