Field Effect Transistor Experiment Abstract The characteristics of a Field Effect Transistor (FET) would be measured by this experiment. “The field-effect transistor (FET) is a transistor that relies on an electric field to control the shape and hence the conductivity of a 'channel' in a semiconductor material.” ①

FET is a

semiconductor device that can control electric current. The transistor used in this experiment is a Junction Field Effect Transistor (JFET). The three connections to the JFET are showed in the figure

②. The voltage between source and drain is called VDS and the voltage between the gate and the source is called VGS. Groups of data of current varied with VDS were obtained and a whole family of IV characteristics was obtained. By plotting the graphs, IDSS was found to be 2.41. Therefore, VP was computed to be 1.93.

PROCEDURE Set up the apparatus as shown below.

An n-channel JFET was connected to the control boxes, the potentiometers on the control box should be fully anticlockwise and the selector knob should in the OFF position. Turn on the power supply unit. The selector knobs switched between VGS, VDS and ID which are measured using the multimeter. Began with VGS=0, -0.2, -0.4, -0.6, -0.8, 1. and varied VDS. Measure the corresponding ID. Plot the family of IV characteristics obtained and plot the transconductance

curve for the device. Used the family of IV characteristics to find the value to IDSS and IDMAX. IDSS was the biggest value of IDmax and IDmax was the maximum value of each group’s ID. Used both the tangent method and the straight line plot method to find the value of VP.

CALCULATIONS & RESULTS The table of family of IV characteristics is shown in the appendix. Vgs=0

Vgs=-0.2

Vgs=-0.4

Vgs=-0.6

Vgs=-0.8

Vgs=-1

Vds/V

Id/mA

Vds/V

Id/mA

Vds/V

Id/mA

Vds/V

Id/mA

Vds/V

Id/mA

Vds/V

Id/mA

0.20

0.47

0.20

0.41

0.20

0.36

0.20

0.30

0.20

0.25

0.20

0.20

0.40

0.88

0.40

0.77

0.40

0.66

0.40

0.56

0.40

0.45

0.40

0.34

0.60

1.22

0.60

1.07

0.60

0.91

0.60

0.75

0.60

0.60

0.60

0.44

0.80

1.52

0.80

1.32

0.80

1.11

0.80

0.91

0.80

0.69

0.80

0.49

1.00

1.78

1.00

1.51

1.00

1.26

1.00

1.01

1.00

0.75

1.00

0.52

1.20

1.97

1.20

1.66

1.20

1.36

1.20

1.07

1.20

0.78

1.20

0.53

1.40

2.13

1.40

1.77

1.40

1.43

1.40

1.11

1.40

0.80

1.40

0.54

1.60

2.24

1.60

1.85

1.60

1.48

1.60

1.14

1.60

0.82

1.60

0.54

1.80

2.32

1.80

1.90

1.80

1.51

1.80

1.16

1.80

0.83

1.80

0.54

2.00

2.37

2.00

1.93

2.00

1.53

2.00

1.17

2.00

0.84

2.00

0.54

2.20

2.41

2.20

1.95

2.20

1.55

2.20

1.18

2.20

0.84

2.20

0.54

2.40

2.41

2.40

1.95

2.40

2.60

2.42

2.60

1.96

2.60

The graph of the IV family characteristic is shown in the appendix. Table of √(Idmax/Idss) is shown below: Transconductance equation: IDmax=IDSS((1-VGS)/VP)2 Expanding and rearranging: √(IDmax/IDSS)=1-(VGS/VP)

Multiply all terms by VP: VGS= -Vp*√(IDmax/IDSS)+VP IDSS=2.41 A table of √(IDmax/IDSS) was obtained: Vgs/V

Idmax/mA Idmax/Idss

√(Idmax/Idss)

0.00

2.41

1.00

1.00

-0.20

1.95

0.81

0.90

-0.40

1.55

0.64

0.80

-0.60

1.18

0.49

0.70

-0.80

0.84

0.35

0.59

-1.00

0.54

0.22

0.47

The graph of VGS VS IDmax is shown in the appendix. Using the tangent method to calculate the value for VP: Points are (-0.85,0.7) & (-0.20,1.90) The slope of the tangent is: (1.90-0.7)/(0.85-0.2)=1.846 Using the straight line plot method to calculate the value for VP: Points are (0.48,-1.00) & (0.90,-0.20) (1.00-0.20)/(0.90-0.48)=1.905

DISCUSSION & CONCLUSIONS In a JFET, the current was never pinched off totally but it reached a saturation level instead. As the drain bias starts to increase, the device will start to pinch off near the drain end of the gate. This response will also increase the resistance as a larger depletion zone will obstructs more flow of electrons. The depletion zone was growing and at a time it reached a point where the resistance of JFET reached its maximum value. Meanwhile, VDS=IR and VDS is not zero, it could not be zero. So the current I could not be zero even the resistance R was large. The depletion layer taper to its maximum value at the drain end of the JFET, this is because the reverse bias occurred. The p-type region was connected to the negative terminal and the n-type region was connected to the positive terminal. Electrons would therefore be drawn towards the terminals and the depletion region would be enlarged. Current would flow through the channel as the VGS increased and the current would travel from the source to the drain as the reverse bias rose. Higher reverse bias caused a thicker

depletion layer at the drain then at the source end. The value of the pinch off voltage decreases as the gate voltage is increased. The reason for this was, P-type became more negative and the depletion zone would increase. Therefore, the resistance increased. At the same time, VGS increased, and ID decreased. V=IR, as I decreased, VPS decreased. Therefore, the value of the pinch off voltage VPS decreased as the gate voltage VGS was increased. The width of the n-type channel in the JFET can be calculated as follow: Dielectric constant of silicon= 1.065 × 1010 F/m=ε Charge on an electron= 1.602 × 10 15

−19

C=q

Donor Concentration= 10 electrons/cm =Nd=109

Vp =

3

qNda 2 2E

1.9=（1.602*10-19*109*a2）/(2*1.065*10-10)=1.60m