XCELL SOFTWARE JOURNAL: XCELLENCE WITH SDSOC
Figure 5 — SDSoC-generated performance, speedup and resources estimation report
Figure 6: Vivado HLS synthesis estimation report 26
including the FPGA bitstream and the application binary of the software-only version. We boot from this SD card and run the application on the ZC702 target platform. Once Linux has booted on the board, we can execute the software-only application, and the SDSoC environment then generates the performance estimation report of Figure 5. We see both the FPGA resources utilization (26 DSP, 80 BRAM, 15,285 LUT, 17,094 FF) and the performance speedup (1.75) of the cholesky_alt_top function if executed in hardware instead of software. We can also see, from the main application point of view, that the overall speedup is lower (1.23) because of other software overhead such as malloc and data transfer. Our complete application is indeed small, focusing mainly on illustrating the SDSoC flow and design methodology; we would need more routines to be accelerated in the PL, but that is beyond the scope of this article. Using the SDSoC environment, we have generated this information in a few minutes without requiring synthesis and place-and-route FPGA compilation; those processes could take hours, depending on the complexity of the hardware system. Estimations like this one are often enough to analyze the system-level performance of hardware-software partitioning and let users very rapidly iterate a design to create an optimized system.