X P L A N AT I O N : F P G A 1 0 1
Using Formal Verification for HW/SW Co-verification of an FPGA IP Core A new formal-verification technique allowed a group of academic and industry researchers to holistically verify tightly coupled hardware and firmware within a Xilinx soft core.
by Markus Wedler Prof. Dr.-Ing. Berlin Institute of Technology email@example.com Eric Crabill IP Design Engineer Xilinx, Inc. firstname.lastname@example.org Graham Schelle Senior Staff Research Engineer Xilinx, Inc. email@example.com Patrick Lysaght Senior Director Xilinx, Inc. firstname.lastname@example.org
n ever-growing number of productsâ€”from mobile devices to automobiles to industrial machineryâ€”employ sophisticated processing in which hardware and software function together to perform a range of remarkable tasks. But as these systems become more complex, their designers face growing challenges in verifying that the hardware and software work together properly. Over the past few decades, companies and researchers have created a number of ways to verify the proper functioning of both hardware and software. But the ability to verify that the two will work together as intended is very challenging. For well over a decade, one of the most promising technologies design teams have employed to verify the correctness of their hardware has been a technique called formal verification. Intel, for example, recently revealed that this was the methodology its engineers adopted after rectifying the costly floating-point unit problem it had with its Pentium I microprocessor in the 1990s.  Formal verification has since gained adherents at Intel and many other hardware design groups, although it remains something of a niche methodology. But formal techniques for HW/SW co-verification are still not widely used in industry.
Second Quarter 2012
Xcell Journal issue 79’s cover story details Xilinx releasing its new Vivado Design Suite to enable higher levels of user productivity for t...