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First Year - Issue 3 - October 2012

Field Programmable Analog Arrays

Research Inspiring Innovation

Ultra Wide Band

Japan EDA Insight Integrated Optical RX



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Editorial Word

Welcome to VLSI Egypt magazine

4 Japan EDA Insight ASIP Solutions


Integrated Optical Receivers

10 A Magazine by VLSI Egypt Editor in Chief

Ahmad Ibrahim


Research Inspiring Innovation The next Big "Small Thing"

Field Programmable Analog Arrays A brief history


Why Do we need UWB?

23 26

Editorial Team

Mohamed Atef Muhammad El-Khashab Khaled Kabil Ahmad Abou El-Saoud Hussein Ali Website Contacts VLSI-Egypt is a nonprofit, service oriented, community based NGO



The maturity and performance of standard CMOS technologies make the optoelectronics integrated circuits (OEIC) a competitive solution for many low-cost consumer and sensor applications


Optical Integrated Receivers

Editorial Word Welcome to the Third Issue ofVLSI Egypt magazine Presenting the third issue of VLSI Egypt magazine is like a dream coming true. The great feedback and interaction we had received from the community has been overwhelming and has allowed us to continue and sustain this activity and develop it even further.


First of all, we would like to thank all the authors who contributed and all those who contacted us with feedback and offered their help. We would also like to encourage any those interested in writing articles, whether they are business, technical or educational, to contact the editorial group and we would be more than happy to answer any of your inquiries.



This issue of VLSI Egypt covers a whole new set of topics in addition to the continuation of previously initiated series. We continue our series on EDA in Japan with the story behind the ASIP Meister design tool. The series on current trends in RF and Microwave and IC research continues with a discussion on why we need UWB. In this issue we give an overview about the analog counterpart of FPGAs, that is Field Programmable “Analog� Arrays (FPAAs) and its history. A historical overview of Arduino and its evolution and a brief article on integrated optical receivers are also presented. A discussion on the goals and objectives of research and how new research associates with new business opportunities is presented through an article discussing the research and motives of innovation. We also present a detailed guide on Scholarships, Tuition and Graduate studies in the European Union. This issue also contains the first articles written in Arabic as opposite to all-English issues previously published. We hope you find this issue of VLSI Egypt interesting and useful. We would also like to ask you to update us with all your feedback, opinions and comments as this is how we asses our progress and success. Finally we would like to thank you all very much for your interaction, support and for keeping VLSI Egypt such a dynamic community.



State of the Art


EDA Insight (2) By: Mohamed AbdElSalam As we set in our first article, Japan EDA Insight will focus on an Insight “small piece of information” topics that vary from the Educational System in Universities, Research Organizations, Design Tools, Hardware Platforms, and many other EDA trends, based on my experience living and studying in Japan, which I truly hope that VLSI-Egypt magazine readers find useful and interesting. In this article I would present one of most powerful tools in processor design which my Prof. Masaharu Imai architected through years of effort and collaboration from different lab members and ended in a spin out as a commercial tool known as ASIP Meister - An EDA tool for drastically reducing the design time 4


of Application Specific Instruction Set Processors (ASIP). I would mainly reference the company web site located at and conference publications to introduce this tool to VLSI-Egypt magazine readers. Different Processor Technologies

Processor technologies vary in their customization for the problem at hand, so assume that you have the functionality described by the program in Figure 1. You can typically design a processor which exactly do this functionality and nothing else (we call this Single Purpose Processor – note the shape match), a

processor driving a baby bear toy hitting a drum is one example. Or, you can design a processor that executes the desired functionality and extends this to all problems with same nature, we call them Application Specific Instruction Set Processors (ASIPs), a Digital Signal Processor (DSP), a Vide co-processor and a Micro Controller are examples of these kind of ASIPs. Or, you can design a processor that executes any kind of problem at hand (note again the shape) and these are desktop/laptop processors or what we call General Purpose processors. In depth, the main difference is in the architecture of the computation engine used to implement the desired functionality. For a single purpose processor,

Fig.1 Different Processor Technologies – A Simple View as shown in Figure 1, it contains only the components needed to execute a single program - you would find just few registers and a fixed control logic with a small data memory and no program memory, its merits are speed, low power and small die size. For an application specific processor, you would have an optimization for a particular class of applications having common characteristics as we stated, so you would find more registers, a program memory with Instruction Register (IR) and Program Counter (PC), a separate Data/Program memory and a custom Arithmetic, Lo-

gic, and Shift unit (ALU) with special functional units that solve specific application domain computations (signal processing, multimedia, control oriented). Its merits are more flexibility, good performance, size and power. On the other hands, the general purpose processor has a general purpose data path with large register file and general ALU, it has programmability using a Program/Data memory and IR/PC registers as ASIPs, its merits are high flexibility and high computation power.

Fig.2 ASIP Meister Design Flow concept behind an ASIP, let’s introduce ASIP Meister (Master in German).

Now, after we have understood the main

ASIP Meister generates dedicated proISSUE 3


Computer Design: VLSI in Computers & Processors, pp.430-436, September 2000.

Software Tools Generation S. Kobayashi, Y. Takeuchi, A. Kitajima, M. Imai, “Compiler Generation in PEAS-III: an ASIP Development System,” Proc. of SCOPES 2001, March 2001. Lessons To Learn

Figure 3. ASIP Meister: An ASIP Design Environment cessor hardware descriptions and software development tools automatically based on target processor specifications. You can easily get high flexibility for processor design only by modifying the processor specifications on user friendly ASIP Meister GUI. Design Flow with ASIP Meister

Lets’ summarize, the design flow with ASIP Meister (A Snapshot is shown in Figure 3) is as follows: 1. Set the design goals & architecture parameters of the target ASIP, such as the number of pipeline stages and instruction/data bit-width. 2. Select the hardware resources of the ASIP from (Flexible Hardware Model) FHM database library and set parameters for each resource. 3. Define ASIP storage specification & I/O interface. 6


4. Define the instruction type, format and exception information. 5. Check design quality with architecture-level estimation. 6. Describe the behavior of each instruction using ANSI-C like syntax. 8. Describe the micro-operation of each instruction per pipeline stage. 9. Check the performance with the generated HDL descriptions and software development tools. For more details, I would recommend to go to Japanese site of ASIP Solutions and use google translate (I see good translation results!!!) *References

Generation of HDL Description M. Itoh, S. Higaki, J. Sato, A. Shiomi, Y. Takeuchi, A. Kitajima, M. Imai, “PEASIII: An ASIP Design Environment,” 2000 IEEE International Conference on

In my opinion Japan’s, leading in embedded systems since the early days lies in the strong knowledge in (1) Processor design – we have many companies which developed their own processors SH/SuperH family from Renesas, M32R from Mitsubishi, etc. and still prefers to use over ARM/Intel based processors (2) Real Time Operating Systems – ITRON is a national project that aims to be in all embedded systems sold in Japan from vending machines (Jidohanbaiki), automotives, etc. and its evolution now lead to T-Kernel/T-Engine projects which are main cornerstones in Ubiquitous Japan (3) FPGA prototyping – as an economic way to spread IP design culture among students (4) Applying this knowledge in commercial embedded systems on large scale with government support to give preference to indoor embedded systems.

Dr. Muhammad Abdel-Salam Technical Lead, Mentor Graphics Emulation Division (MED)

Integrated Optical Receivers By: Mohamed Atef Optical absorption in a semiconductor material is the key-effect to convert optical power into an electrical current. This conversion is done by a photodiode which is the first stage in any optical receiver. Discrete photodiodes can be connected to transimpedance amplifier (TIA) chip in multi-chip packages by wire bonding or in heterogeneous integrated circuits. The discrete solution performance can be optimized separately by using photodiode and TIA from different technologies. The high costs due to complex production and assembly process, and potential noise sources and bandwidth reduction due to bonding pads and package pins are the main drawbacks. An alternative low-cost solution in the visible spectral range is the integration of photodiodes with the TIA and post amplifiers in standard CMOS and BiC-

Integrated Photodiode

Figure 1 PIN Photodiode structure MOS technologies. The maturity and performance of standard CMOS technologies make the optoelectronics integrated circuits (OEIC) a competitive solution for many low-cost consumer and sensor applications. OEIC give a better performance than discrete solutions because there are no bonding pads, no bond wires and no package pin parasitics between photodiode and amplifier input [1].

The integrated photodiode is the main component and the first stage in the integrated optical receiver. The photodiode converts the optical power into an electrical current. The photodiode should convert photons into charge carrier pairs with maximum efficiency and to transport them to the electrodes as fast as possible. Also the capacitance of the photodiode must be as low as possible to keep the high frequency loss of the photocurrent low to reach highest possible sensitivity. These demands are partially conflicting. So a trade-off is necessary, especially due to the wavelength dependence of the penetration depth. More details about the theory of integrated photodiodes can be found in [2, 3]. Depending on the specific application, the thickness of the intrinsic zone of the photodiode must be optimized; Figure 1 ISSUE 3


shows the structure of a PIN photodiode. For a good trade-off, the main parameters that must be known are the maximum data rate, the operating wavelength, type of photodiode and the maximum voltage available for the photodiode. A main characteristic of integrated optical receivers is the achievable sensitivity, which depends strongly on the responsivity of the photodiode and also the capacitance, so minimum capacitance and maximum responsivity lead to maximum sensitivity. This could be achieved by increasing the thickness of the intrinsic layer. But this contradicts to speed, since increasing the intrinsic layer thickness without increasing the reverse voltage would lead to a double penalty (quadratic dependence) since the electric field decreases and so the speed of the charge carriers decreases. Additionally the distance the charge carriers have to drift increases and so the whole transition time of the charge carriers increases dramatically. To solve this problem partially the voltage across the diode has to be increased according to the increase of the thickness of the intrinsic layer. The main goal is that the electric field is at a high constant level where the charge carriers travel with saturation drift velocity. In practice, however, the saturation velocity is not achieved in most cases due to limited available supply voltage. Often a certain data rate is given, so the photodiode has to achieve a certain riseand fall-time. In a first order approximation the necessary 10%-90% rise- and fall-time of the photodiode can be calculated from the formula (1) with td as the drift time through the intrinsic zone. (1) 8


When rise- and fall-time are nearly equal, then the formula (1) simplifies to formula (2) and gives approximately the drift-time of the charge carriers through the drift zone. In both cases the factor 3 indicates a conservative approximation and for an aggressive approximation the factor can be two.

converters are necessary in order to convert the photocurrent delivered by the photodiode into an output voltage

(2) The cut-off frequency of the PIN-photodiode can be estimated by: (3)

Under the assumption that the drift velocity reaches saturation (vs=107cm/s) the maximum allowable thickness of the intrinsic layer can easily be calculated by: (4) The necessary voltage for the PIN-diode can now also be calculated with the electric field where saturation occurs. (5) Transimpedance Amplifier

Photodiodes do not use any amplification effect and have responsivity (ratio of output current to input light intensity) that is for example ≤ 0.5A/W for a silicon photodiode at a light wavelength of 650nm. Therefore a combination of a photodiode with an amplifier is necessary in all practical applications. In optical receivers current-to-voltage

Figure 2 Simplest possibility of the preamplifier which is proportional to the input current. The transimpedance amplifier is the most suitable preamplifier configuration used in optoelectronic receivers. For most optical receiver applications these amplifiers need a high and also variable gain, high bandwidth, low noise and low input impedance. The main characteristics of transimpedance amplifiers are discussed in [3]. The preamplifier is used to convert the incoming photocurrent into an output voltage, which is amplified by the following stages. The simplest way to do this conversion is a resistor between the PD output and the supply voltage as shown in Figure 2. The preamplifier is one of the determining parts concerning the sensitivity and bandwidth of an optical receiver. The sensitivity mainly depends on the responsivity of the PD and the input referred noise current of the circuit. Due to the fact that the output current of the PD is the smallest signal in the circuit, this point is the most sensitive concerning noise. The signalto-noise ratio is most critical at the input node of the preamplifier. Therefore, the noise of the preamplifier is the dominating part of the input referred

noise current. Again the noise of the resistor R and the first amplifying stage are the deciding factors. The most interesting characteristics of the preamplifier, therefore, are the

Let us compare the small-signal transfer functions of the two structures in Figure 2 and Figure 3, which is the transimpedance gain vo/iin. From Figure 2 (6) From Figure 3 (7)

Figure 3 Basic circuit of a TIA as preamplifier bandwidth and the input referred noise of the circuit. For the simple receiver shown in Figure 2 the bandwidth is indirectly related to the capacitance of the input node and the resistor R. In this simple model, the capacitance of the input node consists of the capacitance of the PD, and the input capacitance of the amplifier. To achieve a high bandwidth therefore the resistance R has to be small, as well as the capacitance of the input node. The noise of the circuit shown in Figure 2 depends also on the resistor R, the capacitance of the input node and the first amplifier stage of the following amplifier. To achieve high bandwidth the resistor R must be small and therefore its noise current dominates the sensitivity of the optical receiver. With a more complicated circuit, for example a TIA, a better performance can be achieved. Shunt­Shunt Feedback TIA

Figure 3 shows the basic circuit of a shunt feedback TIA as a preamplifier. In the TIA circuit CT consists of the capacitance of the PD and the input capacitance of the TIA.

The DC transimpedance gain for the simple TIA in Figure 2 is the transimpedance resistor value Rfb. For high amplifier gains A0 this is also the case for Figure 3. Comparing the frequency behavior, the dominant pole which defines the small-signal bandwidth for the two circuits are defined by: From Figure 2 (8) From Figure 3 (9) Equation (8) shows, that the bandwidth of the simple resistor TIA is completely defined by a given transimpedance and photodiode capacitance. Equation (9) shows that the shunt-shunt feedback TIA has an approximately A0 times higher bandwidth compared to a simple resistor TIA. The amplifier gain A0 is design dependent and higher than 1 for frequencies up to the amplifier’s transit frequency ft. Therefore the increased bandwidth for the same transimpedance value is one of the most important ad-

vantages of a shunt-shunt feedback TIA compared to a simple resistor solution. The advantage of a shunt-shunt feedback TIA compared to the simple circuit described before is the fact that the bandwidth is indirectly related to the resistor Rfb divided by the open-loop gain A0 of the TIA (Rfb/A0). Therefore the noise can be decreased for a given bandwidth, because of a large resistor RF. The smaller CT and the larger Rfb, the higher the sensitivity is for a given responsivity (more discussion will be presented in the next articles). For a high bandwidth it is important to have small CT and small Rfb. CT is dominated by the PD capacitance, a trade-off between sensitivity and bandwidth has to be found for the feedback resistor. [1] M. Atef and H. Zimmermann, “10Gbit/s 2mW Inductorless Transimpedance Amplifier “, IEEE International Symposium on Circuits and Systems (ISCAS), 2012. [2]H. Zimmermann, Integrated Silicon Optoelectronics, Springer, 2000. [3]H. Zimmermann and K. Schneider, Highly Sensitive Optical Receivers, Springer, 2006.

Dr. Mohamed Atef Assistant Prof. Electrical Eng. Dept. , Assiut Univerity, Egypt.



Research Inspiring Innovation, the next Big “Small Thing” By Mohamed Farag Hassan

Our ancestors achieved great accomplishments in architecture, medicine, astronomy, etc. we can’t achieve anything unless we searched the heritage they left for us and learn from them. However; Research isn’t information gathering or transferring of facts from books and magazines where no contribution to new knowledge is added. Research is defined as “a systematic process of collecting and analyzing information (data) in order to increase our understanding of the phenomena about which we are concerned”. It is cyclic and should be nonstop process. It starts with a very defined and specific question resulting into the most suitable conclusion for your problem based on 10


the researcher hypotheses and passing through systematic steps. Research is about curiosity and questioning what people see normal, closely observe details, and experiments to gain new knowledge. Research is for solving existing problems and also for developing the current state of any process.

— Albert von Szent-Gyorgy

searchers by nature but we never noticed! When you want to travel to the coast and compare between different transportation means: whether car and Plane or bus for different tradeoffs: speed, cost and safety. So there is an objective and by collecting data, analyzing it to reach the most suitable way for you to travel. Another example is when you are assigned to a college or work project. You start by defining the problem, collecting data from different sources, analyzing what you gathered till reaching the solution.

The Question now “Is Research only a Scientists Job?” .Definitely the answer is “No”. We are all in certain degree re-

Another Question arises “What to do after Research and reaching my conclusion? Is Research an objective itself?

Discovery consists of seeing what everybody has seen and thinking what nobody has thought. " "

”.Here comes the secret of this article, The Innovation part; Innovation should be targeted to integrate the Researching Process, complete the big picture and produce solutions and new applications in a creative way. Innovation is the ability to see Research Problem as an opportunity - not a threat. It’s about designing and using this original fact you came up with your Research Conclusion in a useful way hence becomes a business potential or a promising startup!! " Capital isn't so important in business. Experience isn't so important. You can get both these things. What is important is ideas. If you have ideas, you have the main asset you need, and there isn't any limit to what you can do with your business and your life." — Harvey Firestone Getting great ideas is a fantastic approach but are they applicable? Will they help in solving the problem? We are researching to produce a new product, service or solve an existing problem while using creative and new ideas .Here the cycle would be complete. Research is the fuel of innovation, it provides us with all information and data we need to come up with creative ideas. Also innovation keeps continuous feedback to researchers, where they should research and what new problems they should face. Research provides the ground to have a lot of ideas so you can have a good idea then you will find your “EUREKA” moments through innovation. We all know what happened with Amazon and their success story when they changed from selling books to selling everything from A to Z online.

Also Intel is another good example. Intel was the leader of microprocessors’ technologies and architectures over the past 30 years .Now; they have expanded their domain to include software products. Amazon and Intel didn’t depend on technical and market Research only, or Innovation and creative Ideas only, but both of them to integrate their cycle of success. " Innovation— any new idea—by definition will not be accepted at first. It takes repeated attempts, endless demonstrations, monotonous rehearsals before innovation can be accepted and internalized by an organization. This requires courageous patience." — Warren Bennis Research Inspiring Innovation is how do we intend to win in business and the reason for the existence of most successful startup’s and big companies .Let's make it our culture to research and innovate...let's expand our F R O N T I E R S.

Muhammad Farag Hassan PastChair, IEEE AinShams Univ. Student Branch.




Field Programmable Analog Arrays, A Brief History By: Mohamed F. Hassan Introduction

Sensor-readout interfaces and filters in transceiver front-ends for wireless communication are implemented in the analog domain. Although analog circuits are very complicated and hard to design, they are very power efficient. For this reason, analog circuits are suitable for mobile applications. Usually, these analog circuits are application specific integrated circuits (ASICs). Due to the rapid change of communication standards, ASICs re-designing and development are very expensive. Therefore, there is an increasing need of reconfigurable analog circuits. Field programmable analog array (FPAA) is the solution. FPAAs are flexible integrated devices containing several configurable analog blocks (CABs) and signal routing net12


work between them. By programming the CABs and changing the connections between them, various analog functions could be implemented. The main purpose of FPAAs is the rapid-prototyping of analog circuits like there digital counterpart the field programmable gate array (FPGA). Unlike FPGAs, FPAAs are more application driven than being a general purpose; this is because analog circuits are more complex, non-linear, noisy and difficult to design than digital circuits. In conclusion, the main purpose of designing FPAAs is the need of adaptive analog circuits in low power analog front-ends. Moreover, FPAAs are needed for rapid-prototyping of analog circuitry to ensure the correct functionality of mixed signal system where simulations are not enough.


Since the term was first used in 1991 by Lee and Gulak [1], the FPAA shown in Figure 1 has become an interesting widely research topic. It was introduced to describe the basic idea of CABs which can be connected by a routing network, and are configured digitally. The idea was further enhanced by the same authors in 1992 and 1995 [2, 3] where opamps, capacitors, and resistors can be connected to form a biquad, for instance. The chip was manufactured in a 1.2Âľm CMOS technology, and operates in the 20kHz range at a power consumption of 80 mW. In 1995, a similar idea, the electronically-programmable analog circuit (EPAC) was presented by Pierzchala et al. [4]. Although their test chip featured

out shown in Figure 2 with local interconnects and switches and the OTA tuning is achieved by a programmable current mirror. This technique allows Gm tuning with 5-bit precision which is limited by the large chip area each additional bit of precision adds. Therefore, this technique is not feasible for high

in tuning the active elements. The design attempts to achieve the complexity and flexibility similar to that of FPGAs by incorporating high-level elements such as second order bandpass filters and four-by-four vector-matrix multipliers into its CABs. This makes interesting applications easily possible

Figure 1 FPAA system architecture by Lee and Gulak [1] only a single integrator, they nonetheless proposed the concept of a local interconnect architecture to avoid the bandwidth limiting switches in a routing network, and the design was commercialized. A successful commercial FPAA supplier is Anadigm [5] whose products allow simple instantiations of complex filters, but the switched capacitor (SC) technique limits their bandwidth to 2 MHz In 2002, a continuous-time (CT) FPAA

Figure 3 FPAA architecture of RASP precision tuning in an FPAA due to the chip area it would require. Also in 2002, the reconfigurable analog signal processor (RASP) shown in Fig-

Figure 2 Schematic of chessboard connection scheme by pierzchala [6] using programmable operational transconductance amplifiers (OTAs) and programmable capacitor arrays was presented by Pankiewicz et al. [6] that functioned in the 1MHz range. The FPAA was designed in a chessboard lay-

ure 3 was presented by Hall et al. [7]. In 2005, a second version of the RASP followed [8]. Both implement a classic layout with CABs connected with a global routing network. Floating gates are used as switches in the routing network and

such as Fourier analysis, but degrades its frequency performance. The 0.35 Âľm CMOS technology used and the necessary large routing network - which introduces many bandwidth-limiting switches into the signal path - limit its frequency range to around 100 kHz. The programming of the floating gates is controlled externally by a PCB containing an FPGA and analog switches; the chip itself is not able of independent reconfiguration. In 2007, the above group introduced a specialized version of the RASP [9]. The complex CABs are all replaced by simpler CABs each containing just one second-order biquad tunable by floating gates shown in Figure 4. They are still connected by a classic global routing network using floating gate switches. The maximum achievable bandwidth is improved to around 10-15MHz on the expense of its reduced complexity and ISSUE 3


Fig.4 FPAA based on biquad tunable by floating gates [9] application range. The OTAs are oper- tings. This technique was taken up and stages and to implement the routing at ated in sub-threshold region by floating developed by Joachim Becker in 2004 the same time. By simply switching all gates. [11] when he proposed its use in a of the cells parallel connected OTAs off, In parallel with the above work, the par- hexagonal local interconnect architec- a signal path is cut off. The arrangement allel connection of OTAs (Figure 5) to ture. of the cells in a hexagonal lattice as shown in Figure 6 allows the instantiations of filters of all orders. By doubling the OTAs in a tunable Gm cell, and connecting half of them with inverted output terminals, the signal can be transconducted either direct or inverted, depending on which set of OTAs is switched on. In 2005, Fabian Henrici joined the work group and developed a novel switchable and invertible OTA which cut the number of OTAs in a tunable Gm cell by half, thus reducing parasitic capacitances and nearly doubling the maximum FPAA bandwidth. Together with Joachim Becker, he developed an FPAA Figure 5 Parallel OTA connection proposed by Pavan at el. using his OTA and the local interconachieve tuning was proposed by Pavan nect architecture introduced by Becker. and Tsividis [10] in 2000. The overall It does not require a routing network This collaboration resulted in the first transconductance of the amplifier de- and eliminates switching in the signal manufactured and published FPAA in pends linearly on the number of OTAs path which improves the frequency re- 0.13Âľm CMOS technology, which was switched on. This allows wide range sponse. Instead, the tunable Gm cell presented at ISSCC (International Solid tuning without the usual drawbacks, e.g. consisting of parallel connected OTAs is States Conference) in 2008 [12]. low dynamic range at low frequency set- used to implement the required Gm-C Moreover, Henrici continued on this 14


Figure 6 Hexagonal FPAA structure work and manufactured an FPAA chip 1995 IEEE International, pp. 196-197, in 0.13µm CMOS technology with con- Feb 1995. tinuous tuning through floating gates. 5. Anadigm: Supplier of Dynamically Programmable Analog Signal ProReferences cessors (dpASP), USA. ht1. Lee, E.K.F. and Gulak, P.G., “A CMOS tp:// Field-programmable analog array," Sol- 6. Pankiewicz, B. and Wojcikowski, M. id-State Circuits, IEEE Journal of, vol. and Szczepanski, S. and Yichuang 26, pp. 1860-1867, Dec 1991. Sun,“A field programmable analog array 2. Lee, E.K.F. and Gulak, P.G., “Field for CMOS continuous-time OTA-C filprogrammable analogue array based on ter applications," Solid-State Circuits, MOSFET transconductors," Electronics IEEE Journal of, vol. 37, pp. 125-136, Letters, vol. 28, pp. 28-29, Jan. 1992. Feb 2002. 3. Lee, E.K.F. and Gulak, P.G.,“A 7. Hall, Tyson S. and Hasler, Paul and transconductor-based field program- Anderson, David V., “Field Programmable analog array," in Solid-State Cir- mable Analog Arrays: A Floating-Gate cuits Conference, 1995. Digest of Approach," in FPL '02: Proceedings of Technical Papers. 42nd ISSCC, 1995 the Reconfigurable Computing Is Going IEEE International, pp. 198-199, 366, Mainstream, 12th International ConferFeb 1995. ence on Field Programmable Logic and 4. Pierzchala, E. and Perkowski, M.A. Applications, (London, UK), pp. 424and Van Halen, P. and Schaumann, R., 433, Springer-Verlag, 2002. “Current Mode amplifier/integrator for 8. Hall, T.S. and Twigg, C.M. and Gray, field programmable analog array " in J.D. and Hasler, P. and Anderson, D.V., Solid State Circuits Conference, 1995. “Large scale field programmable analog Digest of Technical Papers. 42nd ISSCC, arrays for analog signal processing,"

Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52, pp. 22982307, Nov. 2005. 9. Hasler, P.E. and Twigg, C.M.,“An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation," in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 177-180, May 2007. 10. Pavan, Shanthi and Tsividis, Yannis, “High frequency continuous time filters in digital CMOS processes. Norwell, MA, USA: Kluwer Academic Publishers, 2000. See pp. 12, 13, 28, 141. 11. Becker, J. and Manoli, Y.,“A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells," in Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, vol. 1, pp. I-1092-5 Vol.1, May 2004. 12. Becker, J. and Henrici, F. and Trendelenburg, S. and Ortmanns, M. and Manoli, Y.,“A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13 µm CMOS with 186MHz GBW," in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 70-596, Feb. 2008.

Mohamed F. Hassan PhD student, Project Assistant; Electrodynamics, Microwave and Circuit Engineering; Vienna University of Technology



State of the Art

Current Trends in RF and Microwave Integrated Circuits Research

Why do we need Ultra-wideband? (1)

By: Osama Haraz

Since the release by the Federal Communications Commission (FCC) of a bandwidth of 7.5GHz (from 3.1GHz to 10.6GHz) for Ultra-wideband (UWB) wireless communications, UWB is rapidly advancing as a short range high speed high data rate wireless communication technology. A new technology has been employed into our daily lives with minimal interference known as the ultra-wideband or UWB. This technology is an unlicensed service that can be used anywhere, anytime, by anyone. UWB which is well known for its use in ground penetrating radar (GPR) has shown interest in communications and radar applications. Unlike traditional systems, this can only operate over a specific range of frequencies. UWB devices operate by employing a series of very short electrical pulses (billionths of a second long) that result in very wideband transmission bandwidths. In addition, UWB signals can run at high speed and low power levels. All these unique features of UWB technology make it suitable for many different applications such as positioning, geo-location, localization (accurate positioning, high multipath environments and obscured environments), radar/sensor applications (vehicular, marine, GPR, imaging, wall-imaging, sense-throughthe-wall (STTW), surveillance systems), communications (high multipath environments, short range communications, high data rates). 16


UWB Technology

Currently, there is an increased interest in Ultra-wideband (UWB) technology for use in several present and future applications. UWB technology received a major boost especially in 2002 since the US Federal Communication Commission (FCC) permitted the authorization of using the unlicensed frequency band starting from 3.1 to 10.6 GHz for commercial communication applications [1]. Although existing third-generation (3G) communication technology can provide us with many wide services such as fast internet access, video telephony, enhanced video/music download as well as digital voice services, UWB –as a new technology– is very promising for many reasons. Large Bandwidth

The FCC allocated an absolute bandwidth more than 500 MHz up to 7.5 GHz which is about 20% up to 110% fractional bandwidth of the center frequency. This large bandwidth spectrum is available for high data rate communications as well as radar and safety applications to operate in. Fig. 1 shows the comparison between conventional nar-

Fig. 1 Time- and frequency-domain behaviors for narrowband versus UWB communications [3]. rowband (NB) versus UWB communic- used in UWB systems because its shape ations in both time- and is easily generated. Ultra-wideband frequency-domains. The conventional pulses are typically of nanoseconds or NB radio systems use NB signals which picoseconds order. This is the origin of are sinusoidal waveforms with a very the name Gaussian pulse, monocycle or narrow frequency spectrum in both doublet. Transmitting the pulses directly transmission and reception. Unlike a to the antennas results in the pulses beNB system, an Ultra-wideband radio ing filtered due to the properties of the system can transmit and receive very antennas. This filtering operation can be short duration pulses. These pulses are modeled as a derivative operation. The considered UWB signals because they same effect occurs at the receive anhave very narrow time duration with tenna. The spectrum of the Gaussian very large instantaneous bandwidth [2]. doublet is shown in Fig. 2(b). Due to using UWB systems those very short Very Short Duration Pulses duration pulses, they are often characA typical received UWB pulse shape terized as multipath immune or mulwhich is known as a Gaussian doublet is tipath resistant. shown in Fig. 2(a). This pulse is often

Fig. 2 (a) Idealized received UWB pulse shape[4]

(b) idealized spectrum of a single received UWB pulse [4] ISSUE 3


High Data Rates with Fast Speed

The huge bandwidths for UWB systems −compared to other conventional NB systems− can show a number of important advantages. There is an increasing demand for high speed and high data rate applications in communication systems [5]. One of those advantages of UWB transmission for communications is the ability of UWB system to achieve high data rates in future wireless communications which require increasing the bandwidth of the communication system. While current chipsets are continually being improved, most UWB communication applications are targeting the range of 100 Mbps to 500 Mbps [6]. Table 1 shows the spatial and spectral capacity for different communication systems such as UWB, wireless local area network (WLAN) and Bluetooth. The speeds of data transmission for different communication systems are summarized in Table 2. Using UWB technology will enable us to achieve higher data rates with higher spatial capacity compared to other existing systems. In addition, UWB technology achieves very high speed for data transmission. Another advantage of UWB systems is the ability to effectively reduce fading and interference problems in different wireless propagation channel environments because of the limited transmitted power of UWB systems [7]. This is in addition to exploiting multipath or frequency diversity because of the huge bandwidth of UWB systems [8]. The signal-to-noise ratio (SNR) of the UWB system can be increased using some techniques such as antenna diversity and beamforming which in turn 18


Table 1 Spatial and spectral capacity for different communication systems

Table 2 Speed of data transmission for different communication systems will provide range extension and boost the capacity of worldwide interoperability for microwave access (WiMAX) for wireless metropolitan area networks (WMAN), and wireless fidelity (Wi-Fi) for wireless local area networks (WLAN) [9]. Some Basic Definitions

C =B log(1+S⁄N) C is the maximum channel capacity B is the channel bandwidth S⁄N is the signal-to-noise ratio (SNR) of the channel Low Power Consumption

The UWB technology has another advantage from the power consumption point of view. Due to spreading the energy of the UWB signals over a large frequency band, the maximum power

available to the antenna –as part of UWB system– will be as small as in order of 0.5mW according to the FCC spectral mask shown in Fig. 3.This power is considered to be a small value and it is actually very close to the noise floor compared to what is currently used in different radio communication systems [2]. Table 3 shows the power spectral density (PSD) of some wireless broadcast and communication systems such as UWB, radio, television, 2G cellular and WLAN. The PSD is defined as the total transmitted power over the operating bandwidth. According to the definition in [10], one important feature of a radar and communications transmitter is called the effective isotropic radiated power (EIRP) which can be defined as the product of its gain and input power. Fig. 4 shows the FCC spectral mask of the indoor UWB EIRP emission level. It can be seen that the maximum signal power is limited to−41.3 dBm per MHz throughout the whole UWB frequency range from 3.1 to 10.6 GHz. All the

UWB systems and devices must work within this spectral mask for legal operation in order to comply with the FCC standards and regulations. Small Size and Low Cost

Fig. 3 UWB versus other radio communication systems [3].

Table 3 PSD of some wireless broadcast and communication systems

The small size of UWB transmitters is a requirement for inclusion in today’s consumer electronics. The main arguments for the small size of UWB transmitters and receivers are due to the reduction of passive components. However, antenna size and shape are other factors that need to be considered. Ultra-wideband antennas are considered in the next article. Among the most important advantages of UWB technology are those of low system complexity and low cost. Ultra-wideband systems can be made nearly “alldigital�, with minimal radio frequency (RF) or microwave electronics. The low component count leads to reduced cost, and smaller chip sizes invariably lead to low-cost systems. The simplest UWB transmitter could be assumed to be a pulse generator, a timing circuit, and an antenna.

Dr. Osama Haraz, Concordia University, Montreal, Canada

Fig. 4 FCC spectral mask for indoor UWB systems [1] ISSUE 3

















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VLSI Egypt Magazine Issue 3