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Implementation and Test of a Power-Line based Communication System for Electrical Appliances Networking Andrea Ricci∗ , Valerio Aisa§ , Ilaria De Munari∗ , Valerio Cascio§ and Paolo Ciampolini∗ ∗ Dept.

of Information Engineering, University of Parma, Parma, Italy. Email: andrea.ricci@nemo.unipr.it, {ilaria.demunari, paolo.ciampolini}@unipr.it § Wrap S.p.A., Fabriano (AN), Italy. Email: {Valerio.Aisa, valerio.cascio}@indesitcompany.com Abstract— This paper discuss the development of a low-cost, narrow-band transmission system, aimed at connecting digital appliances to a home network. The proposed approach is based on powerline communication (ULP: Ultra Low-cost Powerline), carried out on the power-supply wire between the appliance and the outlet. Through ULP, appliance can communicate with a transceiver node located at the outlet, the “smart adapter”, which, in turn, can flexibly route messages toward external control devices (e.g., for diagnostic purposes) or, more generally, toward a home control network. At the appliance side, such an approach allows for connectivity at extremely low costs, at the same time keeping independent of the actual home control network protocol (since different configurations of the smart adapter take care of it). To make practical their implementation on a variety of digital appliances, ULP communication functions have been implemented in a dedicated hardware device, conceived as a dedicated peripheral for a general-purpose microcontroller. In this work, details on the peripheral architecture and its implementation are given. A prototype of the peripheral has been developed, based on a FPGA board directly connected to the microprocessor bus. This closely emulates the perspective microcontroller architecture, and allowed for extensive testing of the device under realistic operating conditions. Complete characterization of ULP protocol has been carried out, estimating BER figures well below 10−6 .

I. I NTRODUCTION Microelectronic technology fostered the pervasive diffusion of digital controllers. Modern household appliances embed microcontrollers to manage all tasks; digital cores are used, for example, to control electric actuators and to manage sensor signals. Furthermore, digital domain computation allows for the deployment of innovative features. Among these new characteristics, connectivity is expected to become a standard in the next future. This will enable for innovative services like preventive maintenance, remote control and smart power management. Networking will improve functionality, safety, reliability and performance of appliances. To this purpose, the adoption of several communication protocols, either wired or wireless, had been proposed (Konnex [2], LonTalk [1], Ethernet [3], ZigBee [4]). However, high-priced communication nodes, typical of these solutions, prevent most of them from being effectively exploited for low-cost “white goods” networking. Moreover, the absence of universal agreement on a recognized home-networking standard, makes the protocol selection a difficult task and

Communication node

microcontroller

( PLC , ZigBee , WiFi , ...) AFE microcontroller

AFE

ULP peripheral

CPU

Smart Adapter Low-Cost Power-Line Communication Digital Appliance

Home Network

Fig. 1.

Network structure.

leaves the field open to new smart solutions. A new approach has been proposed in [5] and [6], based on a novel network structure, which allows for each digital appliance to establish an ultra low-cost half-duplex power-line communication (called ULP: Ultra Low-cost Powerline) on its power-supply cord. A general-purpose communication node (called a ”smart adapter”, SA) located, for instance, at the outlet then acts as a bridge between the ULP communication and the actual homenetworking protocols. Using this method, i) communication costs at the appliance side are kept at a minimum and, ii) communication with the specific home-networking protocol are delegated to the the smart adapter, so that the internal appliance architecture does not care about standard protocols at all, and the same appliance may communicate with different networks just by exploiting the proper SA. Moreover, since appliance additional costs due to ULP are negligible, ULP features can be implemented on every produced item, regardless of its actual need of networking. As a side-effect, this provide an effective and inexpensive way for factory testing as well. In a previous paper [5] a preliminary FPGA-based implementation for ULP peripheral supporting upstream communication was introduced; in this paper, an improved solution will be discussed: some basics of the approach have been revised, aiming at lowering EMC disturbances, and at adding some functionalities. In the following, the novel architecture is described, aiming at implementing the ULP algorithms into a


300 200

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eq

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b) Fig. 2. ULP upstream communication: signals, smart adapter transmission section and appliance receiver.

SA over the power distribution network has been drastically reduced, at the same time making it possible to attain a higher throughput (200 bit/s). Figure 2(a) reports an example of controlled glitches (VSm ), generated by zener diodes connected in series with appliance power supply. The same figure shows the smart adapter transmission section, where a digital device controls current flowing through the diodes by means of a couple of MOSFETs and a relay. At the appliance side (see Fig. 1(b)), an inexpensive analog front-end (AFE), made by a band-pass filter and two Schmitt-triggers, couples the power section to the digital circuitry. In Fig. 2, examples are given of digital signals zc1 and zc2 , provided by the AFE to the digital section. zc1 allows for synchronization, by triggering at the sinewave zero crossing, whereas zc2 tracks data encoded glitches. Perturbations are generated twice within a power supply period, in order to account for the actual nature (i.e., inductive or capacitive) of the appliance load. In fact, a perturbation generated during the first quarter of power-supply period is not properly revealed when inductive reactance are plugged to the power-line. On the other hand, second-quarter glitches are missed if capacitive loads are connected. To cope with this, the first half of supply voltage period is divided into two transmission intervals, and the j th packet of M bit Dj = {dM j , dM j+1 , ..., dM j+M −1 } ,

dedicated microcontreller peripheral. Within this perspective, the hardware emulation of such a peripheral is discussed and physical implementation issue (chip area and power consumption) are analyzed. Performances of the peripheral have been experimentally evaluated, under realistic operating conditions. II. N ETWORK S TRUCTURE AND ULP PHYSICAL LAYER Figure 1 describes the network structure. Each digital appliance establish a half-duplex communication with an external device, here called “smart adapter”, located at the outlet. Transmission is carried out on the power supply cable, according to an ultra low-cost power-line communication protocol described below. The smart adapter, placed between the appliance power-supply plug and the outlet, acts as a bridge towards the home network. At the one end, the smart adapter manages ULP communications with the appliance, while, at the opposite end, it embeds specific network controllers which allows for interfacing to wired (e.g. broadband PLC, ethernet, etc.) as well as wireless (e.g. Wi-Fi, ZigBee, etc.) networks. A. Smart Adapter to Digital appliance communication In [5], basics of the power modulation scheme exploited by ULP were introduced; in particular, upstream communication (i.e., from the smart adapter to digital appliance) relies on intentional and precise perturbations of the power supply waveform. With respect to the previous implementation, here a more efficient scheme is accounted for: by introducing loweramplitude glitches on the waveform, the noise injected by the

(1)

is transmitted twice (i.e., once within each interval). Data are encoded by modulating the perturbation positions, with respect to the zero-crossing of supply voltage waveform. Modulation expressions read: ( g(D ) L1j = L1of f + L1Vj = L1of f + 2Mj LVmax (2) s(D ) L2j = L2of f + L2Vj = L2of f + 2Mj LVmax where g is the Gray encoding function, s is an encoding function described later on, L1of f and L2of f are time offsets, and LV max is the shift range. In figure, for instance, parameters are the following: L1of f = 1 ms, L2of f = 7 ms, LVmax = 2 ms, with the AC supply voltage period T set at 20 ms. Measurements demonstrate that it is possible to transmit at least one nibble (M = 4) at a time without exceeding noise limits set by regional standardization committees (e.g., CENELEC in Europe) and preserving the proper functionality of the appliance. As already discussed above, information data have to be duplicated and encoded into both the transmission intervals, in order to ensure that at least one pulse will trigger the receiver. When both glitches reach the receiver, noise can affect the positions of received pulses, due to appliance load variations within a period. Hence, error correction should be performed: as described in Fig. 3, the coding function s allows for maximize the distance among pulse nominal values within the receiving space. At the appliance side, measured intervals (represented by circles in figure) are rounded to the nearest


L1V

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cycle, the mean power PTk reads:

nominal couples of pulses

PTk

1 = T

(k+1)T Z

kT

received couples of pulses

µ ¶ N −1 1 X T T ∼ P dt = P kT + +i . (5) N i=0 2N N

The resulting scheme is very robust and reliable and can be implemented at practically no additional costs. III. M ICROCONTROLLER PERIPHERAL IMPLEMENTATION

decision intervals 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2

LV Fig. 3.

Receiving space partitioning for M = 4.

nominal values (represented by up triangles) and decoded as follows: ˆ j = min d D ¯ D∈D

h³ ´ ¡ ¡ ¢ ¡ ¢¢i ¯ ,s D ¯ L1Vj , L2Vj , g D ,

(3)

here, d is the Euclidean distance and D is the set of 2M packets of M -bit. Again, the main concern here is to keep the digital control at the appliance side as simple as possible: as already stressed above, the AFE, in order to provide the ULP logic with square waves zc1 and zc2 , just includes a couple of Schmitt triggers and a fist-order band-pass filter. Extracting delays between zc1 rising edge and zc2 falling edges is almost trivial: if such intervals are larger than L1of f or L2of f , a message coming from the smart adapter is recognized and decoded by measuring L1j or L2j respectively. Decoding tasks just require elementary binary counters. Besides, equation 3 is implemented by means of a simple look-up table. B. Digital Appliance to Smart Adapter communication Downstream communication, instead, is based on the modulation of instantaneous power consumption [5]. Data can be easily encoded in the supply current by activating a small triac which, in turn, drives an inexpensive load (ZULP ). Let’s assume a set of binary data dk is to be transmitted; the expression of appliance current, IDA , is therefore: µ ¶ VM 2π X IDA = sin t dk pT (t − kT ) , (4) ZU LP T k

where pT is the port function, T is the AC period, and ZU LP is the impedence of modulation load. At the smart adapter, data coming from the electrical appliance are decoded by measuring the mean power required by the appliance during each k-th cycle of the supply voltage. If N samples of the instantaneous power P (t) are acquired per

As already discussed above, transceiver tasks at the appliance side are kept as simple as possible, in order to lower the overhead induced by communication. Software implementation of these tasks on the appliance native microcontroller is therefore relatively inexpensive; nevertheless, letting a small hardware device take care of them would minimize the impact on both the appliance software and physical resources. Additional hardware costs would be negligible as well, if the ULP hardware controller were integrated as a peripheral into the existing microcontroller architecture. Aiming at this, to investigate the practicality of such an approach, we made reference to the Renesas H8 microcontroller family, widely adopted for white goods applications. We have developed a prototypal implementation of the ULP peripheral, and tested it on the Renesas development system based on the E6000 emulation board ([7]). Figure 4 describes system setup: the microcontroller emulator allows for access to the internal bus signals so that an additional board, embedding a FPGA device, can directly communicate with the microcontroller CPU core. ULP digital peripheral has been implemented within the programmable logic. Connection of the emulated microcontroller to the appliance target board is performed by means of a flat cable the header of which features a standard chip footprint connector. The ULP peripheral architecture is detailed in Figure 5, and can be divided into six functional blocks: a register interface, a module for signal conditioning, transmitter, receiver, line info and low-power control block. Peripheral operations are performed using 1 MHz system clock, derived from the appliance microcontroller. Communication between ULP peripheral and CPU is performed using a register interface. The register set includes five 8-bit registers: control register (PMCR), status

appliance power supply cord

header cable with chip footprint

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Fig. 4.

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Signal conditioning ULP Peripheral ( FPGA Altera FLEX 10K )

TIMER x Standard Peripheral

Line info block monitors the power supply. It evaluates amplitude and frequency of the supply voltage, by using the same time interval estimation techniques exploited by the receiver section. Supply voltage amplitude is evaluated during periods not involved in data communication (negative half of power supply waveform); this allows the supply-voltage meter to share the same hardware resources related to receiver block. The amplitude is thus extracted from eq. (6), by measuring the time interval between Schmitt-triggers’ outputs; assuming the signal is sampled n clock periods after a zero-crossing reference time (i.e., first trigger’s output), the amplitude is related to the second trigger’s threshold voltage (Vth ) by the following relationship:

RX ( zc 1 , zc 2 ), TX ( triac control) Analog Front-End

Fig. 5.

VM = Power Supply Cord

ULP peripheral architecture.

register (PMSR), data register (PMDR), voltage-measure register (PMVMR) and clock-generation register (PMCGR). All of the registers share access to common interface with the microcontroller, based on address- and data-buses and read/write mode signals. The peripheral status is signalled through a set of five interrupt flags, allowing for microcontroller supervision and to cope with exceptions (such as overrun errors and blackout detection). The macrocell takes care of signal conditioning: square waves zc1 and zc2 are routed through noise suppressors before being latched internally. Their edges are used to generate trigger signals for subsequent processing blocks. The receiver module operates in two distinct modes: an initial calibrating phase, and the actual running mode. Calibration is necessary to deal with tolerances of low-cost AFE components: to this purpose, the receiver is first trained by means of a fixed sequence of known data, from which the actual mean value of the offsets L1of f and L2of f are extracted. When only one offset can be computed, his value is exploited for either transmission intervals. In the operating phase, interruptions length are measured through binary counters. If only one pulse per period triggers the receiver, data is decoded according to equations 2, accounting for the calibrated value L1of f or L2of f . When a couple of glitches is received, operations described in equation 3 are performed instead. Decoded nibbles are used by the RRC (Receiver Register Control) block to build data bytes, to be stored into data register. Contemporarily, receiver state flags are set in the status register. The receiver block also detects power supply failures, by testing if voltage interruptions length exceedes the AC period value. If this occurs, a proper interrupt flag is raised. The transmitter section generates the mask signal m(t) (which controls power modulation triac TU LP ), by means of a shift register, triggered by the zero-crossing signal zc1 and loaded, eight bit at a time, from data register PMDR.

V V ¡ 2πth ¢= ¡ th ¢. 2π sin T nTclk sin 10 4 n

(6)

To abtain precise results, a calibrating step is required for this section of ULP peripheral too: to deal with tolerance of Schmitt-trigger threshold (Vth ), the voltage meter has to be configured once by using a known reference voltage source. The last block control the peripheral power consumption, enabling various modes of operation. These includes a normal active mode and different power-down modes, to keep power requirement as low as possible. in which power consumption is significantly reduced. Power reduction is achieved exploiting hierarchical clock-gating. Power-management modes include: • Active mode: since transmission, reception and powersupply monitoring happens at separate time slots within the power supply period, are separated time functions, the relative hardware modules are enabled one at a time by the power control block. provides one module at a time with clock signal, reducing total power consumption. • Subactive mode: only the essential tasks are enabled

2125

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Fig. 6. Examples of distribution functions: a), b) report fL1 L2 and fL2 while transmitting Dj = 0x5; c), d) measured distribution functions with Dj = 0x8.


by this mode: power control block halts logic not strictly necessary to communication (e.g., power-supply monitor). Stand-by mode: the stand-by mode is activated if a SLEEP instruction is executed by the microcontroller core. The peripheral clock is turned down and no operation is carried out; register contents are preserved and I/O ports are placed in high-impedance state.

single pulse received 1

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IV. E XPERIMENTAL R ESULTS In order to validate the communication principle and investigate the microcontroller peripheral performance, an extensive set of experimental measurements was carried out in a thorough field test. To this purpose, a set of static and time-variable appliance loads were connected to the powerline, to simulate the actual operating environment. First, measurements were performed using a barely resistive load, represented by a 25 W lamp, always connected to the power supply cord at the appliance side. The same device was also exploited to perform downstream communication, modulating the current flowing over the power supply cord, as described in Section II-B. Next, capacitive and time-dependent inductive loads were taken into account, by connecting an actual washing-machine to the network. Capacitive behavior was obtained exploiting appliance power-supply filters, whereas an inductive load was given by the washing-machine electrical engine. Timedependent behavior was induced by performing several different washing cycles. Data collected during measurements were processed to extract statistics and BER performances. Figure 6 reports examples of distribution functions evaluated at the appliance side, whith the running washing-machine loading the network. Plots (a) and (b) were obtained for a given transmitted nibble, i.e., Dj is equal to 0x5. Probability of both glitches reaching the receiver within the default time slot is estimated to be P = 0.5769. In 0.0867% of transmission events the pulses are outside default bounds, although they still falls within the error correction area defined by encoding functions g and s. During the remaining transmissions (P = 0.3364), only second quarter pulses trigger the receiver, and always fall within the right time slot. Plots (c) and (d) illustrate the response for a different transmission (Dj equal to 0x8). Figure 7 shows the summary of statistical data collected during communication under different load conditions. Plots (a) and (b) reports statistics of pulse position when only one glitch is received during fist transmission interval. Plot (a) shows the mean difference between measured and nominal pulses position as a function of data transmitted (Dj ) and load states (bar graph shade). The related standard deviation distribution is shown in (b). Plots (c) and (d) refer to the mean and standard deviation of pulse position, respectively, evaluated when glitches were received only during the second transmission interval. The same distributions, shown in Figure 7(e)-(h) for both intervals, are eventually given, when both pulses trigger the receiver. As already highlighted, a couple of pulses within

Lamp Appliance Input Filter Washing Machine P2 Washing Machine P3 Washing Machine P5

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TABLE I S YNTHESIS RESULTS USING UMC 0.18µm STANDARD CELL LIBRARY Hierarchy ULP interface

register interface signals conditioning receiver transmitter line info power control

Cell Area [µm2 ]

Pdyn [µW ]

28008

7051 567 13424 2603 3135 1228

Pleakage [nW ] 138.98

active mode: 97.72 subactive mode: 87.28 standby mode: 26.19 68.32 1.46 18.40 3.27 4.62 1.65

34.95 2.10 71.01 11.84 14.56 4.52

the supply voltage period may imply a higher noise impact with respect to a single trigger event. This is reflected by the higher mean difference and standard deviation reported in (e)-(h), which give reason of the introduction of the errorcorrection technique described in Section II-A. Results illustrated so far validate the proposed solution for upstream communication. Furthermore, experimental data suggest that the same communication principle can be applied using higher M value, allowing for throughput improvement. After fully validating the circuit functionality, an experimental estimate of the Bit Error Rate associated to the ULP protocol was also carried out. A BER figure well below than 10−6 was evaluated, which is more than appropriate for the application at hand. V. UMC 0.18µm S TANDARD -C ELL I MPLEMENTATION To probe further the feasibility and practicality of the hardware implementation of the ULP peripheral, a VLSI implementation was also carried out, by referring to a commercial technology, similar to the fabrication technology of the target microcontroller. The design was fully synthesized in a standard-cell fashion, by using Synopsys Design Analyzer [8]. With reference to the UMC 0.18 µm commercial technology, the implementation of the ULP controller required a total cell area of about 0.028 mm2 , corresponding to 2894 equivalent logic gates. The estimated dynamic power consumption of the ULP interface equals 97.72 µW , at 1.8 V power supply. Stand-by power consumption is much lower, in the range of 29.19 µW . Table I gives more detailed results of the preliminary synthesis process; in order to estimate the relative weight of different subsystems, each block has also been independently synthesized and simulated. This allow for appreciating contributions of different subsystems to the power and area budget. With respect to the preliminary implementation results given in [5], the improved functionality introduced here requires more chip area than first implementation. On the other hand, implementation of the power control module allows for consistent reduction in power-consumption. The overall power and area figures estimated so far are well below reasonable limits for the actual implementation within the industrial microcontroller;

actual test implementation in the real device is foreseen in the next months. VI. C ONCLUSION In this paper a communication system for electrical appliances networking is discussed. Its main goal is that of allowing for networking digital household appliances, without adding significant costs and staying independent of the actual homenetworking protocol. This is achieved by transferring higherlevel communication tasks to an external “smart adapter” device, which may manage different protocols and serve different appliances. Local communication is achieved by exploiting a low bit-rate, ultra low-cost power-line communication (ULP) protocol between the appliance and the smart adapter. Formal basics of the ULP protocol have been illustrated, and improvements over the first prototype version have been discussed. Better performances, with respect to [5], are obtained: the transmission reliability was improved and the injected noise was reduced. Perspectively, higher bit rates are also achievable. Experiments were made, aimed at evaluating costs and performance of a hardware implementation of a ULP controller: the architecture has been conceived as a microcontroller dedicated peripheral, and a prototype was mapped on a FPGA board. The board, in turn, was connected to a microcontroller development system, directly accessing the microntroller buses and allowing for realistic test. The ULPenabled microcontroller was then exploited for the protocol validation, by performing an extensive set of measures. A test environment, including actual appliances, was set up to this purpose. Fully satisfactory results were obtained, both in terms of performance and implementation issues, paving the way toward the actual chip fabrication. ULP capabilities would then come at negligible costs, providing an effective and flexible way for low-cost networking of digital appliances. ACKNOWLEDGMENT The authors would like to thank T.Watanabe, G. Clark and M. Mazzoni from Renesas Corporation for their support to this work. R EFERENCES [1] Echelon Corporation, LonTalk Protocol Specification, version 3.0. 1994. [2] Konnex Association, KNX Standard. 2001. [3] Institute of Electrical and Electronics Engineers, Inc., IEEE Std 802.3. IEEE Computer Society, 2002. [4] Institute of Electrical and Electronics Engineers, Inc., IEEE Std 802.15.4. IEEE Computer Society, 2004. [5] A. Ricci, V. Aisa, V. Cascio, G. Matrella and P. Ciampolini, “Connecting electrical appliances to a Home Network using low-cost Power-line Communication”, in Proc. 2005 International Symposium on Power-Line Communications, pp. 300-304. [6] V. Aisa, P. Falcioni and P. Pracchi, “Connecting white goods to a home network at a very low cost”. International Appliance Manufacturing, 2004. [7] Renesas Technology Corp., H8/300H Series E6000 Emulator, User’s Manual, rev. 2.0, version 12.12.2000. [8] Synopsys, Design Analyzer Reference Manual, version 05.2002.


2006 - Power-Line based Communication System for Electrical Appliances Networking.