Mary Hall Associate Professor www.cs.utah.edu/~mhall email@example.com
Mary Hall is an associate professor. Her research focuses on compiler technology for exploiting performance-enhancing features of a variety of computer architectures, with a recent emphasis on many-core graphics processors and multi-core nodes in supercomputers. Prior to joining University of Utah, Professor Hall held positions at University of Southern California, Caltech, Stanford and Rice University. Professor Hall’s current research involves developing compiler-based autotuning technology, and applying it to application domains that include molecular dynamics, biomedical imaging, signal processing and social networks. Autotuners experiment with a set of alternative application mapping strategies to select the mapping that best exploits architectural features such as deep memory hierarchies, specialized compute engines and multiple cores. Professor Hall is an ACM Distinguished Scientist. She has published over 70 refereed articles and given more than 50 invited presentations. She has led a total of 30 projects funded by NSF, DARPA, DOE, NSA and Intel Corporation. She has served on over 45 program committees in compilers and their interaction with architecture, parallel computing, and embedded and reconfigurable computing, including 2009 program chair of the Code Generation and Optimization Conference, and 2010 program chair of the ACM Symposium on Principles and Practice of Parallel Programming. She serves as chair of the ACM History Committee, and as a member of the IEEE Computer Society Awards Committee. She also participates in outreach programs to encourage the participation of women in computer science.
Publications Refereed Journals J. Shin, M. Hall and J. Chame, “Evaluating Compiler Technology for ControlFlow Optimizations for Multimedia Extension Architectures,” International Journal of Embedded Systems, 2009. 33(4) pp. 235-243. M. Hall, D. Padua and K. Pingali, “Compiler Research: The Next Fifty Years,” Communications of the ACM, Feb. 2009. 52(2) pp. 60-67. T. Kurc, S. Hastings, V. Kumar, S. Langella, A. Sharma, T. Pan, S. Oster, D. Ervin, J. Permar, S. Narayanan, Y. Gil, E. Deelman, M. Hall, J. Saltz “HPC and Grid Computing for Integrative Biomedical Research,” International Journal of High Performance Computing, 2009. 23(3) pp. 252-264. V.S. Kumar, T. Kurc, V. Ratnakar, J. Kim, G. Mehta, K. Vahi, Y.L. Nelson, P. Sadayappan, E. Deelman, Y. Gil, M. Hall and J. Saltz, “Parameterized specification, configuration and execution of data-intensive scientific workflows,” Cluster Computing,
54 >> 2009 & 2010 REPORT
April 2010. 13(3) pp. 315-33. Refereed Conference and Workshops M. Demertzi, P. C. Diniz, M. W. Hall, A. C. Gilbert, and Y. Wang. “Computation reuse in domain-specific optimization of signal recognition (poster).” In Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA ‘09), Feb. 2009, p. 281. A. Tiwari, C. Chen, J. Chame, M. Hall and J. K. Hollingsworth, “A Scalable Autotuning Framework for Compiler Optimization,” Proceedings of the International Parallel and Distributed Processing Symposium, May, 2009. pp. 1-12. V. S. Kumar, P. Sadayappan, G. Mehta, K. Vahi, E. Deelman, V. Ratnakar, J. Kim, Y. Gil, M. Hall, T. Kurc, J. Saltz, “An Integrated Framework for Parameter-based Optimization of Scientiﬁc Workﬂows,” Proceedings of the International Symposium on High Performance Distributed Computing, June, 2009. pp. 177-186. W. Chiang, M. DeLisi, T. Hummel, T. Prete, K. Tew, M. Hall, P. Wallstedt, and J. Guilkey, “GPU Acceleration of the Generalized Interpolation Material Point Method,” Symposium on Application Accelerators for High Performance Computing, July, 2009. K. Venkataraju, M. Kim, D. Gerszewski, J. R. Anderson, and M. Hall, “Assembling Large Mosaics of Electron Microscope Images using GPU,” (poster) Symposium on Application Accelerators for High Performance Computing, July, 2009. J. Shin, M. W. Hall, J. Chame, C. Chen, P. F. Fischer, P. D. Hovland, “Autotuning and Specialization: Speeding up Nek5000 with Compiler Technology,” (poster) SC’09, Nov. 2009. J. Shin, M. W. Hall, J. Chame, C. Chen, P. Fischer, P. D. Hovland, “Autotuning and Specialization: Speeding up Nek5000 with Compiler Technology,” International Conference on Supercomputing, June, 2010. pp. 253-262. B. Peterson, M. Datar, M. Hall and R. Whitaker, “GPU Accelerated Particle System for Triangulated Surface Meshes,” (poster) Symposium on Application Accelerators for High Performance Computing, July, 2010. Gagandeep S. Sachdev, Vishay Vanjani and Mary W. Hall, “Takagi Factorization on GPU using CUDA,” (poster) Symposium on Application Accelerators for High Performance Computing, July, 2010. G. Rudy, M. Khan, M. Hall, C. Chen, and J. Chame, “A Programming Language Interface to Describe Transformations and Code Generation,” Proceedings of the