International Journal of Electrical and Electronics Engineering Research (IJEEER) ISSN 2250-155X Vol. 3, Issue 3, Aug 2013, 147-154 ÂŠ TJPRC Pvt. Ltd.
USER WANTED LOGIC GATE ON A SINGLE IC CHIP PRIYANKAR ROYCHOWDHURY B-Tech in ECE, Kolkata, West Bengal, India
ABSTRACT The IC described here can produce output of a logic gate as the user wants which gate output (OR, AND, XOR, NOR, NAND, XNOR, NOT) he/she wants. Just by setting some switches on the IC and giving proper inputs at the pins of IC, he/she can get the output of his/her desired logic gate from proper output terminals. The internal circuit diagram, block diagram, pin diagram and explanation of circuit and operations are stated in this paper.
KEYWORDS: Logic Gate, Switch, IC, Path, Circuit INTRODUCTION We know that for performing logic gate operations in digital circuits, family of ICs are available. Each IC has a separate function: AND/OR/XOR/NAND/NOR/XNOR/NOT. If a user wants to perform a logic gate operation, he/she has to remember the specific IC for specific operation and then use it for his/her purpose. If he/she needs multiple different operations one after another, for that each operation purpose, say AND, NOT, XOR, specific IC for each operation will be required. Each IC is comparatively larger and so for multiple operations, a large amount of space of circuit board is utilized. But the IC described in this paper can perform any logic gate operation. So, there is no requirement of remembering any IC no. For multiple operations, this single IC can perform different logic gate operations one after another. So, there is no requirement of multiple IC connections for different logic gate operations. So, due to a single IC, large amount of space is saved on circuit board that can result in smaller size.
OVERVIEW Now, the internal circuits will be drawn according to some logic gate operations and conditions which will be described later. Then the circuit will be explained. After that switches and their functions will be stated. After this, finally we will come to the pin diagram of IC, its operation procedure. The circuit diagram will use RTL logic for various operations. However, for the paper purpose, no commercial value of BJTs and resistor values are not used. But during manufacturing, according to market availability, BJTs will be used which have all commercial parameters and corresponding resistor values can be used within the circuit. However, this paper will provide all theoritical back-ground for making such a kind IC. So, let us now proceed to the details. Let us now draw the truth table of all LOGIC GATES except NOT and represent the outputs in form of inputs.
Table 1 A 0 0 1 1
B 0 1 0 1
OR 0 1 1 1
AND 0 0 0 1
XOR 0 1 1 0
NOR 1 0 0 0
NAND 1 1 1 0
XNOR 1 0 0 1
So,by observing it can be stated that,for.
OR GATE : Y = B when A=0 = A when A=1
AND GATE : Y=A when A=0 =B when A=1
XOR GATE : Y= B when A=0 = B’ when A=1
NOR GATE : Y= B’ when A=0 =A’ when A=1
NAND GATE : Y=A’ when A=0 =B’ when A=1
XNOR GATE : Y=B’ when A=0 =B when A=1 Now.it is seen that all the outputs are either in the form of inputs A or B or their complements according to the
input conditions of either A=0 or A=1.So, let us find the circuital approach of the above conditions.
Figure 1 Level ‘1’ represents the higher voltage level (+Vcc).Level ‘0’ represents the lower voltage level nearer to 0V but greater than 0V say 0.2 V.But, for convenience in the circuits, level ‘0’ is considered as ground. To implement all the circuits, the first condition to be noticed is separation of A when A=0 and A=1. Now figure 1 shows the circuit that can separate A=0 and A=1. When A=1,BJT is switched ON.R is such chosen that when BJT is ON, voltage level developed accross R due to flow of current equals the higher voltage level. Through A=1 path,level ‘1’ voltage flows only when A=1 and BJT is subsequently switched ON. Through A=0 path, level ‘0’ voltage can flow but also level ‘1’ voltage will flow.
User Wanted Logic Gate on a Single IC Chip
So, to prevent level ‘1’ voltage passing through level ‘0’ path affecting the next stage circuits, proper circuits have to be established.
Figure 2: Circuit Diagram of Internal Circuit
EXPLANATION OF CIRCUIT It is seen that there are 3 A=0 nad A=1 paths, for OR, AND, XOR separatively. Let us Start with OR Part For A=1,output is A.So,A=1 path is stretched to the output.A=0 path is passed through an inverter where it is converted to A=1.Now, it is connected to a BJT which is in series with another BJT fed with B. Whenever A=0, it is connected to A=1 by inverter.1st BJT switches ON. Whether 2nd BJT will switch on, it depends on B. If B=0, it switches OFF. If B=1, it switches ON. In case A=1,for B=1,output is level 1 and for B=0,output is level 0. In short, for A=1,output is B. Now, it is stated before, that through A=0 line,A=1 pulse can flow but it is prevented to effect the output because through inverter A=1 converts to A=0 which cannot switch ON the 1st BJT of the series BJT(S1). The two outputs of A=0 and A=1 paths are now joined to form the OR output. Now. Let us Deal with AND Part If we see results of AND gate,we will find that output for A=0 and A=1 are outputs for A=1 and A=0 in OR GATE respectively. So, A=1 is converted to A=0 and the nit is connected to A=0 path for OR GATE and output is obtained for A=1.A=0 path is connected to a pnp BJT which switches ON only at level 0 and thus A=1 pulse which flows through A=0 path is prevented. Now, after A=0 pulse switches ON BJT, level ‘1’ pulse is produced which is again converted to level ‘0’ pulse by an inverter. Now, A=1 and A=0 paths outputs are joined to produce AND output. Now, Let us Proceed with XOR Part If we see the result of XOR GATE, for A=0 input, we are seeing that the result is same as that of OR GATE for A=0 and the output is Y=B. So, A=0 path of XOR GATE is now connected to A=0 path of OR GATE.Now, A=1 is connected to a BJT(S3) which switches ON only for A=1.S3 is now in series with another BJT S4 which has its base fed by B.S4 switches ON only for B=1 and switches off for B=0.So, output produced is B. Now, for XOR GATE A=1 input, required output is B’.So, B produced is inverted by an inverter to produce B ‘.
Now, paths for A=0 and A=1 are merged to produce output for XOR GATE.
NOT, NAND, NOR, XNOR GATE OUTPUT All the outputs of the above gates are basically inverted outputs of some previous results.NOR,NAND,XNOR are inverted outputs of OR, AND, XOR GATES respectively.NOT is used to produce inverted output of either of inputs A or B.Inverted output is obtained by an inverter. So, a common inverter is used to connect all the outputs of A, B, OR output, AND output, XOR output. Separate inverter for each of A, B, OR output, AND output, XOR output can be used but instead this is not done because in this case excess inverters will be used and one at a time, the user generally needs anyone of them. So, a single inverter can fulfill the purpose in that case. Before the inverter, there is a switch to turn ON the inverter output.Also for NOT purpose, user needs inverted output of either A or B. There is a switch after A and B are joined between joined path of A and B and OR /AND/XOR path called NOT switch. This NOT switch plays an important role for selection between NOT and NOR/NAND/XNOR paths. The switch before inverter is kept specifically for power saving reasons.If there is no INVERTER switch,whenever OR/AND/XOR operation will be carried on,inverted operation will get carried on which is unnecessary resulting in power wastage. Now, OR, AND, XOR outputs are merged to a common terminal.Separate terminals can be used for each of OR, AND, XOR outputs but user usually needs only 1 operation and common terminal requires only 1 pin in an IC thus saving no. of pins. Similar reasoning holds for common inverter for NOT/NOR/NAND/XNOR purpose.It is possible to use separate inverters with either A or B, OR, AND, XOR purpose to produce NOT, NOR, NAND, XNOR outputs respectively. But this results in increased no. of pins in IC and inverters. But generally user needs any one of NOT/NOR/NAND/XNOR outputs. So, hardware cost can be compensated with user requirements.
INPUT TERMINAL CIRCUIT In figure 1, it was shown the circuit that separates A=0 and A=1 paths. Now, it has to be found out how an user can select any one of OR, AND, XOR operation.
Figure 3 In figure 3, it is shown that, just by switching of parallel paths A=1 and A=0 by 2-pole 3-way selector switch, OR/AND/XOR path can be selected. Before A is fed in the split circuit of figure 1,it has another path which is joined with B-path for NOT operation purpose. So, the block diagram can be drawn as follows as shown in figure 4.
Figure 4: Block Diagram
User Wanted Logic Gate on a Single IC Chip
Figure 5 The IC of user wanted logic gate on a single chip is drawn in the form of pin diagram.A 6-pin IC will be formed. Pin nos.
GND (LOW LEVEL VOLTAGE INPUT)
Vcc(HIGH LEVEL VOLTAGE INPUT) Vcc and GND inputs form the Vcc and GND voltage supply source of all transistors in the circuit.
SWITCHES ON IC
OR AND XOR switch : It is a 2-pole 3-way selector switch to select OR/AND/XOR operations.
NOT switch : It is a 1-pole 2-way selector switch to select between NOT operation and OR/AND/XOR operation.
INVERTER switch : It is a 1-pole 2-way selector switch for turning ON or OFF the inverter path.
HOW TO USE For OR/AND/XOR operation, user has to give inputs to A and B and select OR/AND/XOR position of switch, keeping inverter switch OFF and the output will be obtained from pin 5. For NOR/NAND/XNOR operation, user has to give inputs to A and B,select OR/AND/XOR position of switch respectively, select others in selection switch, keeping inverter ON, the output will be obtained from pin 4. For NOT operation, user has to provide input either to A or B, keeping NOT ON in selector switch, keeping inverter ON, the output will be obtained from pin 4.
LARGER MULTIPLE OPERATION IC Keeping 1 GND Pin and 1 Vcc Pin
2 input pins A and B
OR/AND/XOR output pin
NOT/NOR /NAND/XNOR output pin
OR-AND-XOR selection switch
INVERTER ON-OFF switch can be repeated to form multiple operations IC which will be useful to perform multiple logic gate operations one after another.
Figure 6: 3-Operation IC Pins 1,2,12,13 : 1st operation Pins 3,4,10,11 : 2nd operation Pins 5,6,8,9 : 3rd operation In this way, 3 logic gate operations can be performed one after another with the help of this IC.
CONCLUSIONS This paper is basically based to provide the theoritical back-ground to develop an IC which can perform any logic gate function as the user wants. Also, different operations of logic gates can be performed simultaneously or one after another as required by the user. The main aim is to decrease the space requirement for digital logic gate operations in the circuit and also ite eases the user’s operation because there is no requirement of memorizing which IC can perform what logic gate operation. If ICs like this can be manufactured, that will benefit both the users in labs and also in industrial designs.
ACKNOWLEDGEMENTS It is a paper based on my personal thinking and views. I would like to express my gratitude to professors of ECE department of my college, Techno India, Salt-lake for teaching me the subjects of my stream and by their guidance, I have now developed the skill of independent thinking and applying own skills in my field.In this paper, I have applied my own skills to develop whole of the contents. REFERENCES 1.
S.Salivahanan & S.Arivazhagan ; Digital circuits and design ; Chapter 3 ; Pg 77-90 ; Third Edition Reprint 2010
H.Taub & D.Schilling ; Digital Integrated Electronics ; Chapter 4 ; Pg 134-135 ; Edition 2008 Fifth reprint 2010
A.Sedra & K.Smith ; Microelectronic circuits Theory & Applications ; Chapter 3 ; Fifth Edition