Project 3: single wire multiprocessor system
Mode 3 SM0 ¼ 1 REN TI RI
187
SM1 ¼ 1 Enables serial reception Transmit interrupt flag Receive interrupt flag
SM2 ¼ 1 Multiprocessor (master with all slaves) communication SM2 ¼ 0 Dual (master with addressed slave) communication TB8 ¼ 1 Transmitted bit 8 (all slaves can be interrupted, provided SM2 ¼ 1) TB8 ¼ 0 Only addressed slave is interrupted because its SM2 ¼ 0 RB8 ¼ 1
Transmitted bit (TB8 ¼ 1) is received into slave
Initialise Slave 1 TB8 = 0 SM2 = 1
NO
Check Slave 1 address YES
Initialise Slave 2 TB8 = 0 SM2 = 1
Initialise Master TB8 = 0 SM2 = 1
Send Address Slave 1
Send Address Slave 2
TB8 = 1
Acknowledge TB8 = 0
Check Slave 2 address YES
NO
Acknowledge TB8=0 SM2 = 0
SM2 = 0 Read data
Send Slave 1 task data
Transmit data to Master
Receive Slave 1 data
SM2 = 1
SM2 = 1
Send Slave 2 task data
Read data
Receive Slave 2 data
Transmit data to Master
TB8 = 1
Figure 7.20 Communication protocol for master/slave communication
PROGRAM PLAN The main controlling bits are SM2 and TB8. SM2 ¼ 1 enables multiple processor communication. Initially the master device and all the slave devices are set up for multiple communication. When the master sets TB8 ¼ 1 it interrupts all the slave devices. In this first interrupt the master sends through its UART the address of the slave it wishes to communicate with. The chosen slave acknowledges and clears its SM2 ¼ 0. The master clears its TB8 ¼ 0. The remaining slaves continue with