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March 13-14, 2011 Shanghai, China

China Semiconductor Technology International Conference 2011 Call for Papers Abstract Deadline: October 30, 2010 Manuscript Deadline: January 10, 2011 Welcome to China Semiconductor Technology International Conference (CSTIC) 2011 to be held on March 13-14 in Shanghai, China. CSTIC is the largest annual semiconductor technology conferences for the industry in China, which is organized by SEMI and ECS. We are soliciting papers from all persons involved in the semiconductor and PV industry, including manufacturers, academic and research institutes, equipment manufacturers and materials suppliers. CSTIC 2011 has 10 symposia covering all aspects of semiconductor technology and manufacturing, including devices, lithography, integration, materials, processes as well as packaging, emerging technologies and silicon material applications. Hot topics like PV, III-V semiconductors and MEMS will also be included in the conference. CSTIC provides a platform for executives, managers, engineers and researchers to exchange the latest developments in the industry. It also offers an opportunity for those who are interested in investing in the semiconductor industry in Asia, particularly in China. CSTIC is organized by SEMI and ECS, co-organized by China's High-Tech Expert Committee (CHTEC). It is co-sponsored by IEEE-EDS, MRS and China Electronics Materials Industry Association. CSTIC 2011 will be held on March 13-14, 2011 in Shanghai, China, in conjunction with SEMICON China 2011. Prospective authors are requested to submit an abstract of 200-500 words and a 100 word biography by Oct. 30, 2010 through conference website at http://semiconchina.semi.org/cstic. The abstract must clearly describe the nature, scope, content, organization, key points and significance of the proposed paper, using the templates on the website. Presentations are to be original, non-commercial in that they focus on the technical merits of a design, a method, a structure, an integration scheme, a material or a process rather than on the individual company’s product benefits. All abstracts will be reviewed by CSTIC committees. Selected speakers will be notified no later than Nov. 20, 2010. Manuscripts of three to six pages including diagrams, figures, and photographs, are to be submitted electronically via the ECS Transaction website. The deadline for manuscript submittal is Jan. 10, 2011. English oral presentation materials are required by Feb. 10, 2011. Accepted papers for publication in conference proceedings are subject to co-copyright with ECS and SEMI, who reserves the right to republish, re-sell, and display submitted material in whole or in part. SEMI ECS Student & Engineer Award (SESEA Award) will be presented during the conference to recognize outstanding scientific and/or engineering work in fundamental or applied semiconductor industrial field by a student or young engineer in the world, particularly in China. The nominee must be a graduate student or young scientist or engineer who has contributed an accumulation of outstanding theoretical and/or experimental work in the fields of semiconductor. The age is generally younger than 35. Besides technical paper, the nominator will submit to the Award Committee documentation of the nominee’s accomplishments including a list of publications, patents, professional and educational experiences before Jan. 30, 2011. Please visit http://semiconchina.semi.org/cstic for detailed information.

Contact: April Peng, SEMI China Phone: 86.10.51906086

Fax: 86.10.51906087

E-mail: cstic@semi.org.cn 


March 13-14, 2011 Shanghai, China

Topics to be addressed at CSTIC 2011 include, but not limited to the following:

Symposium I: Design and Device Engineering • Advanced MOS devices • Memory devices (DRAM, SRAM, Flash, emerging memory devices) • RF/HV/Power devices • Device reliability • Mobility enhancement technology • Shallow junction formation • Source/drain engineering • Other emerging devices

Symposium II: Lithography and Patterning • Resist - Resist fundamentals - Cost effective photoresist for volume production - High performance photoresist - Anti-reflection schemes for advanced process - Advanced processing technology • Optical lithography - CD and overlay control in process - Immersion Lithography - Defectivity control - Cost effective RET techniques - Advanced optical imaging modeling - Advanced RET such as double patterning and polarization application - Advanced OPC & Source mask optimization - DFM solutions and Design Technology Co-optimization for 32nm node and beyond • Emergent Technology - EUV - Direct-write E-beam - Nanoimprint - Other novel lithographic techniques • Metrology - Overlay, CD, defect, and topography metrology - Integrated metrology - Advanced process control • Mask technology - Cost effective reticles for 65nm and below - Mask Defect and CD control - Advanced mask blank and EMF effect OPC for mask for 32nm node and beyond

Symposium III: Dry &Wet Etch and Cleaning • Advanced gate etching and FEOL etching - Polysilicon / metal/high-k gate stack etching, gate first and replacement gate integration schemes - 3D gate stack etching for FinFET, tri-gate - Spacer etching - CD and LER/LWR control • Advanced interconnect etching, MOL/BEOL etching - Contact, CA and self-aligned CA patterning and etching - Etching of low-k interconnecting materials - Low-k and ultra low-k trench-via patterning, mask opening, CD, profile control, damage cleaning - Etching challenges for advanced 193nm immersion lithography double exposures and double etching integrations - Advanced photo resist trimming and etching - Etching challenges for tri-layer mask integration schemes • Plasma Processing for 3D Integration, TSV, and MEMS/ NMES • Advanced memory etching and patterning - Advanced memory materials - DRAM, eDRAM, Flash memory - Advanced nonvolatile memory, such as MRAM, PCM, and other new memory devices • Advanced plasma sources and process control • Photo resist stripping and clean • Post plasma treatment cleaning • Wet etching and cleaning

Symposium IV: Thin Film Technology • High k gate dielectrics and metal gates thin film materials, processes and integration schemes • Thin film processes and materials for straining engineering, including SiGe, SiC, stress liners and SMT • Advanced channel materials, such as Ge and III/V channels, related topics and integration schemes, including Ge passivation. • Processes, properties, integration and reliability for low k dielectric materials • Thin film processes and materials for high aspect ration gap fill • Self-aligned silicides, Schottky barrier source/drain and advanced contact technologies • Electroplating and electroless deposition materials and processes • Silicon nanowire, carbon nano tube, graphene or other new materials for FET, metallization, dielectrics, contacts, strain and channels.

CHTEC SEMI China Room 201, 295 Zuchongzhi Road, Zhangjiang, Shanghai, 201203, China

ECS - Electrochemical Society 65 South Main Street, Building D, Pennington, NJ 08534-2839 USA

China's High-Tech Expert Committee No.9 building, Xiyuan Hotel 1 Sanlihe Road, Beijing 100044,China




March 13-14, 2011 Shanghai, China

Symposium V: CMP and Post-CMP Cleaning • CMP Manufacturing Process, Equipment and Materials Challenges - Defect reduction: Micro-scratch, dishing, erosion and defects - Defect inspection: In-line or off-line defect monitoring - Process integration: Low K / Cu, high K / metal gate and others - Process control: End-point detection using optical, eddy current, shear force, motor current and other methods - Post-cleaning: Equipment, processes and chemistries - Equipment: Productivity and process flexibility and low shear force polishing - Consumables: Slurry, pad, conditioning disc, retaining ring, brush rollers and others • New Polishing and Cleaning Technologies - Phase change materials, HOT CMP, MEMS and polymer polishing - Equipment, processes, cleaning chemistry and consumables • Modeling, Simulation and Fundamental Characterization of CMP - Pattern density, dummy feature and CMP design rules - Tribology, process physics and chemistry, wafer-slurry-pad interactions

Symposium VI: Materials and Process Integration for Device and Interconnection • Key process module development and integration • Material for 45nm and 32nm manufacturing • Reliability of copper/low-k interconnect • High-k/metal gate and future transistors • Plasma assisted material process • Implantation and millisecond anneal • Strained silicon process and integration • Cleaning technology in manufacturing • Innovative metrology for 45nm and beyond

Symposium VII: Packaging and Assembly • 3DIC/WLSCP/TSV process and reliability • FC/MCP/die stacking/package stacking • Embedded active/passive integration • MEMS and sensor packaging technology • RF and microwave packaging technology • LED and photovoltaic packaging technology • Emerging technology/Nanotechnology • Future packaging materials • Interconnect

• Thermal mechanical/electrical/thermal modeling • HDI/high performance interposer design and manufacturing • Thermal management/active cooling • Supply chain management

Symposium VIII: Metrology, Reliability and Testing • Metrology - Applications to ICs, thin film heads, systems-on-a-chip, and thin film device manufacturing - Breakthroughs and advancements in electron/Ion microscopy calibration and accuracy - Critical dimension metrologies - Defect detection, analysis, and control - Limits of metrology and inspection systems - Mask related metrology - Measurement system modeling and simulation - Metrology and inspection methodologies - Overlay, registration, and alignment metrologies - Process control, characterization, and yield enhancement • Reliability - MEMS reliability - Nano-electronic device reliability - Package/assembly reliability - Product reliability and burn-in - Reliability in designs and circuits - Reliability in device and process - Reliability in interconnects - Reliability qualification strategies • Test - ATE hardware and software - ATPG, test synthesis - Design-for-Test: chip, board, system - Design and test for reliability - Diagnostics - IDDQ and current test - Memory test - Microprocessor Test - Mixed-Signal and Analog Test - Power issues in test - System-on-Chip test - System-in-Package test - Test and design for manufacturability - Test for nanometer technologies - 3D integrated circuits testing

CHTEC SEMI China Room 201, 295 Zuchongzhi Road, Zhangjiang, Shanghai, 201203, China

ECS - Electrochemical Society 65 South Main Street, Building D, Pennington, NJ 08534-2839 USA

China's High-Tech Expert Committee No.9 building, Xiyuan Hotel 1 Sanlihe Road, Beijing 100044,China




March 13-14, 2011 Shanghai, China

Symposium IX: Emerging Semiconductor Technologies • Extension of Si CMOS technology: FinFETs: Si nanowire-based FETs, Ultra-thin SOI technology, III-V Semiconductors • 3D integration and through silicon via technology • Post-CMOS device options - Growth, assembly and device /system demonstration of carbon nanoelectronics: nanotubes, graphene - Spintronics, Molecular electronics, Single electron transistors, Quantum dots - Simulation and modeling of post-CMOS devices - Other novel device concepts and demonstration • Novel memory technologies - Magnetic memor y (MRAM), Phase change memor y, Resistive memory, Ferroelectric memory - Recent advances in DRAM, NAND memory technologies • Light Emitting Diode (LED) Technology - Solid Sate Lighting Technology: Design, Materials, Devices, Systems, Testing and Standards - Organic LEDs - Applications of LEDs: Backlighting for Liquid Crystal Display, Indoors and Outdoor Lighting, Energy Efficient Lighting • Organic and plastic semiconductors, flexible electronics - Synthesis and device demonstration of novel organic semiconducting materials - Organic electronics for RFID, memory, display, photovoltaic applications - Low-cost processing of organic electronics, such as solution processing and roll-to-roll processing • Photonics, future interconnects, optoelectronic devices - Si photonics, nanophotonics, optical interconnects, carbon nanotube-based interconnects - Novel interconnect concepts, such as photo-patternable low-k and nanoimprint of interconnect structures - Optoelectronic materials and devices

• Emerging lithography and non-traditional pattern techniques - EUV lithography: optics, light sources, masks, resists, patterning and integration demonstration - Nanoimprint lithography: Concept, mask making, materials, patterning and integration demonstration - Self-assembly and directed-assembly patter ning: material synthesis, patterning, defect-reduction and device demonstration - Other non-traditional patterning techniques • Other Applications of semiconductor devices and processes - Energy generation, conversation and storage devices and systems, such as solar cells, battery technology, supercapacitors - Sensors MEMS, Bio-MEMS, LEDs, Micro-fluidics and biomedical devices, Bio-chips • Environmentally-friendly and energ y-efficient semiconductor manufacturing

Symposium X: Silicon Materials for Electronic and Photovoltaic Applications • Silicon materials production, characterization and process modeling • Crystallization and impurity control • Emerging materials, SOI and strained engineering. annealed silicon • Bulk wafer processing for solar and semiconductor industries • Material technology for 450mm wafers • Crystalline silicon and thin film solar cell • Thin film transistors and light conversion efficiency • Solar cell device physics, applications, testing and reliability • Solar power generation and market trend

CHTEC SEMI China Room 201, 295 Zuchongzhi Road, Zhangjiang, Shanghai, 201203, China

ECS - Electrochemical Society 65 South Main Street, Building D, Pennington, NJ 08534-2839 USA

China's High-Tech Expert Committee No.9 building, Xiyuan Hotel 1 Sanlihe Road, Beijing 100044,China



http://semiconchina.org/downloadFile/1289284920656  

http://semiconchina.org/downloadFile/1289284920656.pdf

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