Issuu on Google+

MODELING OF LDMOS TRANSISTOR Presented by: NAME: Pritam Bhattacharjee STREAM: Electronics & Communication Engineering – VLSI UNIVERSITY ROLL NO.: 12614911006 UNIVERSITY REGISTRATION NO.: 111260410106 HERITAGE INSTITUTE OF TECHNOLOGY, KOLKATA.

IN GUIDANCE OF: Prof. Atanu Kundu, Assistant Professor Department of Electronics & Communication Engineering, Heritage Institute of Technology, Kolkata.


INTRODUCTION Motivation for the research & study 1. With the advance of process technologies, new device structures are required for handling high power in efficient manner. 2. Double diffused MOS structures evolved as the solution for high power handling & its correspondings. 3. Introduction of lightly doped drain (LDD) region at the drain extension. 4. But, there is a trade-off, i.e., designing for high breakdown voltage degrades the on-resistance and vice-versa. 5. The trade-off can possible be overcome by introduction of reduced surface field (RESURF) concept. 6. A surface-potential based model (MOS Model 20) will be taken as reference for the modeling purpose.


TOOLS USED TCAD (for process simulation: T-SUPREME-4 for device simulation: MEDICI) TANNER EDA v15 S-EDIT & T-SPICE MOS MODEL 20


EVOLUTION OF LDMOS

Principle of RESURF Proposed LDMOS structure & its operation Proposed device measurements Capacitance modeling Simulations & Results


PRINCIPLE OF RESURF Cross-section of RESURF diode

An improved RESURF LDMOS


RESURF (contd....) Breakdown voltage calculation: i. BV_ds= E_lat * L_drift Another way of calculating the breakdown voltage following the RESURF technology is, ii. BV_lat= ε * (E_c)^2 / (2 * q * N_epi) On-resistance calculation: R_ON= ρ * L_drift / (W * t_drift) = R_sh * L_drift / W


PROPOSED DEVICE STRUCTURE


PROPOSED DEVICE MEASUREMENTS


ELECTRICAL MODEL OF THE DEVICE


SMALL SIGNAL ANALYSIS OF THE ELECTRICAL MODEL


EXTRACTED PARAMETERS (Capacitance & Transconductance)


SIMULATIONS & RESULTS


SIMULATIONS & RESULTS (Contd....)


SIMULATIONS & RESULTS (Contd....)


SIMULATIONS & RESULTS (Contd....)

Best Ron recieved at dope level = 1E12


SIMULATIONS & RESULTS (Contd....) Schematic of the electrical model in TannerEDA S-Edit


SIMULATIONS & RESULTS (Contd....) T-SPICE NETLIST subckt Cell0 D G Gnd *-------- Devices With SPICE.ORDER > 0.0 -------CCapacitor_1 N_2 N_1 1p $ $x=2300 $y=5900 $w=600 $h=400 $r=270 CCapacitor_2 N_1 D 1p $ $x=5000 $y=5900 $w=600 $h=400 $r=270 CCapacitor_3 N_1 N_3 1p $ $x=2800 $y=5100 $w=400 $h=600 CCapacitor_4 N_3 N_4 1p $ $x=2800 $y=4200 $w=400 $h=600 CCapacitor_5 N_5 Gnd 1p $ $x=7300 $y=1400 $w=400 $h=600 RResistor_1 G N_2 R=10k $ $x=1400 $y=5914 $w=600 $h=149 RResistor_2 N_6 N_4 R=10k $ $x=2785 $y=3500 $w=149 $h=600 $r=270 RResistor_3 Gnd N_6 R=10k $ $x=2785 $y=2700 $w=149 $h=600 $r=270 RResistor_4 N_5 D R=10k $ $x=7285 $y=3000 $w=149 $h=600 $r=270 EResistor_5 D Gnd G Gnd 1 $ $x=5900 $y=4300 $w=600 $h=600 .ends *-------- Devices With SPICE.ORDER == 0.0 -------***** Top Level ***** XCell0_1 N_1 N_2 Gnd Cell0 $ $x=4500 $y=3900 $w=1800 $h=1000 *-------- Devices With SPICE.ORDER > 0.0 -------VVoltageSource_1 N_2 Gnd DC 5 $ $x=3600 $y=3200 $w=400 $h=600 VVoltageSource_2 N_1 Gnd DC 5 $ $x=5400 $y=3300 $w=400 $h=600 26 ********* Simulation Settings - Additional SPICE Commands ********* .dc VVoltageSource_1 0 1 0.01 VVoltageSource_2 0 1 0.1 .print i(XCell0_1) .end


ACKNOWLEDGEMENT I cordially thank my guide Prof. Atanu Kundu, Department of Electronics & Communication Engineering, HITK, for his immense effort in guiding me throughout the project. I thank Heritage Institute of Technology, Kolkata, for providing me infrastructure and environment to work. Last but not least, I really friends and my teachers encourging me all the time.

thank my parents, for inspiring and


REFERENCES [1] “Modelling of the ON-Resistance of LDMOS, VDMOS, and VMOS Power Transistors” by S.C. SUN and JAMES D. PLUMBER, member IEEE @1980 IEEE. [2] “Design of Complementary LDMOS in 0.35μm BiCMOS technology for Smart Integration ” by MOHAMED ABOUELATTA-EBRAHIM, CHRISTIAN GONTRAND and ABDELHALIM ZEKRY published @ “The European Physical Journal Applied Physics 57,1 (2012) 10103" DOI : 10.1051/epjap/2011100138”. [3] H.J. SIGG, G. D. VENDELIN, T.P. CAUGE and J. KOCSIS, “D-MOS transistor for microwave applications”, IEEE Trans. Electron Devices, vol. ED-19, pp. 45-53, Jan. 1972. [4] V. A. K. TEMPLE and R. P. LOVE, “A 600 volt MOSFET with near ideal on resistance”, in IEDM Conf. Dig., pp. 664-666, 1978. [5] “A Review of RESURF Technology” by ADRIAAN W. LUDIKHUIZE, Philips Research, Eindhoven, The Netherlands. [6] “Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design” by AVINASH S. KASHYAP, Student Member, IEEE, H. ALAN MANHOTH, Fellow, IEEE, TUAN A. VO and MOHAMMAD MOJARRADI, IEEE Transactions on Electron Devices, VOL 57, No. 6 @JUNE 2010.


THANK YOU!


BACK-UP SLIDES


MOS MODEL 20 Model Structure


CURRENT INTO EACH TERMINAL


Surface-charge Equations


CHANNEL CURRENT

which yields to, through the channel range as,


Modeling of LDMOS Transistor