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My Report Multilevel Diode Clamped Inverters

By Xi Xiaodan No: 3100104733


Abstract This project is focused on the goal to investigate the performance of multilevel diode clamped inverters with carrier based modulation schemes, and the influence of third harmonic injection into the multilevel diode clamped inverter. The project is divided into four parts. The first part is to state some basic theories about the multilevel diode clamped inverter, including the circuit of the diode clamped inverter, the switching states, commutation and PWM carrier-based modulation. The second part is to build a Matlab/Simulink model to simulate the three-level and fourlevel diode clamped inverters according to the specific requirements and compare their results. The third part is to search for the influence with the method of third harmonic injection into the three-level and four-level diode clamped inverters. Finally, we get the conclusion of the simulations in this project, that as the modulation index ma decreases, the THD of vA and vAB increases, and the dc bus utilization decreases sharply. Three-level inverter has a lower THD than the four-level one, but also a higher dc bus utilization than the latter. And after injecting third harmonic waves into the modulating wave, the inverter fundamental voltage VAB1 increases, and at the same time, the THD of also increases.


Content Abstract ............................................................................................................................................................... 2 1.

Introduction ................................................................................................................................................. 4

2.

Basic theory of Multilevel Diode Clamped Inverters .................................................................................. 4

3.

2.1

Circuit of Multilevel Diode Clamped Inverters ................................................................................... 4

2.2

Switching States ................................................................................................................................... 4

2.3

Commutation ........................................................................................................................................ 6

2.4

Carrier-Based PWM ............................................................................................................................. 6

Multilevel Diode Clamped Inverter Modeling and Simulation ................................................................... 8 3.1

System Specifications .......................................................................................................................... 8

3.2

Diode Clamped Inverter Modeling....................................................................................................... 8

3.2.1 Three-Level Diode Clamped Inverter Modeling ................................................................................ 8 3.2.2 Four-Level Diode Clamped Inverter Modeling ................................................................................ 10 3.3

Simulation Results of Three-Level Diode Clamped Inverter ............................................................. 12

3.3.1 Three-Level Diode Clamped Inverter (IPD)..................................................................................... 12 3.3.2 Three-Level Diode Clamped Inverter (APOD) ................................................................................ 14 3.4

Simulation Results of Four-Level Diode Clamped Inverter............................................................... 16

3.3.1 Four-Level Diode Clamped Inverter (IPD) ...................................................................................... 16 3.3.2 Four-Level Diode Clamped Inverter (APOD) .................................................................................. 18 3.5 4.

5.

Conclusions ........................................................................................................................................ 20

Third Harmonic Injection PWM in Multilevel Diode Clamped Inverters................................................. 21 4.1

Theory and Simulation of Third Harmonic Injection PWM .............................................................. 21

4.2

Conclusion.......................................................................................................................................... 23

Conclusions ............................................................................................................................................... 23

References ......................................................................................................................................................... 23


1. Introduction The diode-clamped multilevel inverter employs clamping diodes and cascaded dc capacitors to produce ac voltage waveforms with multiple levels. The inverter can be generally configured as a three-, four-, or five-level topology, but only the three-level inverter, often known as neutral-point clamped (NPC) inverter, has found wide application in high-power medium-voltage (MV) drives [1–3]. The main features of the NPC inverter include reduced dv/dt and THD in its ac output voltages in comparison to the two-level inverter. In this essay, two methods of SPWM modulation is discussed, thus IPD and APOD. Besides, we do some research about the third harmonic injection used in diode clamped inverters. It is proved that both IPD and APOD have advantages and disadvantages, and that third harmonic injection can improve the dc voltage utilization.

2. Basic theory of Multilevel Diode Clamped Inverters 2.1 Circuit of Multilevel Diode Clamped Inverters Fig 2.1-1 shows the simplified circuit diagram of a three-level NPC inverter. The inverter leg A is composed of four active switches S1 to S4 with four antiparallel diodes D1 to D4. In practice, either IGBT or GCT can be employed as a switching device.

Fig 2.1-1 Three-level NPC inverter

On the dc side of the inverter, the dc bus capacitor is split into two, providing a neutral point Z. The diodes connected to the neutral point, DZ1 and DZ2, are the clamping diodes. When switches S2 and S3 are turned on, the inverter output terminal A is connected to the neutral point through one of the clamping diodes. The voltage across each of the dc capacitors is E, which is normally equal to half of the total dc voltage Vd. With a finite value for Cd1 and Cd2, the capacitors can be charged or discharged by neutral current iZ, causing neutral-point voltage deviation. This issue will be further discussed in the later sections.

2.2 Switching States The operating status of the switches in the NPC inverter can be represented by switching states shown in Tab 2.2-1. Switching state ‘P’ denotes that the upper two switches in leg A are on and the inverter terminal voltage vAZ,


which is the voltage at terminal A with respect to the neutral point Z, is +E, whereas ‘N’ indicates that the lower two switches conduct, leading to vAZ = –E. Switching state ‘O’ signifies that the inner two switches S2 and S3 are on and vAZ is clamped to zero through the clamping diodes. Depending on the direction of load current iA, one of the two clamping diodes is turned on. For instance, a positive load current (iA > 0) forces DZ1 to turn on, and the terminal A is connected to the neutral point Z through the conduction of DZ1 and S2. It can be observed from Tab 2.2-1 that switches S1 and S3 operate in a complementary manner. With one switched on, the other must be off. Similarly, S2 and S4 are a complementary pair as well. Fig 2.2-1 shows an example of switching state and gate signal arrangements, where vg1 to vg4 are the gate signals for S1 to S4, respectively. The gate signals can be generated by carrier-based modulation, space vector modulation, or selective harmonic elimination schemes. The waveform for vAZ has three voltage levels, +E, 0, and –E, based on which the inverter is referred to as a three-level inverter. Fig 2.2-2 shows how the line-to-line voltage waveform is obtained. The inverter terminal voltages vAZ, vBZ, and vCZ are three-phase balanced with a phase shift of 2π/3 between each other. The line-to-line voltage vAB can be found from vAB = vAZ – vBZ, which contains five voltage levels (+2E, +E, 0, –E, and –2E).

Tab 2.2-1 Definition of Switching States

Fig 2.2-1 Switching states, gate signals and inverter terminal voltage vAZ

Fig 2.2-2 Inverter terminal and line-to-line voltage waveforms


2.3 Commutation To investigate the commutation of switching devices in the NPC inverter, consider a transition from switching state [O] to [P] by turning S3 off and turning S1 on. Fig 2.3-1a shows the gate signals vg1 to vg4 for switches S1 to S4, respectively. Similar to the gating arrangement in the two-level inverter, a blanking time of _ is required for the complementary switch pair S1 and S3. Fig 2.3-1b and 2.3-1c show the circuit diagram of the inverter leg A during commutation, where each of the active switches has a parallel resistor for static voltage sharing. According to the direction of the phase A load current iA, the following two cases are investigated.

Fig 2.3-1 Commutation during a transition from switching state [O] to [P]

2.4 Carrier-Based PWM The carrier-based modulation schemes for cascaded Hbridge multilevel inverters can also be used for the diode-


clamped inverters. Fig 2.4-2 illustrates the simulated waveforms of a four-level inverter modulated by an in-phase disposition (IPD) modulation scheme. The four-level inverter requires three carriers vcr1, vcr2, and vcr3, which are disposed vertically, but all in phase. The amplitude modulation index ma is equal to 0.9, and frequency modulation index mf is 15. The gate signals vg1,vg2, and vg3 for the top three switches S1, S2, and S3 in Fig 2.4-1 are generated at the intersections of the carrier waves and phase A modulation wave vmA, respectively. The gatings for the bottom three devices S1’, S2’, and S3’ are complementary to vg1, vg2, and vg3 and therefore are not shown.

Fig 2.4-1 Per-phase diagram of four-level diode-clamped inverters

Fig 2.4-2 Simulated waveforms in the four-level inverter using IPD modulation (f1 = 60 Hz, fsw,dev = 300 Hz, ma = 0.9, and mf = 15).


3. Multilevel Diode Clamped Inverter Modeling and Simulation 3.1 System Specifications The requirements of this project is shown as follows: Inverter Configuration:

Three- and four-level diode clamped inverters

Rated Inverter Output Voltage: 6.6KV (rms fundamental line-to-line voltage) Rated Inverter Output Power: 5MVA (three-phase) Rated Inverter Output Frequency: 60Hz dc link voltage:

Constant, ripple free.

Total dc link voltage:

To be determined.

Use two identical dc voltage sources for the three-level inverter and three identical dc voltage sources for the four-level inverter. Inverter load:

Three-phase balanced RL load with a lagging power factor of 0.9 at the rated frequency of 60Hz.

The inverter has the output with a fundamental line-to-line voltage of 6600V (rms) at the modulation index of ma = 1.0. So we can calculate the dc link voltage as: Vd 

Vol 6600   9335.22V 0.707 0.707

(1.1)

For the three-level inverter, the dc voltage source is E  Vd / 2  4667.61V , and for the four-level inverter, the dc voltage source is E  Vd / 3  3111.74V . And the load resistance:

Rload

U 

   6600 / 3  2

ol

/ 3

P/3

2

 8.712

(1.2)

L 11.19mH

(1.3)

5 106 / 3

And we can determine the inductance as: Rload Rload 2   L 

2

 0.9

3.2 Diode Clamped Inverter Modeling 3.2.1 Three-Level Diode Clamped Inverter Modeling We can build the model of three-phase three-level diode clamped inverter in Simulink as follows:


Fig3.2.1-1 Three-level diode clamped inverter model in Simulink

In the model, the sub-system SPWM is shown as follows (in IPD and APOD modes):

Fig3.2.1-2 Sub-system SPWM in IPD mode

Fig3.2.1-3 Sub-system SPWM in APOD mode

And the sub-system NPC is:


Fig3.2.1-4 Subsystem NPC

3.2.2 Four-Level Diode Clamped Inverter Modeling We can build the model of three-phase three-level diode clamped inverter in Simulink as follows:

Fig3.2.2-1 Four-level diode clamped inverter model in Simulink

In the model, the sub-system SPWM is shown as follows (in IPD and APOD modes):


Fig3.2.2-2 Sub-system SPWM in IPD mode

Fig3.2.2-3 Sub-system SPWM in APOD mode

And the sub-system NPC is:


Fig3.2.2-4 Subsystem NPC

3.3 Simulation Results of Three-Level Diode Clamped Inverter 3.3.1 Three-Level Diode Clamped Inverter (IPD) We can get the results of three-level diode clamped inverter with fI =60Hz, ma =1.0, mf =15.0 as follows:


Fig 3.3.1-1 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =1.0

We can get the results of three-level diode clamped inverter with fI =60Hz, ma =0.3, mf =15.0 as follows:


Fig 3.3.1-2 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =0.3

3.3.2 Three-Level Diode Clamped Inverter (APOD) We can get the results of three-level diode clamped inverter with fI =60Hz, ma =1.0, mf =15.0 as follows:


Fig 3.3.2-1 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =1.0

We can get the results of three-level diode clamped inverter with fI =60Hz, ma =1.0, mf =15.0 as follows:


Fig 3.3.2-2 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =0.3

3.4 Simulation Results of Four-Level Diode Clamped Inverter 3.4.1 Four-Level Diode Clamped Inverter (IPD) We can get the results of four-level diode clamped inverter with fI =60Hz, ma =1.0, mf =15.0 as follows:


Fig 3.4.1-1 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =1.0

We can get the results of four-level diode clamped inverter with fI =60Hz, ma =0.6, mf =15.0 as follows:


Fig 3.4.1-1 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =0.6

3.4.2 Four-Level Diode Clamped Inverter (APOD) We can get the results of four-level diode clamped inverter with fI =60Hz, ma =1.0, mf =15.0 as follows:


Fig 3.4.2-1 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =1.0

We can get the results of four-level diode clamped inverter with fI =60Hz, ma =0.6, mf =15.0 as follows:


Fig 3.4.2-2 Voltage waveforms vAN, vAB, iA and their harmonic spectrum with fI =60Hz and ma =0.6

3.5 Conclusions (1) The results show that in a three-level and four-level diode clamped inverter, the harmonics appear as sidebands centered around the frequency modulation index mf and its multiples such as 2mf and 3mf.


(2) We can also get the conclusion that as the modulation index ma decreases, the THD of vA and vAB increases, and the dc bus utilization decreases sharply, which are not expected to see. (3) From the comparison of three-level and four-level diode clamped inverters, we can know that generally speaking, three-level inverter has a lower THD than the four-level one, but also a higher dc bus utilization than the latter, which we should consider in specific conditions.

4. Third Harmonic Injection PWM in Multilevel Diode Clamped Inverters 4.1 Theory and Simulation of Third Harmonic Injection PWM The inverter fundamental voltage VAB1 can be increased by adding a third harmonic component to the threephase sinusoidal modulating wave without causing over-modulation. This modulation technique is known as third harmonic injection PWM.

Fig 4.1-1 Modulation wave after third harmonic injection

Fig 4.1-2 shows the modulation waves and gate signals in a three-level and four-level diode clamped inverter.


Three-level inverter

Four-level inverter Fig 4.1-2 The production and wave of the modulating wave with third harmonic injection in a multilevel inverter

Fig 4.1-3 and Fig 4.1-4 shows the comparison of voltage waveform vAB and its harmonic spectrum with third harmonic injection (in three-level inverter and four-level inverter).

Fig 4.1-3 Voltage waveform vAB and its harmonic spectrum with fI =60Hz and ma =1.0 (Three-level inverter)


Fig 4.1-4 Voltage waveform vAB and its harmonic spectrum with fI =60Hz and ma =1.0 (four-level inverter)

4.2 Conclusion From the results comparison, we can know that after injecting third harmonic waves into the modulating wave, the inverter fundamental voltage VAB1 increases from 8146V to 8149V (three-level inverter), from 8081V to 8096V (four-level inverter), which means that the third harmonic injection can raise dc bus utilization of the inverter. But at the same time, the THD of also increases, which is not expected.

5. Conclusions In this project, we do some research about multilevel diode clamped inverters, build practical models of threelevel and four-level inverters, and finish the simulation in Simulink. From the results, we can come to the following conclusions. In a three-level and four-level diode clamped inverter, the harmonics appear as sidebands centered around the frequency modulation index mf and its multiples such as 2mf and 3mf. And as the modulation index ma decreases, the THD of vA and vAB increases, and the dc bus utilization decreases sharply, which are not expected to see. Generally speaking, three-level inverter has a lower THD than the four-level one, but also a higher dc bus utilization than the latter, which we should consider in specific conditions. After injecting third harmonic waves into the modulating wave, the inverter fundamental voltage VAB1 increases, which means that the third harmonic injection can raise dc bus utilization of the inverter. But at the same time, the THD of also increases, which is not expected.

References [1] Bin Wu. High Power Converters and AC Drives. IEEE Press [2] DURGA PRASAD REDDY, J V G RAMA RAO. Simulation and Comparison of Single Phase Multi High Level Inverter for Different Loads. International Journal of Engineering Science and Technology (IJEST) [3] BHASKAR REDDY, SAI BABU. Comparison of Modulation Techniques for Multilevel Inverter fed Permanent Magnet Synchronous Motor. International Journal of Engineering Science and Technology (IJEST)


Project multilevel diode clamped inverters