Page 1

p. 6 Editor’s Foreword Celebrating VME’s strength and endurance

p. 20 Special Feature VITA Technologies Hall of Fame


Let’s face it: what’s probably top of your mind is how to ensure your program stands the best chance of success: getting to deployment faster, at lower cost and with less risk. That’s what your customers are demanding.

WE INNOVATE. WE DELIVER. YOU SUCCEED.

At Abaco Systems, that’s our business. We could talk forever about how everything we do is based on industry standards and modular, open architectures – but that’s not so important. It’s just a starting point for our innovation. What’s important is that you work with a company with the experience to back up our promises, and that’s entirely committed to your success.

Find out more at abaco.com or follow us @AbacoSys

That company is Abaco Systems. ©2016 Abaco Systems. All rights reserved. All other brands, names or trademarks are property of their respective holders.


SPRING/SUMMER 2016 | VOLUME 34 | NUMBER 1

@VitaTechnology

On the cover The VITA Technologies 2016 Resource Guide showcases technologies based on VITA standards, including FMC, OpenVPX, XMC/PMC, and related rugged boards, systems, and components. Featured on the cover: Annapolis Micro Systems Wild40 Ecosystem for OpenVPX 3U and CurtissWright Defense Solutions AFT Cooled 3U VPX COTS System. FMC+ standard propels embedded design to new heights » p. 10

By Jeremy Banks, Curtiss-Wright, and Jim Everett, Xilinx

ADDITIONAL FEATURES

20 Special Feature

Jerry Gipper

VITA Technology Hall of Fame 2016 DEPARTMENTS

6 Editor’s Foreword

Jerry Gipper

Celebrating VME’s strength and endurance

8 VITA Standards Update Very high-speed sampling and serial ADCs in embedded systems » p. 14

By Thierry Wastiaux, Interface Concept

Jerry Gipper

VITA Standards Organization activity updates

22 Primetime Choices 24 VITA Technologies Resource Guide FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OpenVPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Systems and Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Small Form Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Modular Open Radio Frequency Architecture boot camp » p. 17

VPX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 XMC/PMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

By Jerry Gipper, Editorial Director All registered brands and trademarks within VITA Technologies magazine are the property of their respective owners. ™VPX and its logo is a registered product/trademark of VITA. © 2016 OpenSystems Media © 2016 VITA Technologies enviroink.indd 1

4 | VITA Technologies Resource Guide Spring/Summer 2016

10/1/08 10:44:38 AM

www.vita-technologies.com


Advertiser Index 2

Abaco Systems – We innovate. We deliver. You succeed.

3

Annapolis Micro Systems, Inc. – WILDSTAR OpenVPX Ecosystem

15

Elma Electronic – We take our leadership role seriously

7

Excalibur Systems, Inc. – mil-1553.com

24

Highland Technology, Inc. – Continuing our long term commitment to VME

9

Interface Concept – Build your own VPX system

13

LCR Embedded Systems – Rugged chassis, backplanes, and integrated systems

19

Pentair Electronics Protection – VPX & VME systems chassis and front panels express delivery

STRATEGIC ACCOUNT MANAGER Bill Barron bbarron@opensystemsmedia.com (516) 376-9838

48

STRATEGIC ACCOUNT MANAGER Eric Henry ehenry@opensystemsmedia.com (541) 760-5361

Pentek, Inc. – Got tough software radio design challenges?

16

Themis Computer – NanoSWITCH

23

Vector Electronics & Technology, Inc. – VME/VXS/cPCI chassis, backplanes & accessories

18

VEROTEC Electronics Packaging – 19" desktop cases, integrated systems, card cages and components

EDITORIAL DIRECTOR Jerry Gipper jgipper@opensystemsmedia.com MANAGING EDITOR Jennifer Hesse jhesse@opensystemsmedia.com GROUP EDITORIAL DIRECTOR John McHale jmchale@opensystemsmedia.com E-CAST MANAGER Joy Gilmore jgilmore@opensystemsmedia.com CREATIVE DIRECTOR Steph Sweet ssweet@opensystemsmedia.com DIGITAL MEDIA MANAGER Rachel Wallace rwallace@opensystemsmedia.com SENIOR WEB DEVELOPER Konrad Witte kwitte@opensystemsmedia.com WEB DEVELOPER Paul Nelson pnelson@opensystemsmedia.com CONTRIBUTING DESIGNER Joann Toth jtoth@opensystemsmedia.com

SALES SALES MANAGER Tom Varcie tvarcie@opensystemsmedia.com (586) 415-6500 STRATEGIC ACCOUNT MANAGER Rebecca Barker rbarker@opensystemsmedia.com (281) 724-8021

STRATEGIC ACCOUNT MANAGER Kathleen Wackowski kwackowski@opensystemsmedia.com (978) 888-7367 SOUTHERN CALIFORNIA REGIONAL SALES MANAGER Len Pettek lpettek@opensystemsmedia.com (805) 231-9582 SOUTHWEST REGIONAL SALES MANAGER Barbara Quinlan bquinlan@opensystemsmedia.com (480) 236-8818 NORTHERN CALIFORNIA REGIONAL SALES MANAGER Twyla Sulesky tsulesky@opensystemsmedia.com (408) 779-0005 ASIA-PACIFIC SALES ACCOUNT MANAGER Elvi Lee elvi@aceforum.com.tw EUROPE SALES ACCOUNT MANAGER James Rhoades-Brown james.rhoadesbrown@husonmedia.com

ECASTS WWW.OPENSYSTEMSMEDIA.COM PUBLISHER Patrick Hopper phopper@opensystemsmedia.com PRESIDENT Rosemary Kristoff rkristoff@opensystemsmedia.com EXECUTIVE VICE PRESIDENT John McHale jmchale@opensystemsmedia.com

Space Rovers and Surgical Robots: System Architecture Lessons from Mars May 5 2:00 p.m. EDT

EXECUTIVE VICE PRESIDENT Rich Nass rnass@opensystemsmedia.com CHIEF TECHNICAL OFFICER Wayne Kristoff ASSISTANT MANAGING EDITOR Lisa Daigle ldaigle@opensystemsmedia.com SENIOR EDITOR Sally Cole scole@opensystemsmedia.com ASSOCIATE EDITOR Mariana Iriarte miriarte@opensystemsmedia.com PICMG EDITORIAL DIRECTOR Joe Pavlat jpavlat@opensystemsmedia.com

Solving Aerospace Tech Development Challenges June 7 2:00 p.m. EDT

EMBEDDED COMPUTING BRAND DIRECTOR Rich Nass rnass@opensystemsmedia.com EMBEDDED COMPUTING EDITORIAL DIRECTOR Curt Schwaderer cschwaderer@opensystemsmedia.com TECHNOLOGY EDITOR Brandon Lewis blewis@opensystemsmedia.com

ecast.opensystemsmedia.com

TECHNICAL CONTRIBUTOR Rory Dear rdear@opensystemsmedia.com CREATIVE PROJECTS Chris Rassiccia crassiccia@opensystemsmedia.com FINANCIAL ASSISTANT Emily Verhoeks everhoeks@opensystemsmedia.com SUBSCRIPTION MANAGER subscriptions@opensystemsmedia.com CORPORATE OFFICE 16626 E. Avenue of the Fountains, Ste. 201 • Fountain Hills, AZ 85268 • Tel: (480) 967-5581 SALES AND MARKETING OFFICE 30233 Jefferson • St. Clair Shores, MI 48082

EVENTS XPONENTIAL 2016 May 2-5 New Orleans, Louisiana www.xponential.org

REPRINTS WRIGHT’S MEDIA REPRINT COORDINATOR Wyndell Hamilton whamilton@wrightsmedia.com (281) 419-5725

www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

5


Editor’s Foreword By Jerry Gipper, Editorial Director @VitaTechnology

jgipper@opensystemsmedia.com

Celebrating VME’s strength and endurance Embedded Tech Trends 2016 is now in the books. We had a record number of sponsors and media representatives at the event, which is a business and technology forum focused on the critical and intelligent embedded systems industry. The theme this year was “Houston – We have a problem!” All of the presentations and associated videos have been posted to the Embedded Tech Trends website at www.embeddedtechtrends.com. Last year was a very busy time at VITA. Twenty-two new members joined from companies around the world, truly reflecting the international significance of the organization. These memberships were driven primarily by the growing popularity of VPX and FMC. The activity level is high for standards development and design-wins for both of these technologies. At the same time, we are preparing to celebrate the 35th anniversary of the announcement of VMEbus. Looking back, it is hard to imagine the strength and longevity of VME. I had graduated from college and was just getting my feet wet in the world of embedded computing when it debuted. Please feel free to visit our LinkedIn site to add your own comments to the conversation. I will be pulling comments and stories from the LinkedIn conversation to be published in our 35th anniversary feature in the Fall/ Winter issue. New products based on VMEbus continue to be introduced today, as evidenced by some of my Primetime product selections. News from CurtissWright that they have developed an FPGA-based PCI Express to VME64x bridge chip with a 15-year life-cycle commitment is mind-boggling to me in this age of rapid technology turnover! And they were not even the first

to do so; IOxOS also has an FPGA-based bridge chip that is sold as a stand-alone component and is being used by other VMEbus board suppliers. In 2014 the industry was in a panic that VMEbus as we knew it would end when IBM informed IDT that they would no longer build the Tsi148 VMEbus to PCI-X bridge for them, forcing IDT to announce the end-of-life of that popular part. Strong demand for VME incentivized suppliers to look for alternate solutions, from lifetime purchases to custom FPGA implementations. Many are taking the opportunity to make it a VMEbus to PCI Express bus bridge, which is more popular with today’s designs. The industry lost a giant in January with the passing of Lym Hevle, the founder of the VMEbus International Trade Association (VITA). I was saddened to hear the news. I had the fortune of knowing Lym in the early days of VITA and VMEbus. My last contact with him was while I was doing research for the 25th anniversary of VMEbus. Read more about Lym’s contributions in the Hall of Fame feature. I was excited when I got a call from NAVAIR late last year asking if they could attend a VITA Standards Organization (VSO) meeting to discuss some ideas they had on open architecture platforms. They have been following the work of the U.S. Army’s VICTORY program and have been struggling with many of the same development issues. A NAVAIR representative presented the Hardware Open System Technology (HOST) strategy to VSO meeting attendees. NAVAIR has a vision of creating a hardware technical reference framework for developing embedded computing systems through successful development of the HOST strategy to maximize platform and system “openness,” modularity, interoperability, scalability, sustainability, and reuse. The VSO decided to form a study group to continue working on this proposal. Formal release of a document is imminent. Growing a company in the critical embedded computing industry is extremely challenging. I spent several years of my career at Motorola leading a small strategy team tasked with that goal. I am always on the watch for news on acquisitions in our industry. The recent announcement by Mercury Systems to acquire the embedded security, RF and microwave, and custom microelectronics businesses from Microsemi Corporation was especially of interest. Mercury Systems has been active in acquisitions for many years, primarily at a system level. This acquisition takes a different slant that I am not quite sure I understand yet. While I have observed semiconductor companies purchase board and system companies over the years, I have never seen a computer system company in this space purchase a semiconductor company. This will be a fun acquisition to follow in the coming months. It begs me to ask why someone wouldn’t be interested in purchasing the IDT VME chip business? I extend an invitation for everyone to join in the conversations at the VITA Technologies LinkedIn group (www.linkedin.com/groups/2565867). If the rest of 2016 is anything like the first quarter, then this year should be a fun time! I look forward to a great 2016. Jerry Gipper, jgipper@opensystemsmedia.com

6 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


VITA Standards Update By Jerry Gipper jgipper@opensystemsmedia.com

VITA Standards Organization activity updates The March VITA Standards Organization (VSO) meeting was held in Orlando, Florida. This update is based on the results of that meeting. Contact VITA if you are interested in participating in any of these working groups. Visit the VITA website (www.vita.com) for details on upcoming VSO meetings.

ANSI accreditation Accredited as an American National Standards Institute (ANSI) developer and a submitter of Industry Trade Agreements to the IEC, the VSO provides its members with the ability to develop and promote open technology standards. The VSO meets every two months to address embedded bus and board industry standards issues.

VSO study and working group activities Standards within the VSO may be initiated through the formation of a study group and developed by a working group. A study group requires the sponsorship of one VITA member, and a working group requires sponsorship of at least three VITA members.

Status: ANSI/VITA 47-2005 (R2007) has been opened up for revision to improve interoperability, create less reliance on individual supplier ruggedization guidelines, and make sure environments are concurrent with new VPX updates. The working group is actively scheduling meetings and working on revisions. Participation is encouraged.

VITA 48.4: VPX REDI: Mechanical Specification Using Liquid Flow Through (LFT) Applied to VPX Objective: This standard will establish the mechanical design requirements for an LFT-cooled electronic VPX module. Status: The working group is developing a vibration test plan, as well as designing a simplified prototype vibration test module and backplane fixture to further validate the concept of removing the two outer guide pins. A first draft version of the standard is out for review to establish the content structure, with details filling in as the design solidifies. The goal is to have testing complete and a draft standard ready for review by the end of the year.

VITA 48.8: VPX REDI: Mechanical Standard for 3U, 6U Air Flow Through (AFT) Cooling

Work in progress

Objective: This standard will develop an AFT standard using VPX connectors without need for retainers and uses jackscrews instead of levers.

Several working groups have current project work underway; the following roundup summarizes those projects.

Status: The first draft of the standard is under review by the working group. Interested parties are invited to join the effort.

VITA 49.2: VITA Radio Transport (VRT) Control Packet Rules ANSI/VITA 42.0: XMC Switched Mezzanine Card Base Specification Objective: This standard defines a PMC form factor with open-standard switch fabric interconnects. Status: The draft specification has completed the ANSI balloting phase, and comments received during the ballot are under review.

ANSI/VITA 47: Environments, Design and Construction, Safety, and Quality for Plug-in Units Objective: Supplying vendors’ certification of COTS plug-in units to this standard will facilitate the cost-effective integration of these items in larger systems.

Objective: The VRT standard defines a transport-layer protocol designed to promote interoperability between radio frequency receivers and signal processing equipment in a wide range of applications. The VRT protocol provides a variety of formatting options allowing the transport layer to be optimized for each application. The VITA 49.2 standard specifies the rules governing control packets. Status: The working group has developed a draft document for review and discussion. Interested parties are invited to join the working group.

VITA 57.4: FMC+ Objective: The goal of this project is to develop a next-generation specification calling for a new set of connectors to support higher-speed serial interfaces. Status: The working group ballot has passed, and comments are under review before the document will be submitted to ANSI ballot.

ANSI/VITA 65: OpenVPX Architectural Framework for VPX Objective: The OpenVPX architectural framework specification is a living document that is continuously being updated with new profile information and corrections.

8 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


Status: The working group is reviewing clocking, keying, and nomenclature proposals for the next release.

VITA 66: Optical Interconnect on VPX – Half Width MT Objective: The VITA 66 base standard defines physical features of a standalone compliant blind mate optical interconnect for use in VPX systems. This standard defines a half width MT style contact variant. Status: VITA 66.4 has completed the ANSI public review ballot. The working group is reviewing comments.

VITA 67.3: VPX: Coaxial Interconnect, 6U, Four Position SMPM Configuration Objective: This specification details the configuration and interconnect within the structure of VITA 67.0, enabling a 6U VPX interface containing multi-position blind mate analog connectors with up to four SMPM contacts. Status: The working group has completed working group balloting and is addressing the open comments.

VITA 68: VPX: Compliance Channel Objective: This standard defines a VPX compliance channel including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates. This allows backplane developers to design a backplane that supports required Bit Error Rates (BER) for multiple fabric types. This also allows module developers to design plug-in modules that are interoperable with other modules when used with a compliant backplane. Status: The working group has approved moving the specification to “VITA Draft Standard for Trial Use” status. Specifications are available for download by VITA members and are posted at the VITA Store for purchase by the general public.

VITA 74: VNX Objective: VNX describes a rugged small form factor subsystem intended to be rugged for deployed environments. Status: The working group has started several activities to complete the work www.vita-technologies.com

necessary to take this specification to ANSI accredited status. Several additional dot specifications have been introduced to expand the capability of VNX. Interested parties are invited to join the working group.

VITA 76: High Performance Cable – Ruggedized 10 Gbaud Bulkhead Connector for Cu and AOC Cables Objective: Describe the copper interface of a new generation of ruggedized circular connectors with a MIL-DTL-38999L series III shell. Status: ANSI/VITA 76.0-2016 High Performance Cable – Ruggedized 10 Gbaud Bulkhead Connector for Cu and AOC Cables has been ratified by ANSI. The standard is available for download by VITA members and is posted at the VITA Store for purchase by the general public.

Build your own VPX system ! INTERFACE CONCEPT product range of Single Board Computers, FPGA boards, ADC/ DAC FMC and Graphic boards are ideal to devise a complete VPX system for compute intensive and image processing applications (radar, electronic warfare, electro optical and IR, visualization systems)

Intel® CoreTM i7 SBC

VITA 78.1: SpaceVPX Lite Systems Objective: This document leverages the work done on ANSI/VITA 78 to create a specification with an emphasis on 3U module implementations. The most significant change from SpaceVPX is to shift the distribution of utility signals from the SpaceUM to the System Controller to allow a radial distribution of supply power to up to eight payload modules.

• Two Cor CoreTM i7 Processors (Dual / Quad Core) • One Ethernet switch, XMC slot... • One KintexTM 7 FPGA & FMC site

Virtex®-7 FPGA Boards

Status: The working group has developed a draft document of the specification.

VITA 84: Hardware Open System Technology (HOST) Study Group Objective: This is a newly formed study group with the vision of creating a hardware technical reference framework for developing embedded computing systems through successful development of an overarching HOST strategy to maximize platform and system “openness,” modularity, interoperability, scalability, sustainability, and reuse. Status: The study group was kicked off in February by NAVAIR. The first public release of HOST draft specification is awaiting approval. Copies of all standards reaching ANSI recognition are available from the VITA website. For a more complete list of VITA standards and their status, go to www.vita.com/Standards.

• Two Virtex®-7 690T & FMC sites • One FreescaleTM QorIQ T1042 (or T2081)

Graphic Boards

• One AMD RadeonTM E8860 • One KintexTM-7 325T FPGA • Support for DP, HDMI, VGA, Stanag3350, Arinc8181... • One PMC/XMC site

www.interfaceconcept.com +33 (0)2 98 57 30 30

VITA Technologies Resource Guide Spring/Summer 2016 |

9


MAIN FEATURE

FMC+ standard propels embedded design to new heights By Jeremy Banks and Jim Everett

The updated FPGA Mezzanine Card (FMC+) specification has been developed and refined over the past year, promising unparalleled I/O density and backward compatibility. The VITA 57.4 working group has approved the spec and will present it for ANSI balloting in early 2016. The following article takes a closer look at this important new standard to see its implications for advanced embedded design. A new mezzanine card standard called FMC+, an important development for embedded computing designs using FPGAs and high-speed I/O, will extend the total number of gigabit transceivers (GTs) in a card from 10 to 32 and increase the maximum data rate from 10 Gbps to 28 Gbps while maintaining backward compatibility with the current FMC standard. These capabilities mesh nicely with new devices such as those using the JESD204B serial interface standard, as well as 10G and 40G fiber optics and high-speed serial memory. FMC+ addresses the most challenging I/O requirements, offering developers the best of two worlds: the flexibility of a mezzanine card with the I/O density of a monolithic design.

The mezzanine card advantage Mezzanine cards are an effective and widely used way to add specialized functions to an embedded system. Because they attach to a base or carrier card, rather than plugging directly into a backplane,

mezzanine cards can be easily changed. For system designers, this means both configuration flexibility and an easier path to technology upgrades. However, this flexibility usually comes at the cost of functionality due to either connectivity issues or the extra real estate needed to fit on the board. For FPGAs, the primary open standard is ANSI/VITA 57.1, otherwise known as the FPGA Mezzanine Card (FMC) standard. A new version dubbed FMC+ (or, more formally, VITA 57.4) extends the capabilities of the current FMC standard with a major enhancement to gigabit serial interface functionality. FMC+ addresses many of the drawbacks of mezzanine-based I/O compared to monolithic solutions, simultaneously delivering both flexibility and performance. At the same time, the FMC+ standard stays true to the FMC history and its installed base by supporting backward compatibility. The FMC standard defines a small-format mezzanine card, similar in width and height to the long-established XMCs or PMCs, but about half the length. This means FMCs have less component real estate than open-standard formats. However, FMCs do not need bus interfaces such as PCI-X, which often take up a considerable amount of board real estate. Instead, FMCs have direct I/O to the host FPGA, with simplified power supply requirements. This means that despite their size, FMCs could have more I/O capacity than their XMC counterparts. As with the PMC and XMC specifications, FMC and FMC+ define options for both air and conduction cooling, thereby serving both benign and rugged applications in commercial and defense markets. The anatomy of the FMC specification is simple. The standard allows for up to 160 single-ended or 80 differential parallel I/O signals for high-pin-count (HPC) designs or half that number for low-pin-count (LPC) variants. Up to 10 full-duplex

10 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


GT connections are specified. The GTs are useful for fiber optics or other serial interfaces. In addition, the FMC specification defines key clock signals. All of this I/O is optional, though most hosts now support the full connectivity.

Parallel interface 2x 2 GSps ADC

JESD204B Serial 2x 2 GSps ADC

10 mm x 10 mm

The FMC standard also defines a mix of power inputs, though the host supplies the primary power supply as defined by the mezzanine. This approach works by partially powering up the mezzanine such that the host can interrogate the FMC, which responds by defining a voltage range for the VADJ. Assuming the host can provide this range, then all should be well. Not having the primary regulation on the mezzanine saves space and reduces mezzanine power dissipation.

27 mm x 27 mm

Figure 1 | Effect of package shrink on FMC through JESD204B

50 Gbps throughput range. This functionality results from a trade-off between physical package sizes and available connectivity to the host FPGA. In addition to the parallel connections, the FMC specification supports up to 10 fullduplex high-speed serial (GT) links. These interfaces are useful for such functionality as fiber-optic I/O, Ethernet, emerging technologies like Hybrid Memory Cube (HMC) and MoSys’ Bandwidth Engine, and newer-generation analog I/O devices that use the JESD204B interface.

FMCs for analog I/O Designers can use FMCs for any function that you might want to connect to an FPGA, such as digital I/O, fiber optics, control interfaces, memory, or additional processing. But analog I/O is the most common use for FMC technology. The FMC specification affords a great deal of scope for fast, high-resolution I/O, but there are still trade-offs, especially with high-speed parts using parallel interfaces. For example, Texas Instruments’ ADC12D2000RF dual-channel, 2 GSps 12-bit analog-to-digital converters (ADCs) use a 1:4 multiplexed bus interface, so the bus speed is not too fast for the host FPGA. The digital data interface alone requires 96 signals (48 LVDS pairs). For a device of this class, FMC can support only one of these ADCs, even if there is sufficient space for more, because it is limited to 160 signals. Lower-resolution devices, even at higher speeds such as those with 8-bit data paths, can allow more channels even with the increased requirements of the front-end analog coupling of the baluns or amplifiers, clocking, and the like. The FMC specification starts to run out of steam with analog interfaces delivering more than 8 bits of resolution at around 5 GSps or 6 GSps (throughputs of > 50 Gbps) using parallel interfaces. From a market perspective, leading FMCs based on channel density, speed, and resolution are in the 25 Gbps to www.vita-technologies.com

Enter JESD204B Although the JESD204 serial interface standard, currently at revision “B,” has been around for a while, only recently has it has gained wider market penetration and become the serial interface of choice for newer generations of high-sampling data converters. This wide adoption has been stoked by the telecommunications industry’s thirst for ever-smaller, lower-power, and lower-cost devices. As mentioned earlier, a dual-channel 2 GSps, 12-bit ADC with a parallel interface requires a large number of I/O signals. This requirement directly impacts the package size, in this case mandating a 292-pin package measuring roughly 27 mm x 27 mm (though newer-generation pin geometry could shrink the package size to something less than 20 mm x 20 mm). A JESD204B-connected equivalent device can be provided in a 68-pin, 10 mm x 10 mm package with reduced power. This dramatic reduction in package size marries well with evolving FPGAs, which are providing more GT links at higher and higher speeds. Figure 1 illustrates an example of package size and FMC/FMC+ board size. Typical high-speed ADCs and digital-to-analog converters (DACs) using the JESD204B interface have between one and eight GT links operating at 3 Gbps to 12 Gbps each, depending on the data throughput required based on sample rate, resolution, and number of analog I/O channels. The FMC specification defines a relatively small mezzanine card, but with the emergence of JESD204B devices, there is room to fit more parts onto the available real estate. The maximum of 10 GT links defined by the FMC specification is a useful quantity; even this limited number of GT links provides 80 Gbps or more of throughput while using a fraction of the pins otherwise required for parallel I/O. The emergence of serially connected I/O devices, not just those using JESD204B, does have drawbacks for some application segments in electronic warfare, such as digital radio frequency memory (DRFM). Serial interfaces invariably introduce additional latency due to longer data pipelines. For DRFM applications, latency for data-in to data-out is a fundamental performance parameter. Although latency is likely to vary widely between serially connected devices, new generations of devices will push data through the pipelines faster and faster, with some promising the ability to tune the depth of the pipeline. It remains to be seen how much of an improvement is to be realized. VITA Technologies Resource Guide Spring/Summer 2016 |

11


MAIN FEATURE Some standard ADC devices sampling at > 1 GSps today have latency below 100 nanoseconds. Other applications can tolerate this latency or do not care about it, including software-defined radio (SDR), radar warning receivers, and other signals intelligence (SIGINT) segments. These applications gain large advantages by using a new generation of RF ADCs and DACs, a technology driven by the mass-market telecommunications infrastructure.

a separate connector, referred to as an HSPCe (HSPC being the main connector). Table 1 summarizes FMC and FMC+ connectivity. Multiple independent signal integrity teams characterized and validated the higher 28 Gbps data rate. The maximum full-duplex throughput can now exceed 900 Gbps in each direction when the parallel interface is included. See Figure 2 for an outline of the net throughputs that can be expected for digitizer solutions supporting the different capabilities of FMC and FMC+. Designers can use the increased throughput enabled by FMC+ to take advantage of new devices that offer huge I/O bandwidth. There will still be trade-offs, such as how many devices can fit on the mezzanine’s real estate budget, but for a moderate number of channels, the realizable throughput is a huge leap over today’s FMC specification.

Outside the FPGA community, newer DSP devices are also starting to adopt JESD204B. However, FPGAs are likely to remain the stronghold in taking full advantage of the capabilities of wideband analog I/O devices. That’s because FPGAs can deal with vast data volumes with better parallelization.

Next-generation ADCs and DACs In the next few years, it is reasonable to expect high-resolution ADCs and DACs to break through the 10 GSps barrier to support very wideband communications with direct RF samplings for L-, S-, and even C-band frequencies. Below 10 GSps, converters are emerging with 12-, 14-, and even 16-bit resolutions, with some supporting multiple channels. The majority of these devices will be using JESD204B (or a newer revision) signaling with 12 Gbps channels until newer generations inevitably boost this speed even further. These fast-moving advances are fueled by the telecommunications industry, but the military community can take advantage of them to meet size, weight, power, and cost (SWAP-C) requirements.

The evolution of FMC+ To move FMC to the next level, the VITA 57.4 working group has created a specification with an increased number of GT links operating at increased speed. FMC+ maintains full FMC backward compatibility by adding to the FMC connector’s outer columns for the additional signals and not changing any of the board profiles or mechanics.

6

4

The additional rows will be part of an enhanced connector that will minimize any impact on available real estate. The FMC+ specification increases the maximum number of available GT links from 10 to 24, with the option of adding another eight links, for a total of 32 full duplex. The additional links use Function

Connector-limited

Channels

8

2 2

4

6

8

10

12

14

16

18

20

Sample rate per channel (GSps)

22

24

Figure 2 | FMC versus FMC+ digitizer throughput capability

FMC

FMC+

FMC+ with HSPCe extension

80 diff/160 single-ended

80 diff/160 single-ended

80 diff/160 single-ended

Clocks

4

4

4

Maximum # GTs

10

24

32

GT clocks

2

6

8

Miscellaneous

JTAG, SYNC, power good, geographic address

JTAG, SYNC, power good, geographic address

JTAG, SYNC, power good, geographic address

Power supplies

VADJ* (4 pins), 3 V3 (4 pins), 12 V (2 pins), 3 V3 Aux (1 pin)

VADJ* (4 pins), 3 V3 (8 pins), 12 V (4 pins), 3 V3 Aux (1 pin)

VADJ* (4 pins), 3 V3 (8 pins), 12 V (4 pins), 3 V3 Aux (1 pin)

Maximum # parallel I/O

* VADJ: mezzanine defined for voltage level, but provided by host

Table 1 | Summary of FMC and FMC+ connectivity

12 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


is likely where the higher speeds supported by FMC+ will first be realized. Bandwidths of 28 Gbps per fiber will take the throughputs quickly past 100G and 400G speeds on a single mezzanine. Optical throughput of 100G is emerging today on the current FMC format.

Figure 3 | Xilinx KCU114

Other advantages and uses of FMC+ Although FMC+, like FMC, will probably be dominated by ADC, DAC, and transceiver products, the increased GT density provided by FPGAs makes it useful for other functions. Two functions of note are fiber optics and new serial memories. As with JESD204B, there are requirements for faster, denser fiber optics. Those based on fiber-optic ribbon cables offer the smallest parts. Because the FMC+ footprint readily supports 24 fullduplex fiber-optic links, this application

Another emerging area suitable for FMC+ is serial memory such as HMC and Bandwidth Engine. These novel devices represent an entirely new category of high-performance memory, delivering unprecedented system performance and bandwidth by utilizing GT connectivity.

Alive and kicking A new generation of the FMC specification has been introduced and is adapting to new technology driven by serial connected devices. Key players in the FMC industry have already begun adopting this specification. Figure 3 shows the first Xilinx demonstration board featuring FMC+, the KCU114. The FMC standard, through its new incarnation FMC+, is alive and kicking and is prepared for the next generation of high-performance, FPGA-driven applications.

Jeremy Banks is a product manager for sensor and I/O processing at Curtiss-Wright. He has been involved in the defense embedded computing industry for more than 25 years holding positions in engineering design, marketing, and product management across DSP, multiprocessing, RF I/O, SBC, and FPGA disciplines. Jeremy holds a BSc (Hons) in Electronic and Electrical Engineering from the University of Surrey. He can be reached at Jeremy.banks@curtisswright.com. Jim Everett is product marketing manager for Virtex evaluation, GT characterization, and FMC/FMC+ boards and kits at Xilinx. His 35-year career in electronics spans many years in design, sales, and marketing of FPGAs. Jim graduated from Michigan State University with a BSEE degree. He can be reached at jeverett@xilinx.com.

Curtiss-Wright www.curtisswright.com Xilinx www.xilinx.com

Rugged Chassis, Backplanes, and Integrated Systems Engineered for Your Application Standards-based and Highly Customizable Whether you have a back-of-the-envelope design idea and seek collaborative development with our engineering team, or provide us with a complete set of build specifications, LCR Embedded Systems will turn your product into reality.

VPX • AdvancedTCA • VME • CompactPCI • Custom (800) 747-5972 • sales@lcrembedded.com • www.lcrembeddedsystems.com www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

13


TECHNOLOGY FEATURE

Very high-speed sampling and serial ADCs in embedded systems By Thierry Wastiaux

Latest-generation active electronically scaled array (AESA) radar systems can have thousands of TX/RX modules. High bandwidth is needed to connect each array element data converter to the FPGAs that process incoming and generate outgoing data streams. New software-defined radio systems use advanced reconfigurable modulation schemes that increase channel bandwidths and deliver unprecedented wireless data rates. To increase the performance of software radio and electronic warfare systems, it has become critical to use efficient, low-power, low-pin-count, FPGA-connected converter interfaces. As the performances of analog-to-digital converters (ADCs) are quickly improving, the classical approach of transmitting samples through low-voltage differential signaling (LVDS) reaches its limits. LVDS lanes connected to last-generation FPGA I/O are limited to around 1.4 Gbps. As an example, when targeting a four-channel FPGA Mezzanine Card (FMC) with 12-bit analog to digital sampling at 2.6 GSps, a minimum of 96 LVDS lanes is required for data only, without taking into account the clock and service signals. This is not possible on standard VITA 57.1 connectors, and it takes too much I/O resource on the FPGA. The insatiable demand for data sampling thus has led to the need for the standardization body JEDEC to introduce the JESD204 standard for a high-speed serial link between data converters and logic devices. Serial link data rates have been pushed up to 12.5 Gbps in the last revision “B” of the standard, released in 2011 for higher-bandwidth requirements. This revision also includes provisions for “deterministic latency” of data transfers.

Simplification of design Compared to the classical parallel approach, the improvements brought by JESD204 are many. By moving from highpin-count, low-speed to low-pin-count, high-speed serial interface, the overall system design is simplified with a smaller

number of trace routes and easierto-route board designs. The links use 8b/10b encoding, which incorporates an embedded clock, enabling further pin-count reduction by removing the necessity for routing an additional clock line and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates. In addition, trace-to-trace tolerances are relaxed relative to synchronous sampling parallel LVDS signals. All these simplifications in the design eventually lead to cost reduction. Moreover, this allows reducing the size of the ADC components, as the output pins required for FPGA connection are less numerous using the low differential swing DC-balanced high-speed current mode logic (CML) standard. Thus, it can further increase the number of components on the small FMC footprint. It must be noted that the last generation of serial ADCs implements digital downconverters with variable decimation ratios that provide filtering and reduce the output data rate. They might include frequency translation stages (numerical controlled oscillators), finite impulse response (FIR) filtering stages, gain stages, and complex-to-real conversion stages. Numerically controlled oscillators (NCOs) and digital mixers allow tuning the center of the bandwidth of interest

14 | VITA Technologies Resource Guide Spring/Summer 2016

to baseband. The filtering stages allow filtering the unwanted part of the spectrum. Gain stages allow compensating for mixer and NCO losses. And complex-toreal conversion enables presenting the final real signal of interest. These down-converter features dramatically reduce the complexity of radio and radar systems, using part of the FPGA resources to implement these functions. The FPGA capacity is fully used for the important signal processing part as beamforming for radars, for instance.

Deterministic latency It is important to know the timing relationship between the sampled signal and its digital representation. This timing relationship is affected by the latency of the converter, which is defined for an ADC as the number of clock cycles between the instant of the sampling edge of the input signal until the time that its digital representation is present at the converter’s outputs. This latency is typically in the range of several nanoseconds in classical parallel ADCs. In JESD204B, this latency is increased by the process of serialization even if the speed of the sampling data transmission lanes is much higher. This latency can typically be several tens of nanoseconds. JESD204B-compliant receivers are outfitted with an elastic buffer that is used www.vita-technologies.com


to compensate for skew across serializer/ deserializer (SERDES) lanes, which simplifies board layout. This elastic buffer stores the data until the data from the slowest lane arrives. It then releases the data from all lanes simultaneously for digital processing. This skew management is possible because the data clock is embedded in the serial data stream. While the JESD204B standard has simplified multichannel synchronization by using deterministic latency, minimal latency is needed in some applications such as electronic warfare (EW) and radar applications where actions are required immediately after detection. For these applications, the LVDS interface should still be considered, as the JESD204Bcompliant data converter’s delay in serializing the data is omitted. However, applications such as radar warning receivers (RWR) or COMINT that are receiver-only applications tolerate the latency brought on by the JESD204B serialization. These applications thus can benefit from the last generations of ADCs driven by the mass market of telecommunication infrastructure, allowing very high-speed sampling and reducing the complexity of the analog part of the system.

The FMC standard defines a small format mezzanine, similar in width and height to XMCs or PMCs, but around half the length. As real estate is limited, some features have been included in the standard. First, to save space, its primary power is supplied by the FPGA carrier board. During the power-up sequence, the host interrogates the FMC as to what the feeding voltage must be. In addition, FMCs directly connect the I/O devices on the mezzanine to the host FPGA via a high-speed, highdensity connector as if the device was on the host itself, leading to logic reduction and saved space. The first generation of the FMC standard allows up to 160 for high-pin-count (HPC) or 80 for low-pin-count (LPC) “parallel” I/O signals and up to 10 full-duplex highspeed serial connections (along with some clocks). Figures 1 and 2 shown on page 16 depict an Interface Concept ADC FMC, the IC-ADC-FMC, which can be plugged on a Virtex-7 FPGA carrier board, the IC-FEP-VPX3c, featuring eight high-speed transceivers in front of the mezzanine’s high-speed serial (HSS) links.

FPGA vendors have developed fully compliant JESD204B intellectual property (IP) that can be implemented in their products for communication with the serial ADCs. For example, the JESD204B Xilinx IP supports 256 bytes per frame and 32 frames per multiframe. It can be configured to support up to 32 lanes.

Flexible design follows the fast moving market of ADCs In combining the technologies available on ADCs including the new JESD204B standard and FPGAs, EW system architects can dramatically improve data sample processing. FMC (VITA 57 standard), promoted by the VITA FMC Marketing Alliance, allows high data throughput and very low latency response between an ADC or a digital-to-analog converter (DAC) FMC and the FPGA, simplification of the design, and above all, the cost-efficient ability to simply retarget an FPGA carrier card design. All that is required is swapping out the FMC module and adjusting the FPGA firmware. That is why the standard has become the open standard mezzanine of choice. www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

15


TECHNOLOGY FEATURE At the inception of the FMC standard, the HPC specification appeared as satisfactory in terms of the number of allowed I/O. The evolution of ADC technology, as well as the increasingly demanding requirements of EW system designers, has highlighted the need to go beyond this first version of the FMC standard. An effort to define suitable FMC enhancements is now underway within the VITA 57.4 working group. The focus is on creating a standard with an increased number of HSS links (increased from 10 to 24) operating at increased speed while keeping the existing connector pinout for I/O. The HSS link throughput is targeted at up to 28 Gbps, extending the aggregate bandwidth to the huge level of 672 Gbps, to which the traditional LVDS links can be added. Backward compatibility is ensured by adding to the FMC connector’s outer columns for additional signals without changing the form factor, real estate, or mechanics (mounting holes, thermal interface, and so on). The approval of this new standard is currently in process.

Layer 2/3 Enterprise Non-Blocking GigE Smart Switch for Demanding SWAP-C Environments TM

NANOSWITCH

The Themis NanoSWITCH is a Size, Weight, Power and Cost (SWAP-C) optimized rugged multi-layer Gigabit Ethernet switch with an embedded x86 PC. NanoSWITCH brings enterprise level layer 2/3 switching into demanding environments found in military ground, air and sea vehicles.

Applications • Vehicle network switching • Distributed architecture vehicle controller • VICTORY compliant switch, router, timing, and control • Shared processing and peripheral communications

Environmental • IP67 environmentally sealed for water, dust, and salt fog) • Sealed MIL connectors • Operating temperature: -40°C to 71°C • Shock: 50g @25ms • Vibration: 5G RMS.10Hz to 2KHz • Status LED blanking control

ww w.t h e mis.c om/ n a n oswit ch

47200 Bayside Parkway, Fremont CA 94538 | 510-252-0870 | www.themis.com ©2016 Themis Computer. All rights reserved. Themis and the Themis logo are trademarks or registered trademarks of Themis Computer. All other trademarks are the property of their respective owners.

16 | VITA Technologies Resource Guide Spring/Summer 2016

Figure 1 | IC-ADC-FMCc quad 12-bit 1300 MSPS FMC

Figure 2 | IC-FEP-VPX3c Virtex-7 carrier with one VITA 57.1 FMC slot

The future of converter digital interfaces The industry is requiring better performing ADCs, leading to huge sample data flows. The big push of the ADC industry has led to the development of the JESD204B standard. Looking to the future, it is clear that JESD204 is poised to become the industry choice for the digital interface to converters. Each revision has answered the demands for improvements on its implementation and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performances increase, the JESD204 standard should be able to adapt to meet the new design requirements necessary. Thierry Wastiaux is senior VP of sales for Interface Concept. He has 25 years of experience in the telecom and embedded systems market. Prior to joining Interface Concept, he was responsible for the operations of the Mobile Communication Group and the Wireless Transmission Business Unit at Alcatel-Lucent. He holds an MSc from Ecole Polytechnique France.

Interface Concept twastiaux@interfaceconcept.com www.interfaceconcept.com www.vita-technologies.com


TECHNOLOGY FEATURE

Modular Open Radio Frequency Architecture boot camp By Jerry Gipper Designers creating the next generation of embedded defense systems face several challenges getting their solutions off the ground. The newly launched Modular Open Radio Frequency Architecture (MORA) aims to enable the development of true open standards-based radio frequency and microwave modules and small form factor subsystem designs to reduce costs, foster commonality, and enable new communications capabilities. Electronics are a key part of many defense platforms and are becoming more important as the content percentage is growing. However, the purchasing influence of defense programs has become a smaller percentage of the overall worldwide electronics industry. Complicating the issue is the demand to get new solutions to deployment in much shorter time frames to take advantage of the latest technology. This increase in reliance on electronics, reduction in purchasing power, and rapid shortening of time to deployment have created a challenging dynamic for system architects responsible for the design of next-generation defense platforms.

performance and efficiency through reduced cable loss. Use of software-defined radio technologies allows the same hardware to run different waveform application to support a multitude of missions, including EW and communications.

Over the years, many initiatives have emerged to drive standards for open, flexible platforms, with the most recent example being the U.S. Army’s VICTORY program. Recently, the U.S. Army’s Communications-Electronics Research, Development, and Engineering Center (CERDEC) launched a new initiative, the Modular Open Radio Frequency Architecture (MORA), which will enable the development of true open standards-based RF and microwave modules and small form factor subsystem designs that address the size, weight, and power consumption (SWaP) constraints of today’s ground vehicles. MORA is intended to leverage the work done under the VICTORY initiative by adding consideration for RF modules and subsystems.

› Enable sharing of hardware and software components among C4ISR/EW capabilities. › Allow technology refresh to keep pace with threats while improving reliability and robustness. › Support current and future interoperability requirements and facilitate transition planning. › Permit capabilities that are innovative but unplanned to be rapidly implemented for “future-proofing.” › Reduce developmental and acquisition costs through greater commercial competition.

CERDEC is defining a converged open architecture that will provide open interfaces to enable rapid insertion of new capabilities, interoperability, and a reduced SWaP footprint. The MORA architecture, which extends the U.S. Army’s VICTORY architecture, will:

About the MORA architecture

Wide embedded industry support of the modular and scalable MORA architecture will help drive the network-based connectivity of sensors and peripherals on ground vehicles and help speed the deployment of new C4ISR/EW capabilities.

Current command, control, communications, computers, intelligence, surveillance, and reconnaissance (C4ISR) and electronic warfare (EW) systems use single-purpose hardware and software that aren’t shared beyond their defined functions and compete for limited resources on the platform. MORA decomposes radio systems into high-level components that enable sharing of hardware such as amplifiers and antennas. Low power distribution of RF signals improves overall system

MORA is based on the popular OpenVPX module and backplane open-standard framework managed by VITA members. MORA-based hardware and software solutions developed by VITA member companies will enable enhanced C4ISR/EW capabilities to exist within the SWaP constraints of platforms and provide subsystem commonality across the vehicle fleet to reduce life-cycle costs.

www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

17


TECHNOLOGY FEATURE “One thing we know about the future is that we don’t know what the future holds,” said Ben Peddicord, chief of CERDEC Intelligence and Information Warfare Directorate’s Intel Technology and Architecture Branch. “The interfaces that have been exposed to MORA were chosen based on an analysis of the capabilities we’ve wanted to field over the past 15 years.”

to define common standards, a clear picture of which interfaces are desired must be established across the board.

Compared to a traditional radio solution, MORA provides the system integrator with greater flexibility when addressing technical challenges and the ability to insert third-party capabilities.

“We’ve never been able to tell industry partners exactly what we want because we never understood standards well enough to steer their efforts toward our benefit,” Peddicord said. “Now we have built up enough expertise to actively contribute to standards.” Peddicord presented on overview of MORA to the audience at Embedded Tech Trends 2015 (www.embeddedtechtrends.com). Figure 1 illustrates how MORA extends the VICTORY architecture.

According to Peddicord, nearly all military platforms – to include soldiers – have RF devices on them, making MORA an important element of hardware and software convergence because of its ability to share hardware assets across the platform. “It’s hard to get meaningful improvements, flexibility, and SWaP reduction if you don’t include RF components,” Peddicord said.

MORA payoffs include hardware reuse and pooling, rapid third-party technology insertion, reduced dependence on proprietary hardware and software, and the ability to improve compatibility and/or interoperability. The real catch, however, has been ensuring that industry would build to MORA standards, said Peddicord.

With a continued emphasis on open systems architecture, CERDEC became a sponsor member of VITA, an international non-profit organization that has championed open system architectures since 1982.

“Without industry support, it won’t work. If government programs ask for it, then industry will support, but government is cautious to put out requirements for a standard not supported by industry,” he said.

Using common standards ultimately saves money and time, both of which are key components from the Better Buying Power 3.0 initiative, Peddicord said. The challenge, however, is that in order

To define these standards, CERDEC has worked closely with industry through VITA, conferences, and third-party vendors, as well as collaborated with companies that build according to

19”DESKTOP CASES

INTEGRATED SYSTEMS

CARD CAGES AND COMPONENTS

BACKPLANES AND EXTENDERS

19” RACK CASES PLUGGABLE POWER SUPPLIES

THERMAL SOLUTIONS

18 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


MORA specifications. CERDEC is being assisted by MIT Lincoln Laboratory, Georgia Tech Research Institute, Johns Hopkins University Applied Physics Laboratory, and other strategic research partners that are familiar with OpenVPX.

Radioheads (Antenna + PA)

VICTORY Shared Processing Unit

VICTORY Data Bus (GbE)

“It’s important to have a third party build against the spec because it always makes sense to the person who wrote it, so it’s important that someone who didn’t write it builds it to ensure it’s working,” Peddicord said. “We believe that MORA provides a path for using true industry open standards to develop rugged COTS solutions to meet [defense] critical requirements,” said Lynn Bamford, senior VP and general manager of the Defense Solutions Division at Curtiss-Wright. Several other VPX technology suppliers stand ready to develop products in support of MORA.

The future of RF distribution The ANSI/VITA 49 VITA Radio Transport (VRT) standard defines a transport-layer protocol designed to promote interoperability between RF receivers and signal processing equipment in a wide range of applications. The VRT protocol provides a variety of formatting options allowing the transport layer to be optimized for each application. CERDEC is also evaluating VITA 49 as an alternate form of RF distribution within MORA. VRT potentially eliminates the need for an RF distribution device and RF cables, minimizes power loss due to coaxial

www.vita-technologies.com

MORA High-Speed Bus Power Bus RF Cables

Software-Defined Radio

RF Distribution Device

Figure 1 | VICTORY/MORA relationship

cables, improves resistance to EMI, and simplifies cabling in chassis and platforms, all key advantages to MORA. Work continues on investigating the performance of VITA 49. Toward the end of 2016, CERDEC is planning a vehicle demonstration of hardware/software convergence using MORA. Specifications for MORA can only be released to U.S. government agencies and their contractors. The current version of the specification is available through the VICTORY portal at http://victory-standards.org.

VITA Technologies Resource Guide Spring/Summer 2016 |

19


SPECIAL FEATURE

VITA Technology Hall of Fame 2016 Lyman Hevle was the founding executive director of the VMEbus International Trade Association (VITA). He held that role from its inception in 1984 until 1993. During his career Lym was focused on the business and market growth of VMEbus. He passed away in January 2016, and his legacy will live on in the industry. Lym’s own words best describe his involvement with VMEbus and how he came to be the founding executive director of VITA. The following discourse is an excerpt from his autobiography.

Genesis and development of VMEbus From Lym Hevle’s autobiography Like any successful human endeavor, there are many who claim fatherhood. There were actually many true and some untrue claimants. Some of these came aboard the VMEbus train several years after it had left the station. They did, however, fulfill a valuable role as VMEbus pioneers. The actual birth of VMEbus was painful, though exciting. I will relate my role as accurately as I can, with no purpose of denigrating anyone else’s memory or participation. It starts with the [Motorola] 6800 microprocessor and the Exercisor. In those days every manufacturer designed their own non-standard boards and guarded them zealously. The engineers who established the Exercisor board parameters did a good job with a fairly small board. When we started Microsystems, we inherited this head start. We immediately saw that the same boards that we would develop for the Exercisor could fit nicely in a commercial computer system business. We gleefully developed a prodigious 5-year plan to launch this

Lyman Hevle

business. Our plan was to furnish the systems hardware and systems software, limited to operating system and languages. We had already lined up independent established distributors who would handle sales and service and develop user application software. A marriage made in heaven. Glenn Iaggi (our boss), Dick Ruth, and I made a triumphant trip to Shaumberg to excite the brass with our creativity. All the brass was there. About halfway into our presentations, Motorola President John Mitchell abruptly stopped us and told us we were computer retreads who would diminish his base business profits. He strongly stated that Motorola would never be in the computer business. We protested that Motorola was already in the revolutionary computer business by virtue of the microprocessors. When I asked him if there was no place for creative people who could lead Motorola into the future, he said there wasn’t. We packed up our papers in complete defeat and left the boardroom. We really didn’t know if we had been fired or not. We weren’t. Bob Galvin would visit us quite often for our “Moments of Madness” looks into the future, and told us he understood us and appreciated our forward thinking. We partially satisfied our longings by offering our Exercisor as an end-use system in the process automation market. It wasn’t a good fit and our success was modest at best. The 68000 series came along, and our expansion desires were rekindled. Our Microsystems engineers designed the EXORmacs development system. Max Loesel (our Europe Manager) made me aware of the European developing standard called Eurocards. It came in single, double, and triple widths. I argued for this approach. I lost because of strongly stated engineering requirements and distaste for anything European at that time. Another reason was that engineers from the large computer businesses were used to big boards. There was no way we could sell these big VERSAbus modules in the process automation market. Max, however, didn’t give up. His engineers retrofitted the VERSAbus onto double Eurocards in his Munich “skunk works.” He kept me up-to-date and even took me to see some of his prospective customers. I was hooked, and the result was called Versa Module Europe. Its acronym became “VME.”

20 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


There was a certain NIH feeling in Phoenix and a little “we/they” animosity. I was delighted with the VMEbus market prospects because of not only its size, but also more importantly because it was a standard that other manufacturers could use. The trick now was to get management acceptance and approval. On a trip to the Shaumberg Corporate Planning, I explained that with VMEbus we could catch Intel, whose Multibus II was quickly gobbling up the market. The next idea was that if we shared the VMEbus with other manufacturers, we would swamp the market with VMEbus boards and bury Intel. Sharing a standard technology was something Intel would never consider. Just then John Mitchell looked in and said these two ideas were stupid. His rationale was: 1. You have already spent a ton of money developing VERSAbus. Why spend it again just changing the size? 2. You have spent a lot of money developing the technology. Why on earth would you want to give it away? I told him the KOA Camp story. Will we settle for 100 percent of a small piece of the pie, or get rich with a smaller percentage of a gigantic pie? He reiterated that computer retreads were dangerous. He didn’t say no, so I took it as tacit approval. Motorola Microsystems embraced the concepts. We sent Jim Gunderson to explore the cooperation concept with Philips/Signetics and United Technologies [key 68000 supporters], and they were ecstatic. Thus began a series of meetings to determine which company would build which boards to share with each other. This entire group spent a lot of time with attorneys to make sure we avoided any anti-trust situations. Philips/Signetics jumped on board and designed some boards. Time went slowly by with modest results. Management changes were made at the Corporate and Semiconductor levels. Dick Ruth was fired and this troubled me greatly. I was asked if I wanted to be interviewed for his job and I quickly declined. The new Microsystems manager knew nothing of our dream. New blood was inserted www.vita-technologies.com

into Microsystems who I felt were nice guys but incompetent to lead Microsystems to any creative new heights. They had zero marketing and/or business acumen. Yes, I was totally disillusioned with Motorola. I told my new boss that I was going to leave Motorola but I would stay long enough to produce a comprehensive five-year plan to launch VMEbus into the process automation business. This had been my background with General Electric. I told him I would do it with Shaumberg Planning cooperation and management approval. I knew enough from our failures with top management to omit any land mines. For example, I would never mention computer systems, but rather call them “process controllers.” The plan was completed, but I felt little understood by the new Microsystems. I left Motorola and joined Dick Ruth with GEC of England. They were developing a super mini-computer and needed some marketing and business planning. A few years later I got a call from Jim Gunderson of Microsystems, saying that VMEbus was going nowhere, and did I have any ideas to get it moving? I said I would do an international study if the three VMEbus principals would foot the bill. They pledged about $300,000 and hired me. I listened and made speeches all over the United States and Europe. I painted an alluring picture of a business that could inure to one billion dollars in five years (and it did). The response was a standing ovation in each location. They each wanted a longer private meeting. This we did, and the results were stunning. They all wanted a piece of a new VMEbus adventure. The resulting consulting report was easy for me to write because my previously conceived ideas were validated. I presented the report to Motorola, Philips/Signetics, and United Technologies in Las Vegas. All three companies eagerly accepted the formation of an International VMEbus Trade Association … hence VITA was born. The report covered the structure of VITA and how it would operate in detail. The next step in the report was to hire an executive director. It was decided that each company would produce a candidate. Each candidate would visit each company, which would result in an appointment. Motorola voted for me, but the others had some reservations. They had two concerns about me. One was that I had been an employee of Motorola and might be biased. The other was that I had a reputation as an entrepreneur and owned several outside businesses. I told each that I admired Motorola very much, but had left them two years ago with much disappointment. On the question of allocation of my time, I said I would write a binding contract to limit my outside activities. I said VITA would be my burning passion, and that if I had nothing else, I had integrity. I was hired and started immediately. The starting point was selling VITA membership in several classifications according to the plan. This went extremely well, and we then developed the Compatible Products Directory (CPD), VITA Journal, Mailing Lists, et al. We also published the VMEbus specification, as well as a VMEbus technical design manual. We held technical seminars and participated in shows all over the world. We established a very successful VITA office in Europe with brilliant Zoltan Hunor as director. We also had satellite offices in Tokyo and Moscow. We were able to get the U.S. Navy to standardize on VMEbus, then the Army and Air Force. Soon all the world’s military forces followed suit. A major accomplishment was the reduction of Intel’s percentage of the market from 95 percent to zero. They eventually discontinued their Multibus II board operations. Mission accomplished. I retired in 1995 and have not followed the progress of VITA or the VMEbus since then. VITA was the high point of my professional life, and I am eternally grateful to the very many fathers and pioneers of VMEbus.

VITA TECHNOLOGY HALL OF FAME Main page: http://opensystemsmedia.com/hall-of-fame/vita-technologies Nomination guidelines and nomination form: http://opensystemsmedia. com/hall-of-fame/vita-technologies/nomination-guidelines VITA Technologies Resource Guide Spring/Summer 2016 |

21


PRIMETIME CHOICES

VRT protocol engine paves way for the future of signal processing The VITA 49 Radio Transport (VRT) standard defines a transport-layer protocol for data and context packets designed to promote interoperability between radio frequency (RF) receivers and signal processing equipment in a wide range of communication and radar systems. The Pentek Cobalt Model 71664 XMC FPGA module is a 4-channel 200 MHz 16-bit A/D with programmable digital down converter based on the Xilinx Virtex-6 FPGA. Model 71664 is the first Pentek product to include an IP engine for the VRT protocol. “VRT is the future of software-defined radio,” said Paul Mesibov, Pentek’s VP of engineering. “The protocols defined in VRT provide data and context packets that standardize the way information is transported from radio to signal processing equipment.” A front-end A/D converter stage accepts four analog HF or IF inputs on front-panel SSMC connectors, with each transformer coupled to Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The 200 MHz sampling rate handles the needed bandwidth for a wide range of signal processing applications. [Image shows Cobalt Model 71664 on a 3U VPX module, model 53664.] Pentek • www.pentek.com • www.vita-technologies.com/p373439

T2080-based VME SBCs boosts performance at reduced cost Performance, cost, and product longevity are frequently the top buying decisions with SBCs. Curtiss-Wright Defense Solutions’ SVME/DMV-196, its newest Power Architecture (PA) based 6U VME SBC, fits the bill for these requirements. The rugged SBC delivers up to 6x higher performance in a similar power envelope and at a lower price point compared to earlier single- and dualprocessor PA VME SBC designs. Highlighting Curtiss-Wright’s commitment to its VME customers, the SVME/DMV-196 is the first in a new family of SBCs designed with the company’s new obsolescence-fighting FPGA-based Helix PCI Express to VME64x interface. To further aid longevity of supply, a key requirement for most rugged embedded defense and aerospace applications, the board’s T2080 processor is backed with NXP Semiconductor’s 15-year life cycle. “This powerful new Power Architecture SBC delivers all the advantages of non-throttled quad-core processing and AltiVec while easing technology insertion for customers using a previous generation of Curtiss-Wright products,” said Lynn Bamford, senior VP and general manager of the Defense Solutions division. Curtiss-Wright Defense Solutions • www.curtisswrightds.com • www.vita-technologies.com/p373440

Broad-bandwidth OpenVPX processor blade opens processing possibilities “Ensemble LDS6526 processing blades are the highest-performing sensor processing blades available in the embedded industry today, with a maximum theoretical processing capability of 576 single-precision GFLOPS supported by an enhanced sensor I/O bandwidth of 5 GBps per channel. These OpenVPX 6U blades are opening the door to a host of new possibilities for sensor chain architects,” said Shaun McQuaid, director of product management at Mercury Systems’ Embedded Products Group. The Ensemble LDS6526 leverages Mercury’s fourth generation of size, weight, and power (SWaP)-efficient packaging technology to securely house the Arria 10 FPGA and Intel Xeon Processor D-1500 system-on-chip (SoC) devices for reliable deployment right to the tactical edge. The Ensemble LDS6526 secures and reliably cools commercial technology to produce a dense, powerful combination of server-class, low-latency, front-end FPGA processing with advanced switch fabric management in an open-systems blade that is designed and made in the United States. Mercury Systems, Inc. • www.mrcy.com • www.vita-technologies.com/p373441

22 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


VITA Technologiess Resource Guide

2016 RESOURCE GUIDE INDEX Company

Category

ADLINK Technology

VPX

ALPHI Technology Corporation

Page

Company

Category

Page

43

Interface Concept

Networking

26

PMC

37

Interface Concept

OpenVPX

33

Annapolis Micro Systems, Inc.

FMC

25

Interface Concept

OpenVPX

34

Annapolis Micro Systems, Inc.

OpenVPX

27

Intermas US LLC

VME

40

Annapolis Micro Systems, Inc.

OpenVPX

28

KONTRON

OpenVPX

34

Annapolis Micro Systems, Inc.

OpenVPX

29

KONTRON

OpenVPX

35

Annapolis Micro Systems, Inc.

OpenVPX

30

LCR Embedded Systems

VPX

46

Annapolis Micro Systems, Inc.

OpenVPX

31

North Atlantic Industries, Inc.

VME

41

Annapolis Micro Systems, Inc.

Operating Systems and Tools

38

Pentair/Schroff

OpenVPX

35

Annapolis Micro Systems, Inc.

Operating Systems and Tools

39

Pentair/Schroff

VME

41

Concurrent Technologies

VPX

44

Pentek

OpenVPX

36

Curtiss-Wright Defense Solutions

VPX

44

Pixus Technologies

OpenVPX

37

Dawn VME Products

OpenVPX

32

TE Connectivity

VPX

46

45

Themis Computer

Small Form Factor

40

33

TTI & TE Connectivity

VPX

47

InnovativeNOTE: IntegrationKEYLINE DOES FMC NOT PRINT

26

Vector Electronics & Technology, Inc.

VME

42

as shown InnovativeTRIM Integration

47

Highland Technology VITA Elma Electronic Inc.Summer Issue insert VPX 04/01/15 Hartmann Electronic

OpenVPX

XMC/PMC

Continuing our long term commitment to VME HIGHLAND TECHNOLOGY CRATE CONTROL Cabled PCIe, ethernet / USB DATA ACQUISITION Precision analog Wide range source measurement Synchro / resolver / LVDT Tachometer / overspeed Thermocouple / RTD / Cryo Isolated digital input Resistance measurement

OUTPUT and SIMULATION Arbitrary waveform Rotating machine Synchro /resolver / LVDT Thermocouple Analog and digital / relay I/O Voltage and 4/20 mA I/O

www.HighlandTechnology.com tel: 1-415-551-1700 fax: 1-415 551-5129

24 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


Ultra-Low Latency DRFM-Optimized Mezzanine Cards These ultra-low latency mezzanine cards are specifically designed for DRFM applications with latency as low as 20ns from SMA to SMA. Ultra-Low Latency DRFM-Optimized Mezzanine Cards have been designed from the ground up for latency sensitive DRFM applications. The Board Support Interface, which is available in VHDL or Open Project Builder, was also designed from the beginning to be suited for DRFM applications. This interface provides a Digital Bypass Mode to achieve the lowest possible latency and a Fabric Space Mode to allow the user to do additional processing and manipulation of the ADC data before returning it out the DAC. The Fabric Space Mode adds as little as 13ns of latency. The Board Support Interface also includes a built-in Bypass Delay. This allows the user to “walk” the latency out from the minimum Digital Bypass Mode latency to slightly beyond the Fabric Space Latency, providing for a smooth latency transition between the two modes. Open Project Builder, Annapolis’ FPGA Design Tool, allows the user to design a DRFM-optimized application in minutes.

FEATURES ĄĄ

Single or Dual Channel available running at up to 3GSps each

ĄĄ

Ultra Low latency from ADC SMA input to DAC SMA output • Digital Bypass Mode (SMA-to-SMA): as low as 21ns • Fabric Space Mode (SMA-to-SMA): as low as 39ns

ĄĄ

Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sclk periods

ĄĄ

Support for a variety of WILDSTAR mainboards

ĄĄ

Firmware and Software Board Support Interface provided in Open Project Builder

ĄĄ

Converter channels can be synchronized

Latency Number of Channels

Digital Bypass Mode

Fabric Space Mode

Speed (GSps)

ADC (bits)

DAC (bits)

3.0GSps 12-Bit ADC & DAC for WILD FMC+

1+1

<37ns

<50ns

3.0

12

12

2.5GSps 10-Bit ADC 12-Bit DAC for WILD FMC+

1+1

< 21ns

< 42ns

2.5

10

12

2+2

< 24ns

< 39ns

1.5

12

12

WILDSTAR Dual 1.5 GSps 12-Bit ADC & DAC Converter Mezzanine

vita.opensystemsmedia.com/p373414

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/product-category/adc-dac-drfm/ www.vita-technologies.com

 wfinfo@annapmicro.com  410-841-2514

VITA Technologies Resource Guide Spring/Summer 2016 |

25

VITA Technologiess Resource Guide

FMC


VITA Technologiess Resource Guide

FMC

FMC Modules Innovative Integration’s FMC Family of Modules: Module

A/D

D/A

FMC-1000

2x1250MSPS • 14b

2x1250MSPS • 16b

FMC-500

2x500MSPS • 14b

2x1230MSPS • 16b

FMC-310

4x310MSPS • 16b

FMC-250

2x250MSPS • 16b

2x500MSPS • 16b

FMC-Servo

8x500KSPS • 16b

8x500KSPS • 16b

FMC-SFP+

4xSFP+ Ports

FMC-QSFP

2xQSFP Ports

FMC-SDF

4x1MSPS • 14b

FMC-10GE

2x10Gbe ePC-K7 only

FEATURES ĄĄ

1x1MSPS • 16b

Download data sheets and pricing now!

High Speed Digitizing Signal Generation for Wireless Transceiver Pulse Generation, Medical Imaging, Precision Recording/Playback, RADAR, LTE WiMAX Physical Layer, Wireless Receiver and Transmitter

ĄĄ

Remote Radio Head receiver, OBSAI and CPRI interface

ĄĄ

Serial FPDP and SRIO fiber optic ports vita.opensystemsmedia.com/p373447  sales@innovative-dsp.com  805-383-8994

Innovative Integration

www.innovative-dsp.com

Networking

ComEth4080a The ComEth4080a expands our ComEth40xx range in the 3U VPX world. The ComEth4080a provides up to 21 Giga ports and covers a lack of the current OpenVPX release by offering a mix of 1000Base-T and 1000Base-KX ports on the backplane. The ComEth4080a can cover the needs for 1000-KX CPUs interconnection via the backplane, but also the needs to connect legacy boards, external sensors or systems claiming for 1000Base-T interfaces. This switch supports full-wire speed L2 bridging and L3 routing with L2-L4 advanced traffic classification, filtering and prioritization with optimized power consumption. It is fully upward compatible with the Switchware of our ComEth40xx range; it thus benefits from all the latest developments including: IPv6 support, RIPng, OSPF v3, VRRP, additional security features (HTTP/SSH client authentications), configurable memory allocation, and new status counters.

Interface Concept

www.interfaceconcept.com

FEATURES ĄĄ

Ethernet port configuration: • 8 1000Base-BX on P1 (RB) • 12 1000Base-T on P1/P2 (RB) • 1 auto media detect Ethernet port (FB) • 10/100/1000Base-T (RJ45) or 1000Base SX

info@interfaceconcept.com

26 | VITA Technologies Resource Guide Spring/Summer 2016

vita.opensystemsmedia.com/p370370

 +33(0) 2 98 57 30 30 or 800-445-6194

www.vita-technologies.com


Processing – Arria 10 and UltraScale Annapolis FPGA boards are engineered for superior performance and maximum bandwidth. Both Altera and Xilinx FPGAs are leveraged to offer the best FPGA technology available and to fit customer preference, design requirements and production schedule. These FPGA cards paired with Annapolis OpenVPX compliant 6U/3U backplanes enable even the most bandwidth-intensive applications.

FEATURES ĄĄ General Features

• • • • • • • • • • • • • •

Altera Arria 10 or Xilinx Kintex UltraScale FPGAs – Hard 8x PCIe Gen3 endpoint for DMA and register access – FPGAs programmable from attached flash or Annapolis provided software API – 20-nm copper CMOS process – Available with DDR4 DRAM, QDR-IV SRAM ports on all FPGAs Dual Core ARM Cortex-A9 Processor (Cyclone V or Zynq SoC) – Host Software: Linux API and Device Drivers PLX PCI Express Gen3 Switch – Allows expansion plane “chaining” of PCIe bus between adjacent slots. No dedicated PCIe switch slot needed Available in 6U and 3U form factors A Full Board Support Package using Open Project Builder for Fast and Easy Application Development • System Management

ĄĄ Backplane I/O

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

• Two PCIe Gen3 4x Connections to VPX Backplane • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK • – Allows reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards

ĄĄ Front Panel I/O

• Wild FMC+ (WFMC+) next generation I/O site based on FMC+ specification • – Accepts standard FMC and FMC+ cards (complies to FMC+ specification) • Up to 32 High Speed Serial and 100 LVDS connections to FPGA

ĄĄ Mechanical and Environmental

• Available in Extended Temperature Grades • Air or Conduction Cooled path • RTM available for additional I/O vita.opensystemsmedia.com/p373445

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/products/wildstar-ultrak-3u-openvpx/ www.vita-technologies.com

 wfinfo@annapmicro.com  410-841-2514

VITA Technologies Resource Guide Spring/Summer 2016 |

27

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

OpenVPX

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

Ruggedized Systems and High Temperatures Ruggedized COTS systems from Annapolis Micro Systems are designed to withstand the harshest environments. From the bitter cold of an Antarctic radar station to the hottest deserts of the Middle East, AMS equipment is real-world deployed for the most demanding embedded applications. Cooling Options Depending on the application, AMS chassis are robustly designed using Air, Conduction, or Liquid cooling. During the design process, every board and system is simulated for thermal performance, then subjected to hours of grueling operation to verify its ability to withstand temperature stresses. Independently Verified AMS verifies environmental conformance of its equipment

to various stringent standards such as MIL-STD-810 and RTCA/DO-160 (for airborne equipment). This independent testing proves the ability to withstand: • Temperature extremes & thermal shock • Liquid & dust ingress • Humidity, fungus & corrosion • Vibration & shock • Other application-specific stressors Designed & Manufactured in USA All AMS products are engineered and manufactured under one roof in the United States. This co-location of engineering and manufacturing allows for more aggressive design, and better quality control and production flexibility.

Thermal Model of an Annapolis Conduction-Cooled WILDSTAR 3U OpenVPX Chassis vita.opensystemsmedia.com/p373413

Annapolis Micro Systems, Inc. www.annapmicro.com

28 | VITA Technologies Resource Guide Spring/Summer 2016

 wfinfo@annapmicro.com  410-841-2514

www.vita-technologies.com


Wild40 OpenVPX EcoSystem Chassis In May 2013, Annapolis became the first company to bring 40Gb bandwidth to OpenVPX with our line of COTS backplanes, chassis and payload cards that are fully designed, qualified and tested for 40Gb bandwidths. The Wild40 EcoSystem for OpenVPX chassis includes both switched and mesh backplane architectures and has already been FEATURES ĄĄ OpenVPX High Speed Backplane with RTM Support extensively deployed around the world. Annapolis tests the interoperability between Wild40 EcoSystem components on each and every chassis to ensure reliability, consistent performance and best possible user experience. Annapolis is moving towards 100 Gb EcoSystems that are easier to both deploy and maintain. System designs are streamlined by moving as many connections as possible to the rear or onto the backplane. These upgraded EcoSystems simplify maintainability by removing all or many of the connections from the front of the modules. Annapolis is also developing large, modular chassis systems. All components of the chassis will be top-mounted. All payload cards, switch cards, 6U power modules, and fan trays will plug into one backplane. These chassis will feature hot-swappable components and cables will be minimized.

• • • • •

10.3 Gbps Line Rates on Data and Expansion Planes 40GBase-KR4 Ethernet 10GBase-KX4 XAUI SDR, DDR and QDR 4x InfiniBand 2.5-10 Gbps AnnapMicro Protocol (Low FPGA utilization protocol for FPGA-FPGA connections) • 8x PCIe Gen 1, 2 or 3 • 1000Base-x on Control Plane

ĄĄ Chassis Management: Voltage, Temperature and Fan

Monitoring and Control

ĄĄ Front Chassis Display Panel ĄĄ Front Panel Power Switch, System Reset Switch and

Maskable Reset Switch, All with Safety Covers

ĄĄ Allows for boards to be Hot Swappable ĄĄ High Performance Air Cooling with Cleanable Fans and Filters

(Conduction Cooling and Liquid Cooling options available)

ĄĄ Electromagnetic Shielding ĄĄ Commercial Environmental Specifications

• Temperature: Operating: 0 to +50 C Storage: -20 to +70 C • Altitude: Operating: 0 to 6,000 Feet Storage: 0 to 50,000 Feet • Humidity: Operating and Storage: 5 to 95% Noncondensing • Vibration Sine: 1.0g @ 10 to 330Hz • Shock: 10 Gs @ 11ms vita.opensystemsmedia.com/p373409

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/product-category/chassis-openvpx-6u-ecosystem/ www.vita-technologies.com

 wfinfo@annapmicro.com  410-841-2514

VITA Technologies Resource Guide Spring/Summer 2016 |

29

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

OpenVPX

WILD Data Storage Solution When Storage capability is needed, Annapolis offers the highest density OpenVPX storage solutions on the market. Available in 6U and 3U form factors, the WILDSTAR Data Storage Solution features a removable hot swappable canister with a connector rated for 10,000+ mating cycles. The WILD Data Storage Solution comes with standard images to support XAUI, 40GbE and AnnapMicro Protocol (Annapolis low FPGA utilization, full flow control protocol ideal for inter-FPGA communication). The WILD Data Storage Solution is comprised of two pieces fitting in a single 1" OpenVPX slot, the “Storage FEATURES Canister” and the “Storage Carrier” that plugs into the VPX

ĄĄ

3U boards feature 8 TB (currently) or 16 TB (available in 2017) Storage Depth and 5-7 GB/s Bandwidth

ĄĄ

6U boards feature 16 TB (currently) or 32 TB (available in 2017) Storage Depth and 10-14 GB/s Bandwidth

ĄĄ

Backplane I/O using PCIe or 40Gb Ethernet

ĄĄ

Scalable Depth and Bandwidth using multiple Storage Cards

ĄĄ

Hot Swappable Drive Canister with 10,000 Insertion Cycles & Hot Swappable Carrier (exclusive to WILDSTAR OpenVPX EcoSystem)

We offer training and exceptional

ĄĄ

6U/3U OpenVPX (VITA 65) Compliant, 1" VITA 48.1 spacing

special application development support,

ĄĄ

Air Cooled or Conduction Cooled

as well as more conventional support.

ĄĄ

Proactive Thermal Management

backplane and holds the disk canister.

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed.

vita.opensystemsmedia.com/p373411

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/product-category/storage-boards/

30 | VITA Technologies Resource Guide Spring/Summer 2016

 wfinfo@annapmicro.com  410-841-2514

www.vita-technologies.com


WILDSTAR A5 and WILDSTAR 7 for OpenVPX FPGA Boards Annapolis FPGA boards are engineered for superior FEATURES performance and maximum bandwidth. Both Altera and Xilinx FPGAs are leveraged to offer the best FPGA technology available and to fit customer preference, design requirements and production schedule. These FPGA cards paired with Annapolis OpenVPX compliant 6U/3U backplanes enable even the most bandwidth-intensive applications.

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

ĄĄ General Features

• Xilinx Virtex 7 or Altera Stratix® V FPGAs • PCIe Gen3 8x from each FPGA to on-board PCIe switch • Up to 24x High Speed Serial I/O lanes to VPX Backplane (P1/P2) for up to 60 GB/s of Full Duplex Bandwidth • Manufacturing options for SRAM or DRAM on the IOPE as well as multiple memory sizes • RTM available for additional I/O • Available in 6U and 3U form factors • A Full Board Support Package using Open Project Builder for Fast and Easy Application Development • System Management • Hot Swappable

ĄĄ Backplane I/O

• Two PCIe Gen3 4x Connections to VPX Backplane • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK • – Allows reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards

ĄĄ Front Panel I/O

• Accepts Standard Annapolis WILDSTAR Mezzanine Cards, including a wide variety of WILDSTAR ADC and DAC Mezzanine Cards • Three or six optional built-in Front Panel QSFP+ Transceivers running at up to 52.4 Gbps each for 39 GB/s of Full Duplex Bandwidth • QSFP+ Protocol Agnostic connections support 10/40Gb Ethernet, SDR/DDR/QDR InfiniBand, AnnapMicro protocol and user-designed protocols

ĄĄ Mechanical and Environmental

• Available in Extended Temperature Grades • Air or Conduction Cooled path • RTM available for additional I/O vita.opensystemsmedia.com/p373415

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/product-category/fpga-boards-openvpx-6u-ecosystem/ www.vita-technologies.com

 wfinfo@annapmicro.com  410-841-2514

VITA Technologies Resource Guide Spring/Summer 2016 |

31

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

OpenVPX

Fabric Mapping Modules Dawn OpenVPX backplane Fabric Mapping Modules simplify topology customization. Dawn VME Products FABRIC MAPPING MODULES automate optimization of OpenVPX backplane topologies. Newly patented FMM micro-overlays quickly customize off-the-shelf OpenVPX backplanes to mission requirements. Fabric Mapping Modules allow designers to work with flexible configurations of high speed links. Off-the-shelf backplanes can be quickly customized to mission requirements without the time and expense required for new backplane designs, a critical advantage when schedules are compressed by late system changes. Dawn engineers have successfully used Fabric Mapping Modules to solve many OpenVPX application problems in the design phase. Fabric Mapping Modules provide a natural migratory development environment for moving from the lab to the field with high speed OpenVPX backplanes.

FEATURES ĄĄ Off-the-shelf backplanes can be quickly customized to mission

requirements

ĄĄ Optimize the communication topology between slots within a system’s

backplane

ĄĄ Customize inter-slot communications to meet unique system

requirements

ĄĄ Improve signal integrity between system cards beyond requirements of

PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards

ĄĄ Directly connect PCI Express or SerialRapid I/O to multiple cards or

cards and switches

ĄĄ Link SATA from a CPU card to a Solid State Drive (SSD) carrier ĄĄ Enable XMC cards to talk to other XMC cards or other I/O like

PCI Express links

ĄĄ Facilitate rear backplane I/O connections and low profile connector

interface systems when normal transition modules do not fit the system application envelope

vita.opensystemsmedia.com/p372452

Dawn VME Products www.dawnvme.com

 sales@dawnvme.com  800-258-DAWN (3296) • 510-657-4444

OpenVPX

PSC-6265 VITA 62 compliant 6U power supply for conduction cooled systems. Dawn’s VITA 62 compliant 6U PSC-6265 can operate continuously in diverse environments over a wide range of temperatures at high power levels. The standard model is conduction to wedge lock cooled with an operating temperature range of -40C to +85C and a nonoperating range of -55C to +105C. The PSC-6265 operates continuously at a power level of 580 watts. For systems that require higher power levels, up to three supplies may be operated in parallel. Fault monitoring and control circuits protect the system from overvoltage, over-current, and over-temperature conditions. Power supply operational or fault status is displayed using colored LEDs on front panel.

FEATURES ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ

Continuous 580W output over temperature range of -40C to +85C True 6 Channel supply provides full OpenVPX support Secondary Side Wedge lock conduction cooled 6U, 1 inch pitch form factor Compatible with Dawn’s HLD-6262 Holdup Module Fault monitoring and control Output over-voltage, over-current, and over-temperature shutdown protection Current/Load share compatible with up to 3 PSC-6265 units Standard INHIBIT*, ENABLE*, FAIL* and SYSRESET* control signals VBAT for support of VPX memory backup power bus Front I/O panel includes LED status indicator, and VBAT battery access VITA 48.2 Compliant Inject/Eject levers for easy installation vita.opensystemsmedia.com/p372930

Dawn VME Products www.dawnvme.com

32 | VITA Technologies Resource Guide Spring/Summer 2016

sales@dawnvme.com  800-258-DAWN (3296) • 510-657-4444 

www.vita-technologies.com


OpenVPX Product Range Hartmann Electronic offers a full product range of OpenVPX products, like BACKPLANE, POWER SUPPLY, ATR, Power BACKPLANE, SHELF MANAGER, 19'' RACK, high speed ADAPTERS, BRIDGES, OPEN FRAME Chassis, and LOAD BOARDS. With a long experience in Backplane design, for more than 40 years, Hartmann Electronic started in 2008 with the first VPX-Backplane design. Since 2012 Hartmann Backplanes support 50 GBit PCIe transmission (FP) and 10 GBit Ethernet. The newest Backplanes are VITA 66 based for Fiber Optics and RF Signals. In addition, Hartmann designed VPX Power Supplies according to VITA 62, in 3U, 6U, air cooled and conduction cooled. Housings are available as ATR or in 19'' form factor. For development purposes, Hartmann offers different Open Frame chassis and a transportable Tower Rack. Other accessories like Load Boards, Shelf Managers, and Power Backplanes are also available in different sizes. Hartmann specialties are custom designed high speed Backplanes and System Platforms for different Standards or complete custom. At the moment Hartmann is releasing a brand new PCIe Extension Board that can be used to run commercial PCI or Micro PCIe devices on OpenVPX Backplanes or CompactPCI Serial Backplanes. Systems can be linked together by fiber optic cables.

Hartmann Electronic

www.hartmann-electronic.com

FEATURES ĄĄ OpenVPX Backplanes 50Gbd PCIe, 10GBit Ethernet ĄĄ VITA 62 Power Supplies, 3U, 6U, air-, conduction-cooled ĄĄ ATR conduction cooled ĄĄ Open Frame and Tower Chassis for VPX ĄĄ Load Boards 3U, 6U, air-, conduction-cooled ĄĄ Power Backplanes 3U, 6U ĄĄ VITA 66 Backplanes for Fiber or RF vita.opensystemsmedia.com/p373429

info@hartmann-electronic.com

 +49 711 13989 0

OpenVPX

IC-FEP-VPX3c The IC-FEP-VPX3c expands our Front End Processing family with a solution based on Xilinx Virtex-7 FPGAs to respond to seemingly insatiable bandwidth demand. Designed for applications requiring a very high level of computing power in a compact 3U form factor, the IC-FEP-VPX3c board offers the highest bandwidth with the lowest power consumption. The IC-FEP-VPX3c and the other building blocks of our 3U OpenVPX product ranges (Intel and Freescale SBCs, Ethernet Switches and Routers, I/O boards/FMC) running our Signal Processing Reference Design (including signal acquisition, Processing, DMA Engine, data storage, signal generation) are the ideal platforms for customers who want to streamline development by concentrating their efforts on their most critical tasks.

Interface Concept

www.interfaceconcept.com www.vita-technologies.com

FEATURES ĄĄ Xilinx Virtex-7 XC7VX690T (other versions on demand) ĄĄ Two banks of DDR3: 64-bit wide, 2GB each ĄĄ Optional QDRII+ 450MHz, 36-bit wide/up to 36 Mb ĄĄ 128 MB of BPI NOR flash (bitstream storage) ĄĄ VPX interfaces: Four 4-lanes fabric ports on P1, general-purpose

I/O on P2

ĄĄ FMC interfaces: 8 GTX/GTH (FPGA part number dependent),

80 differential pairs, 4 reference clocks

vita.opensystemsmedia.com/p371808

info@interfaceconcept.com

 +33(0) 2 98 57 30 30 or 800-445-6194

VITA Technologies Resource Guide Spring/Summer 2016 |

33

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

OpenVPX

IC-FEP-VPX6a The IC-FEP-VPX6a is a VPX hybrid processing engine coupling the latest generations of FPGAs and processor, both of them delivering a very high level of performance per watt. With its QorIQ processor for system management and a PCIe advanced switch for versatile coupling between the processing nodes, the IC-FEP-VPX6a board expands the flexibility of the two Virtex-6 FPGAs and the VPX high bandwidth serial interfaces. Two FMC mezzanine sites enlarge the adaptability of the board to connect ADC, DAC, general I/O, video, sFPDP or additional FPGA FMC modules. With this combination of high performance CPU, dual FPGAs and FMC sites, the IC-FEP-VPX6a provides the ideal platform for radar, sonar, electronic warfare and other very high demanding digital signal processing applications.

Interface Concept

www.interfaceconcept.com

FEATURES ĄĄ Processing units: One QorIQ processor P2020, 1 GHz, e500 v2

core, two Xilinx Virtex-6 SX315T (-1 or -2), SX475T (-1 only), LX240T or LX550T, one Spartan-6 LX-45T

ĄĄ VPX interfaces: 4 PCIe x4 port (from PCIe switch), GTX ports,

2 GTP

ĄĄ General-purpose I/O: 2 LVDS (16 from each FPGAs), 2 differential

pairs (16 from each FMC I/O connector), GPIO

ĄĄ FMC interfaces: 80 LVDS, 4 reference clocks, 1 GTX x4 link vita.opensystemsmedia.com/p365111

info@interfaceconcept.com

 +33(0) 2 98 57 30 30 or 800-445-6194

OpenVPX

Kontron 3U VPX PCI Express and Ethernet hybrid switch VX3905 The Kontron 3U VPX PCI Express and Ethernet hybrid switch VX3905 is the ideal partner for the centralized backplane to efficiently handle a high bandwidth. It provides up to 24 Ports with 32 lane PCI Express Gen 1/Gen 2 switching and additional 9 port gigabit Ethernet switching capabilities for the control plane. By this it offers a tenfold increase in I/O bandwidth between computing boards in High Performance Embedded Computing applications compared to VME, unleashing a new kind of application for data processing platforms used for Radar, Sonar and general image processing. For customers to capitalize on the Kontron VX3905‘s high bandwidth, while enjoying optimized time-to-market in centralized VPX/OpenVPX™ architectures, Kontron offers VXFabric™, an efficient software solution for interboard communication. With Kontron VXFabric™ on Kontron 3U and 6U VPX processor boards, OEMs can use common Linux and TCP or UDP sockets. Kontron VXFabric™ software simplifies and accelerates application development and helps to extend application lifecycles as it enables migration to hardware communication standards, such as 10G and 40G Ethernet.

FEATURES ĄĄ Compliant with OpenVPX VITA65 profile SLT3-SWH-6F6U-14.4.1 ĄĄ Up to 24 Ports/32 Lanes PCIe Switch ĄĄ 9 Port Giga Ethernet Switch ĄĄ Air-cooled and Conduction-cooled Builds

The Kontron VX3905 is available in an air-cooled version (0°C to +55°C) and in rugged conduction-cooled version (-40°C to + 85°C).

KONTRON

http://www.kontron.com/industries/defense

34 | VITA Technologies Resource Guide Spring/Summer 2016

sales@us.kontron.com

vita.opensystemsmedia.com/p373394

 888-294-4558 @Kontron

 https://www.linkedin.com/company/kontron 

www.vita-technologies.com


VX3058 Octo Core Intel® Xeon® Processor VPX server blade Kontron‘s 3U VPX blade VX3058 is based on the highly integrated 8-core Intel® Xeon® D architecture, supporting Dual 10 Gigabit Ethernet, high bandwidth PCI Express 3.0, and high speed DDR4 memory. It is consequently SWaP-C optimized with versatile mezzanine options for XMC, storage, graphics, M.2, and I/O. The M.2 interface can be used for storage or for integration of customized personality modules. Front I/O module options are selectable for DVI/HDMI, Ethernet or other interfaces. The Kontron VxFabric™ provides a unique API that extends the TCP/IP protocol over the PCI Express infrastructure that when combined with Kontron's advanced switch technologies, enables significantly higher I/O bandwidth. The Kontron VX3058 is pin compatible with the company‘s popular and previous generation VX3044 3U VPX board, which already deploys 10 gigabit (G) Ethernet and PCIe gen3 on the OpenVPX backplane. Options include a shelf manager for centralized health management, sequenced system power-up and Temperature/Power/Performance management as well as Power-On Built-in Test (PBIT) that give designers a comprehensive package for board and system diagnosis.

KONTRON

http://www.kontron.com/industries/defense

FEATURES ĄĄ Fit for Virtual Machines and HPEC Applications ĄĄ Extended Life Cycle and 10-year Silicon Reliability ĄĄ Dual 10 Gigabit Ethernet, x8 PCI Express Gen3 Bandwidth ĄĄ 8 Core Xeon® Processor D, 16 GB DDR4 with ECC vita.opensystemsmedia.com/p373395

sales@us.kontron.com

 888-294-4558 @Kontron

 https://www.linkedin.com/company/kontron 

OpenVPX

Schroff High Clamp Force Retainers from Pentair Pentair is proud to offer the new Schroff Series 260HC High Clamp Force Card Lok retainer. The patent-pending design of the Series 260HC provides on average nearly triple the clamping force of similarly sized Card Loks. As systems continue to be integrated into rugged environments and face ever increasing shock and vibration, sufficient printed circuit board retention is critical. Additionally, SWaP or reducing size and weight while effectively handling increasing power, continues to be a focus for defense and aerospace designers and manufacturers. The Schroff Series 260HC overcomes these challenges, providing on average 1,257lbs of clamping force, in a compact form factor.

Conveniently, the Schroff Series 260HC has been designed to be a drop-in replacement for most applications currently using a standard 260 Card Lok, with the same profile 6.35 (.250") width x 6.86 (.270") height, mounting hole locations, and optional features such as a visual indicator and lock patch. Pentair is also pleased to offer a full range of OpenVPX, VXS, VME64x and VME Bus based products as well as a full range of power supplies, chassis components, cooling solutions and racking products to support all your project needs. Contact the experts at Pentair today to start your project on the path to success! vita.opensystemsmedia.com/p373450

Pentair/Schroff

http://www.pentairprotect.com/schroff-na www.vita-technologies.com

 AskSchroff@pentair.com  1-800-525-4682

VITA Technologies Resource Guide Spring/Summer 2016 |

35

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

OpenVPX

Model 5973-324

FEATURES

The Model 5973-324 is a member of the Flexor® family of high-performance 3U VPX boards based on the Xilinx Virtex-7 FPGA.

ĄĄ

As a FlexorSet™ integrated solution, the Model 3324 FMC is factory-installed on the 5973 FMC carrier. The required FPGA IP is installed and the board set is delivered ready for immediate use.

ĄĄ

ĄĄ

ĄĄ

The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection to the HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four 500 MHz, 16-bit A/Ds, four digital up converters, four 2 GHz, 16-bit D/As, and four banks of memory. In addition to supporting PCIe Gen. 3 as a native interface, the Model 5973-324 includes optional copper and optical connections to the Virtex-7 FPGA for custom I/O.

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock/Sync Bus D/A Clock/Sync Bus

Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 500 MHz 16-bit A/Ds & Four digital upconverters Four 2 GHz 16-bit D/As (500 MHz input sample rate, 2 GHz output sample rate with interpolation)

ĄĄ

4 GB of DDR3 SDRAM

ĄĄ

Sample clock synchronization to an external system reference

ĄĄ

PCI Express (Gen. 1, 2 & 3) interface up to x8

ĄĄ

User-configurable gigabit serial interface

ĄĄ

ĄĄ

ĄĄ

Optional optical Interface for gigabit serial interboard communication Compatible with several VITA standards including: VITA 46, VITA 48, VITA 66.4 and VITA 65 (OpenVPX™ System Specification) Ruggedized and conduction-cooled versions available

RF In

RF In

RF In

RF In

RF Out

RF Out

RF Out

RF Out

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

500 MHz 16-BIT A/D

500 MHz 16-BIT A/D

500 MHz 16-BIT A/D

500 MHz 16-BIT A/D

2 GHz 16-BIT D/A DIGITAL UPCONVERT

2 GHz 16-BIT D/A DIGITAL UPCONVERT

2 GHz 16-BIT D/A DIGITAL UPCONVERT

2 GHz 16-BIT D/A DIGITAL UPCONVERT

Control & Status VCXO

FMC CONNECTOR

Model 3324 FMC Model 5973 FMC Carrier

FMC CONNECTOR

160

10X

LVDS

GTX

VIRTEX-7 FPGA VX330T or VX690T GTX

CONFIG FLASH 1 GB

FPGA Config Bus

GTX

PCIe Gen. 3 x8

4X

16 pairs

GATEXPRESS PCIe CONFIGURATION MANAGER

PCIe Gen. 3 x8

VPX-P0

VPX-P1

FPGA Gigabit Serial I/O

GTX

LVDS

32

32

32

32

DDR3 SDRAM 1 GB

DDR3 SDRAM 1 GB

DDR3 SDRAM 1 GB

DDR3 SDRAM 1 GB

12X

FPGA Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional)

FPGA LVDS GPIO

VPX-P2 (½) VITA 66.4

VPX-P2 (½)

VPX BACKPLANE

vita.opensystemsmedia.com/p373426

Pentek

http://www.pentek.com/go/vita5973



sales@pentek.com www.linkedin.com/company/pentek

36 | VITA Technologies Resource Guide Spring/Summer 2016

 201-818-5900 @pentekinc



www.vita-technologies.com


OpenVPX Backplanes & Chassis Platforms Are you ready for a better experience for your OpenVPX backplane and chassis platform design? Then it‘s time to try Pixus Technologies. Our knowledgeable team will guide you through the process and help you find a cost-effective solution that meets your application‘s specific requirements. Pixus has a wealth of standard backplanes and modular OpenVPX enclosure platforms as a framework to start your tailored design. Whether it‘s a rugged chassis/ATR that meets MIL-704, 810, or 461, or a 19" rackmount design, Pixus has an OpenVPX solution for you.

FEATURES ĄĄ OpenVPX backplane expertise with various standard configurations ĄĄ Virtually unlimited options of OpenVPX chassis platform designs ĄĄ Integrated system management options ĄĄ Rugged conduction-cooled or convection-cooled options ĄĄ Options for full systems with OpenVPX SBCs, FPGAs, & specialty

boards

ĄĄ 40G backplanes, other high-speed options vita.opensystemsmedia.com/p373373

Enclosures Cases Subracks Backplanes Chassis Integrated Systems Components

 sales@pixustechnologies.com  519-885-5775

Pixus Technologies

www.pixustechnologies.com

 @pixustech PMC

PMC-CIV-COM-ISO Summary: • Cyclone IV EP4CE30 484-fbga package • Cyclone IV FPGA allows a wide range of customization options. • 4 Mbyte SRAM • SRAM is dual ported • User Reconfigurable I/O • ISOLATED I/O lines, Up to 155Mbps • Each GPIO line has independent Interrupt Support programmable for Edge trigger • On board Serial configuration device programmable via PMC bus or bit/byte blaster • Local serial EPROM • Internal/External clock • PCI +3.3V/+5V Operation and Logic • 32/64 MHz PMC clock support • Front panel I/O access • Windows, Linux and VxWorks Drivers

ALPHI Technology Corporation www.Alphitech.com www.vita-technologies.com

FEATURES ĄĄ User Programmable Altera Cyclone IV FPGA 484 BGA: ĄĄ Stand alone possibility ĄĄ Single wide PMC Module ĄĄ Opto Isolated 20 LVDS, 2 RS-422,1 RS-232 ĄĄ Optional User clock oscillator

Custom Designs: In addition, Alphi offers complete Engineering Design Services. Custom hardware, drivers and application software as well as FPGA development, we are ready to help. vita.opensystemsmedia.com/p373375

Sales@Alphitech.com

 480-838-2428

VITA Technologies Resource Guide Spring/Summer 2016 |

37

VITA Technologiess Resource Guide

OpenVPX


VITA Technologiess Resource Guide

Operating Systems and Tools

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

FEATURES Application Development Team

ĄĄ

Annapolis Micro Systems employs a select team of experienced FPGA designers dedicated to helping you solve your real-world processing challenges while minimizing your Time to Market. Our patented Open Project Builder provides high-speed solutions that get the application developed in record time, drastically reducing program cost and risk.

ĄĄ

Application Types: • Radar • ELINT • SIGINT • COMINT • Digital Recording Capabilities: • System Architecture • Algorithm sizing and implementation • GUIs

vita.opensystemsmedia.com/p372789

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/services-support/application-development-team/

38 | VITA Technologies Resource Guide Spring/Summer 2016

 wfinfo@annapmicro.com  410-841-2514

www.vita-technologies.com


Open Project Builder

FEATURES Board Support Space

The Annapolis Micro Systems, Inc. Open Project Builder provides the efficiency of CoreFire Next development with the flexibility of HDL. It integrates the CoreFire environment with Annapolis HDL board support packages.

ĄĄ

ĄĄ

User Space

The user has the capability to use FPGA IP from other sources, such as CoreFire Next, HSL, other HDL, etc. Open Project Builder can also port IP to/from other platforms. It uses standard Avalon and AXI IP interfaces. Open Project Builder uses fast portability of application between Altera and Xilinx and to newer FPGA families.

ĄĄ

Algorithmic: DSP, Math, etc.

ĄĄ

Data Flow Control

ĄĄ

Bit and Type Manipulations

ĄĄ

Board Support Packages for all WILDSTAR Boards: Stratix 5, Virtex 7, Arria 10, UltraScale, Stratix 10, etc.

vita.opensystemsmedia.com/p373350

Annapolis Micro Systems, Inc.

https://www.annapmicro.com/product-category/developmenttools/ www.vita-technologies.com

 wfinfo@annapmicro.com  410-841-2514

VITA Technologies Resource Guide Spring/Summer 2016 |

39

VITA Technologiess Resource Guide

Operating Systems and Tools


VITA Technologiess Resource Guide

Small Form Factor

NanoSWITCH NanoSWITCH is a SWAP-C optimized rugged multi-layer gigabit Ethernet switch with an embedded x86 PC. The NanoSWITCH brings enterprise level layer 2/3 switching to rugged environments including military ground, air and sea vehicles, and unforgiving industrial environments. Typical applications include vehicle network switching, distributed architecture vehicle controller, VICTORY compliant switch, router, timing, and control, WAN/LAN interconnectivity and firewall, and shared processing and peripheral communications. NanoSWITCH provides 16x or 10x external Gigabit Ethernet ports that operate at rates of 10, 100, and 1000 Mbps. A full management suite is included, as well as a Command Line Interface (CLI) for controlling switch and routing operations. The NanoSWITCH supports sophisticated IPv4 and IPv6 routing, including tunneling and IP Multicast, VLANs, and IETF, IEEE, and DSL Forum standards. The NanoSWITCH includes numerous Quality of Service (QoS) features to ensure that traffic is prioritized to deliver the superior performance for real-time applications including system management, voice, video, and bandwidth-intensive file uploads and downloads. NanoSWITCH is available in a VICTORY software configuration. The VICTORY open standard, or “Vehicular Integration for C4ISR/EW Interoperability” standard (http://victory-standards.org/), provides a common data-bus centric approach to sharing services and hardware components, eliminating redundancy and reducing SWAP in Army ground vehicles.

Themis Computer

www.themis.com/nanoswitch

FEATURES ĄĄ Layer 2/3 Enterprise non-blocking network switch for demanding

SWAP-C environments

ĄĄ 16x GigE Ethernet ports with auto tri-speed 10/100/1000Mbps

and MDIX

ĄĄ MIL-STD-1275E – Ground vehicle power; MIL-STD-704F –

Aircraft power (with no hold up); MIL-STD-461F – EMI; MIL-STD-810G – Environmental

ĄĄ 10 or 16 port versions ĄĄ Full featured AMD Fusion APU for VICTORY or user applications ĄĄ 1GB DRAM, 64GB SSD ĄĄ Operating temperature: -40°C to 71°C vita.opensystemsmedia.com/p373404

david.forbes@themis.com

 408-623-1545 @Themis_Computer

 http://www.linkedin.com/company/17952



VME

Intermas – InterRail Intermas develops electronic enclosure systems: Cabinets, housings, subracks, and an extensive range of accessories for the 19" rack systems used in the fields of PCI, VME/VME64x, cPCI, IEEE, and communication applications with state-of-the-art EMI- and RFI-shielded protection. Intermas has an extensive product range of more than 10,000 separate components and more than 30 years’ experience.

FEATURES ĄĄ InterRail® products meet tough physical demands and vibration

proofs used for railway engineering, traffic engineering, and power station engineering

ĄĄ 19" subracks and housings with flexible internal layout

Go to www.Intermas-US.com for our new catalog.

ĄĄ EMI- and RFI-shielded protection using stable stainless steel

contact springs ensuring permanent and reliable bonding

ĄĄ Connectors and wiring accessories ĄĄ Customization available vita.opensystemsmedia.com/p372664

Intermas US LLC

www.Intermas-US.com

intermas@intermas-us.com  800-811-0236 

40 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


6U VME COTS System - SIU6 Sensor Interface Unit Customer-configurable

The SIU6 is a highly configurable rugged COTS system or subsystem ideally suited for military, industrial, and commercial applications that require high-density I/O, communications, Ethernet switching, and processing. The SIU6 leverages NAI field-proven, 6U VME boards to deliver off-the-shelf, SWaP-optimized COTS solutions that Accelerate Your-Time-to-Mission.

Versatile Architecture

NAI’s Custom-On-Standard Architecture™ (COSA™) offers a choice of over 40 intelligent I/O, communications and Ethernet switch functions, as well as Single Board Computer (SBC) options. Pre-existing, fully tested functions can be quickly and easily combined in an unlimited number of ways to meet system requirements. Individually dedicated I/O and communications processors allow mission computers to manage, monitor, and control the functions via single or dual Ethernet ports. Alternately, select one of NAI’s 6U VME SBC options. All products are designed to operate under extreme temperature, shock, vibration, and EMI environments. EMI filters and gaskets meet or exceed MIL-STD-461F and MIL-STD-810G requirements. Eliminate man-months of integration with a configured, field-proven 6U VME COTS System or Subsystem from NAI.

FEATURES ĄĄ 2 x 6U VME slots – allows installation of up to 12 I/O or

Communications modules • 40+ modules to choose from

ĄĄ SBC-less stand-alone operation supported via Ethernet connection

to your mission computer

ĄĄ Processor options: NXP PowerPC QorIQ® P2041, Intel® Core™ i7,

Intel® Atom™ or ARM Cortex-A9 MIL-STD-461F, MIL-STD-1275 & 704A +28 VDC input Customer Configurable I/O, Communications and Processing 11.75" W x 3.35" H x 8.65" D Wind River® Linux/VxWorks®, Xilinx® PetaLinux, Windows® Embedded Standard 7 OS Support TM ĄĄ COSA Architecture ĄĄ Operating temperature: -40°C to +71°C Made in the USA Certified Small Business conduction cooled (air-cooled option) ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ

vita.opensystemsmedia.com/p373448

North Atlantic Industries, Inc.

http://www.naii.com/6U-VME-COTS-System-Sensor-Interface-Unit/P232

 lboccone@naii.com  631-567-1100

VME

Schroff Backplanes and Systems Chassis from Pentair Based on VITA Standards Pentair is proud to offer a full line of Schroff Backplane and Systems Chassis products compliant to VITA specifications. Open VPX, VXS, VME64x and VME Bus based products are available off-the-shelf from the standard catalog. Custom and modified products are expertly produced to your specifications using the latest processes and materials. Pentair offers the expertise to solve any chassis related challenges your project has to offer. Whether mechanical in nature or related to cooling or chassis management and monitoring, Pentair has decades of expertise bringing projects to success. Pentair has been a VITA member and active participant in specification and development for many years.

Additionally, Pentair offers a full range of power supplies, chassis components, cooling solutions and racking products to support your projects. Pentair offers board retainer and conduction cooling products, including ejector handles and CCA clamshell assemblies. Services including design, simulation, testing as well as production and supply chain logistics are available to support projects from the initial specification phase through production and delivery anywhere in the world. Contact the experts at Pentair today to start your project on the path to success! vita.opensystemsmedia.com/p373449

Pentair/Schroff

http://www.pentairprotect.com/schroff-na www.vita-technologies.com

AskSchroff@pentair.com  1-800-525-4682 

VITA Technologies Resource Guide Spring/Summer 2016 |

41

VITA Technologiess Resource Guide

VME


VITA Technologiess Resource Guide

VME

cPCI, PXI, VME, Custom Packaging Solutions VME and VME64x, CompactPCI, or PXI chassis are available in many configurations from 1U to 12U, 2 to 21 slots, with many power options up to 1,200 watts. Dual hot-swap is available in AC or DC versions. We have in-house design, manufacturing capabilities, and in-process controls. All Vector chassis and backplanes are manufactured in the USA and are available with custom modifications and the shortest lead times in the industry. Series 2370 chassis offer the lowest profile per slot. Cards are inserted horizontally from the front, and 80mm rear I/O backplane slot configuration is also available. Chassis are available from 1U, 2 slots up to 7U, 12 slots for VME, CompactPCI, or PXI. All chassis are IEEE 1101.10/11 compliant with hot-swap, plug-in AC or DC power options. Our Series 400 enclosures feature side-filtered air intake and rear exhaust for up to 21 vertical cards. Options include hot-swap, plug-in AC or DC power, and system voltage/temperature monitor. Embedded power supplies are available up to 1,200 watts. Series 790 is MIL-STD-461D/E compliant and certified, economical, and lighter weight than most enclosures available today. It is available in 3U, 4U, and 5U models up to 7 horizontal slots. All Vector chassis are available for custom modification in the shortest time frame. Many factory paint colors are available and can be specified with Federal Standard or RAL numbers.

For more detailed product information,

FEATURES ĄĄ

Made in the USA

ĄĄ

Most rack accessories ship from stock

ĄĄ

Modified ‘standards’ and customization are our specialty

ĄĄ

Card sizes from 3U x 160mm to 9U x 400mm

ĄĄ

System monitoring option (CMM)

ĄĄ

AC or DC power input

ĄĄ

Power options up to 1,200 watts

please visit www.vectorelect.com or call 1-800-423-5659 and discuss your application with a Vector representative.

vita.opensystemsmedia.com/p371649

Vector Electronics & Technology, Inc. www.vectorelect.com

42 | VITA Technologies Resource Guide Spring/Summer 2016

 inquire@vectorelect.com  800-423-5659

www.vita-technologies.com


VPX6000 Rugged 6U VPX Processor Blade The VPX6000 is a dual-CPU 4th generation Intel® Core™ i7 processor 6U VPX blade (0.85" pitch) with Mobile Intel® QM87 Chipset in a rugged conduction cooled, VPX REDI (VITA 48) form factor. The VPX6000 features two CPU sub-systems, each with up to 16GB DDR3-1600 dual channel ECC memory soldered onboard, and onboard soldered 32GB SLC SATA solid state drive. Rear I/O per node includes 2x 10GbE, 2x 1000BASE-BX and 2x 1000BASE-T, 2x PCIe x1, HD audio (Line-in, Line-out), 3x SATA 6 Gb/s, 2x USB 3.0, 2x USB 2.0, 8x GPIO, HDMI, DVI and RS-232/422. A VPX-R6000 Rear Transition Module (RTM) is available to access rear I/O signals from the VPX6000, and a tBP-VPX6000 Test Backplane supporting three payload slots is available for users to validate VPX6000 functionality. The VPX6000 Series is rugged, conduction-cooled with conformal coating, making it ideal for mission critical applications such as military and aerospace platforms.

ADLINK Technology

http://www.adlinktech.com

FEATURES ĄĄ

Dual quad-core 4th generation Intel® Core™ i7 processors with ECC

ĄĄ

Dual channel DDR3L ECC memory soldered, 16GB per node

ĄĄ

Supports three independent displays

ĄĄ

Supports storage upgrade via mezzanine card

ĄĄ

Offers remote management support

ĄĄ

Conduction-cooled and air-cooled versions available

vita.opensystemsmedia.com/p373452

info@adlinktech.com

 800-966-5200 @ADLINKTech_usa

 www.linkedin.com/company/adlink-technology 

VPX

XMC-G745 Rugged XMC Module ADLINK recognizes the trend towards implementing General Purpose computing on Graphics Processing Units (GPGPU) for parallel computing and increased processing performance, and the XMC-G745M targets a variety of high-performance computing applications that can take advantage of this technology. The rugged XMC-G745M module is equipped with the CUDA-enabled 384-core NVIDIA GeForce GT 745M GPU, utilizing NVIDIA Kepler architecture and yielding unprecedented levels of graphics processing performance for defense and aerospace applications. The GeForce GT 745M features 2048MB of GDDR5 memory, ensuring high-capacity and high-bandwidth access to data during massively parallel GPGPU algorithm processing. The XMC module incorporates the VITA 42.0 XMC switched mezzanine card auxiliary standard and the VITA 46.9 PMC/XMC/Ethernet signal mapping on 3U/6U VPX module standard and supports both Windows and Linux operating systems. The GPU also supports OpenGL 4.4, OpenCL 1.2 and DirectX 11, as well as High-bandwith Digital Content Protection (HDCP).

ADLINK Technology

http://www.adlinktech.com www.vita-technologies.com

FEATURES ĄĄ ĄĄ

NVIDIA GeForce GT 745M GPU (Kepler refresh) CUDA compute capability 3.0 for parallel computation and graphics processing

ĄĄ

Dual channel GDDR5 soldered memory, 2GB

ĄĄ

PCIe x8 Gen3 on P15

ĄĄ ĄĄ

High-resolution, high-performance platform for rugged video I/O and GPGPU applications Ideal for defense, radar, sonar, UAV and ground vehicles vita.opensystemsmedia.com/p373451

info@adlinktech.com

 800-966-5200 @ADLINKTech_usa

 www.linkedin.com/company/adlink-technology 

VITA Technologies Resource Guide Spring/Summer 2016 |

43

VITA Technologiess Resource Guide

VPX


VITA Technologiess Resource Guide

VPX

TR C4x/msd TR C4x/msd is a 3U VPX™ board featuring the Intel® Xeon® Processor D-1500 family and up to 32GB of DDR4 ECC DRAM for high performance embedded computing applications. Concurrent Technologies are supporting variants based on 8, 12 and 16-core processors to suit application profiles. TR C4x/msd has four SATA600 interfaces for external drives plus two SATA600 connections for on-board solid state disk options. For high speed networking applications, two 10 Gigabit Ethernet data plane ports could be used either as a system ingress/egress point or for local data connectivity within the chassis. Two Gigabit Ethernet control plane ports are available on the backplane and two optional Gigabit Ethernet ports are available on the front panel of air cooled boards. TR C4x/msd can also provide up to x16 PCI Express® (PCIe®) lanes on the expansion plane of the backplane with a theoretical bandwidth of 15.6GB/s. These PCIe lanes enable point to point and small mesh configurations for high speed applications without the use of an additional switch module.

FEATURES ĄĄ Intel® Xeon® processor D-1500 Family ĄĄ Up to 32 Gbytes of DDR4 DRAM ĄĄ On-board solid state drive (SSD) options ĄĄ 2 x 10GBASE-KR Data Plane ĄĄ Up to x16 PCI Express® Gen 3 Expansion Plane ĄĄ Air cooled and rugged conduction cooled variants ĄĄ Compliant with VITA 46.11 management vita.opensystemsmedia.com/p373355

Concurrent Technologies

http://www.cct.co.uk/sheets/TR/trc4xmsd.htm

 sales@cct.co.uk  +1 781 933 5900 or +44 1206 752626

VPX

AFT cooled 3U VPX COTS system In support of the new VITA 48.8 Air Flow Through (AFT) cooling standard, Curtiss-Wright Defense Solutions has produced a range of 3U and 6U modules designed to bring the advanced cooling technology to rugged deployed embedded systems. During a presentation at VITA’s Embedded Tech Trends (ETT) 2016 symposium, Curtiss-Wright demonstrated the industry’s first functioning AFT chassis based on commercial-off-the-shelf (COTS) 3U VPX modules. The groundbreaking demo featured a 3D printed plastic chassis integrated with Curtiss-Wright’s VPX3-1258 single board computer (SBC) and VPX3-716 graphics modules, both outfitted with AFT frames. The first modules slated for use in VITA 48.8 AFT systems are Curtiss-Wright’s VPX3-652, VPX3-1259, and VPX3-1258 SBCs and the VPX3-716 graphics module. The combination of advanced cooling, small form factor AFT and reduced weight delivered by VITA 48.8 are of especial benefit for size, weight, power and cost (SWAP-C) constrained platforms such as rotorcraft and unmanned vehicles.

FEATURES ĄĄ

Advanced cooling suitable for the highest power Intel CPU

ĄĄ

Small form factor

ĄĄ

3D printed chassis reduces weight

ĄĄ

Wedgelock-free technology

ĄĄ

Low cost vita.opensystemsmedia.com/p373339

Curtiss-Wright Defense Solutions https://www.curtisswrightds.com

ds@curtisswright.com

 +1.703.779.7800

 www.linkedin.com/company/curtiss-wright-defense-solutions  @curtisswrightds

44 | VITA Technologies Resource Guide Spring/Summer 2016

www.vita-technologies.com


Find out how we can help with your successful VPX designs. OpenVPX Systems

FEATURES

Elma Electronic is the leader in OpenVPX (VITA 65) products and technologies. Our engineering experts developed the industry‘s first VPX backplane, and still actively participate in the VITA standards efforts. Elma has developed a sizable portfolio of backplanes, platforms and embedded computing solutions. OpenVPX defines an easier way to ensure the interoperability between VPX Modules from different vendors, and also compatibility between certain Slot configurations with similar VPX Modules. Elma Electronic‘s comprehensive design approach enables us to meet almost any application challenge. We become an extension of your team, helping to design and select the elements that are best suited to the task. Elma stays involved throughout the process for as long as you need us. This includes design, sourcing, testing and materials management. Open standards-based solutions enable us to offer expert solutions at reduced costs.

ĄĄ

Chassis platforms

ĄĄ

3U & 6U OpenVPX backplanes

ĄĄ

Single board computers (SBCs)

ĄĄ

Ethernet Switches

ĄĄ

High performance FPGA based I/O

ĄĄ

Solid state storage and arrays

ĄĄ

Modular I/O & imaging

ĄĄ

Sub-system design & integration

ĄĄ

Rugged and thermal design & testing

ĄĄ

Lifecycle management

vita.opensystemsmedia.com/p373455

Elma Electronic Inc.

sales@elma.com  510-656-3400  @elma_electronic  https://www.linkedin.com/company/elma-electronic 

http://www.elma.com/en/services/us-resources/architecture-overviews/system-solutions-openvpx-overview/ www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

45

VITA Technologiess Resource Guide

VPX


VITA Technologiess Resource Guide

VPX

6U Universal Development Enclosure

The 6U Universal Chassis/Backplane Assembly provides an ideal, customizable solution for open-standards-based application development. Able to support 6U VPX, VME, CompactPCI, or custom backplanes, the enclosure provides between 2 and 21 slots depending on the specific standard.

FEATURES ĄĄ Form factor: VPX, VME, CompactPCI, Custom ĄĄ Card size: 6U x 160mm ĄĄ Fabric/Profile: BKP6-CEN16-11.2.2-3 (shown) ĄĄ Cooling: Convection, forced air, bottom to top ĄĄ Input power: 85-264 VAC, 1/3 phase, 47-440 Hz

(Optional DC input)

ĄĄ Output power: 5/3.3/±12 V vita.opensystemsmedia.com/p373332

LCR Embedded Systems

www.lcrembeddedsystems.com

sales@lcrembedded.com

 610-278-0840 @LCREmbedded

 www.linkedin.com/company/lcr-embedded-systems-inc- 

VPX

CeeLok FAS-X Connectors TE Connectivity’s CeeLok FAS-X connector combines rugged reliability with signal integrity to support current high-speed protocols and new, faster protocols on the horizon. The new connector features fast field termination and repair, requiring only standard contact insertion/removal and crimping tools. The CeeLok FAS-X connector meets military and aerospace markets’ 10 GB/s requirements and other high-speed protocols such as IEEE 1394b I/O, Fibre channel networks and Modular D38999 for harsh environment applications. Designed for optimal signal integrity, the patented shielding arrangement virtually eliminates crosstalk and completely isolates each pair through the connector to provide improved impedance.

FEATURES ĄĄ Supports 10G Ethernet and other high-speed protocols ĄĄ Patented shielding arrangement shields each pair through the

connector to provide improved impedance matching and to eliminate crosstalk

ĄĄ Uses standard crimp AS39029 contacts ĄĄ Allows fast field termination and repair ĄĄ Available with aluminum or composite shells with a variety of

finishes

ĄĄ Range of inserts for Size 25 shell to accommodate other

connectivity needs

vita.opensystemsmedia.com/p373335

TE Connectivity

www.te.com/highspeed

 1-800-522-6752 www.linkedin.com/company/te-connectivity



46 | VITA Technologies Resource Guide Spring/Summer 2016

 @TEConnectivity www.vita-technologies.com


MULTIGIG RT 2 and MULTIGIG RT 2-R Connectors TE Connectivity’s (TE) portfolio of VPX systems gives you a complete array for high-speed data, optical, RF, power, and mezzanine connectivity. More choice means more flexibility in achieving specific system architectures with standards-based solutions. Get the high-speed signal integrity advanced applications require in rugged, reliable connectors. The MULTIGIG RT 2 connector, the standard for VITA 46, represents a huge step forward in the world of rugged computing and C4ISR enabling technology. MULTIGIG RT 2-R connectors meet application needs beyond VITA 47 environmental performance, while leveraging all the technical and economic benefits of VITA 46 VPX. The modular connector system features a protected backplane connector and uses a pinless backplane and wafer-based design in place of pin contacts. Wafers, available for differential, single-ended, and power needs, can be easily modified to support specific customer needs for characteristic impedance, propagation delay, and other electrical parameters. The connector system also offers built in ESD features enabling field serviceability, is extremely light weight and is fully qualified for VITA 47 environments. MULTIGIG RT, TE Connectivity and TE connectivity (logo) are trademarks. VPX (logo) is a trademark of VITA.

TTI & TE Connectivity

http://www.ttiinc.com/object/te-vpx-clp.html

FEATURES ĄĄ MULTIGIG RT 2 connectors support speeds up to 10 Gb/s, providing

a comfortable performance margin in VPX applications

ĄĄ Differential, single-ended, and power contacts ĄĄ Backplane connector system with “pinless” interface ĄĄ Customizable impedance-matched printed circuit wafer interface ĄĄ Superior crosstalk performance ĄĄ Optimized footprints for signal integrity and ease of board design ĄĄ Ultra-Rugged MULTIGIG RT 2-R Connectors: Quad-Redundant

Contact System rather than the two points of the existing MULTIGIG RT 2 connector. Increasing the points of redundancy increases reliability in a high vibration environment. vita.opensystemsmedia.com/p372976

information@ttiinc.com

 www.linkedin.com/company/7150

 1-800-CALL-TTI @ttiinc.com



XMC/PMC

XU-TX xmc Two 5.1 GSPS 16-bit DACs Xilinx UltraScale The XU-TX – an XMC module featuring two, AC-coupled, single-ended 16-bit DAC outputs with programmable DC bias. The DAC devices employed support synchronization and interpolation and their unique output circuits allow improved frequency synthesis in the 2nd and 3rd Nyquist zones, to shift of the Nyquist null frequency in the output spectrum by a factor of two. The DAC ICs may be clocked at up to 5.1 GHz via an onboard, ultra-low-jitter PLL. A unique feature of the PLL guarantees multi-board synchronization when supplied a 1/16th-rate external reference and trigger.

FEATURES

Sixteen high-speed serial links connect to the host (eight via XMC connector J15, and eight via J16). 8000 MB/s PCIe gen3 and Aurora protocols, respectively are supported.

ĄĄ Two 16-bit, > 5.1 GSPS DAC channels

A Xilinx Kintex UltraScale XCVU060/085 FPGA lies at the heart of the product, supported with 8 GB DDR4 and 4 MB of QDRAM memory, providing a very high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog I/O, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 7000 GMAC/s.

ĄĄ Up to 7800 MB/s streaming via PCIe or Aurora

Applications include: High Speed Arbitrary Wave Generation, Wireless MIMO transmitter, RADAR Waveforms, and Electronic Warfare.

Download data sheets now!

Innovative Integration

www.innovative-dsp.com www.vita-technologies.com

ĄĄ Enhanced 2nd and 3rd Nyquist modes ĄĄ Internal or external clocking ĄĄ Internal or external triggering ĄĄ Xilinx Kintex UltraScale FPGA XCKU060/085: ĄĄ 4 GB DDR4 DRAM in 2 banks each with 64 bit interface & up to

38.4GB/s total bandwidth

vita.opensystemsmedia.com/p373376

sales@innovative-dsp.com  805-383-8994 

VITA Technologies Resource Guide Spring/Summer 2016 |

47

VITA Technologiess Resource Guide

VPX


Got Tough Software Radio Design Challenges?

Unleash The New Virtex-7 Onyx Boards! Pentek’s Onyx® Virtex-7 FPGA boards deliver unprecedented levels of performance in wideband communications, SIGINT, radar and beamforming. These high-speed, multichannel modules include: • A/D sampling rates from 10 MHz to 3.6 GHz • D/A sampling rates up to 1.25 GHz • Multi-bandwidth DUCs & DDCs • Gen3 PCIe with peak speeds to 8 GB/sec • 4 GB SDRAM for capture & delay • Intelligent chaining DMA engines • Multichannel, multiboard synchronization ® • ReadyFlow Board Support Libraries ® • GateFlow FPGA Design Kit & Installed IP ® • GateXpress FPGA - PCIe configuration manager • OpenVPX, AMC, XMC, PCIe, cPCI, rugged, conduction cooled • Pre-configured development system for PCIe • Complete documentation & lifetime support

With more than twice the resources of previous Virtex generations plus advanced power reduction techniques, the Virtex-7 family delivers the industry’s most advanced FPGA technology. Call 201-818-5900 or go to www.pentek.com/go/vitaonyx for your FREE online Putting FPGAs to Work in Software Radio Handbook and Onyx product catalog.

Pentek, Inc., One Park Way, Upper Saddle River, NJ 07458 • Phone: 201.818.5900 • Fax: 201.818.5904 • e-mail:info@pentek.com • www.pentek.com Worldwide Distribution & Support, Copyright © 2013 Pentek, Inc. Pentek, Onyx, ReadyFlow, GateFlow & GateXpress are trademarks of Pentek, Inc. Other trademarks are properties of their respective owners.

Profile for OpenSystems Media

VITA Technologies Spring/Summer 2016 with Resource Guide  

VITA Technologies Spring/Summer 2016, 2016 Resource Guide, MORA – Modular Open Radio Frequency Architecture Boot Camp, FMC+ New Heights in I...

VITA Technologies Spring/Summer 2016 with Resource Guide  

VITA Technologies Spring/Summer 2016, 2016 Resource Guide, MORA – Modular Open Radio Frequency Architecture Boot Camp, FMC+ New Heights in I...