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to compensate for skew across serializer/ deserializer (SERDES) lanes, which simplifies board layout. This elastic buffer stores the data until the data from the slowest lane arrives. It then releases the data from all lanes simultaneously for digital processing. This skew management is possible because the data clock is embedded in the serial data stream. While the JESD204B standard has simplified multichannel synchronization by using deterministic latency, minimal latency is needed in some applications such as electronic warfare (EW) and radar applications where actions are required immediately after detection. For these applications, the LVDS interface should still be considered, as the JESD204Bcompliant data converter’s delay in serializing the data is omitted. However, applications such as radar warning receivers (RWR) or COMINT that are receiver-only applications tolerate the latency brought on by the JESD204B serialization. These applications thus can benefit from the last generations of ADCs driven by the mass market of telecommunication infrastructure, allowing very high-speed sampling and reducing the complexity of the analog part of the system.

The FMC standard defines a small format mezzanine, similar in width and height to XMCs or PMCs, but around half the length. As real estate is limited, some features have been included in the standard. First, to save space, its primary power is supplied by the FPGA carrier board. During the power-up sequence, the host interrogates the FMC as to what the feeding voltage must be. In addition, FMCs directly connect the I/O devices on the mezzanine to the host FPGA via a high-speed, highdensity connector as if the device was on the host itself, leading to logic reduction and saved space. The first generation of the FMC standard allows up to 160 for high-pin-count (HPC) or 80 for low-pin-count (LPC) “parallel” I/O signals and up to 10 full-duplex highspeed serial connections (along with some clocks). Figures 1 and 2 shown on page 16 depict an Interface Concept ADC FMC, the IC-ADC-FMC, which can be plugged on a Virtex-7 FPGA carrier board, the IC-FEP-VPX3c, featuring eight high-speed transceivers in front of the mezzanine’s high-speed serial (HSS) links.

FPGA vendors have developed fully compliant JESD204B intellectual property (IP) that can be implemented in their products for communication with the serial ADCs. For example, the JESD204B Xilinx IP supports 256 bytes per frame and 32 frames per multiframe. It can be configured to support up to 32 lanes.

Flexible design follows the fast moving market of ADCs In combining the technologies available on ADCs including the new JESD204B standard and FPGAs, EW system architects can dramatically improve data sample processing. FMC (VITA 57 standard), promoted by the VITA FMC Marketing Alliance, allows high data throughput and very low latency response between an ADC or a digital-to-analog converter (DAC) FMC and the FPGA, simplification of the design, and above all, the cost-efficient ability to simply retarget an FPGA carrier card design. All that is required is swapping out the FMC module and adjusting the FPGA firmware. That is why the standard has become the open standard mezzanine of choice. www.vita-technologies.com

VITA Technologies Resource Guide Spring/Summer 2016 |

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