MEPTEC Report Winter 2018 by MEPTEC

315 Savannah River Dr., Summerville, SC 29485 Tel: (650) 714-1570 Email: bcooper@meptec.org

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 22, Number 4

The 2019 MEPTEC/SMTA Medical Electronics Symposium, “The Body Electric”, is a two-day event to be held on Tuesday and Wednesday, May 21st and 22nd at Lorain County Community College in Elyria, Ohio. This event will bring together experts to cover topics such as: Forecasting and Analytics, MEMS, Sensors and Integrated Circuits, Implantable Devices and Neural Interface, Medical Robotics, Equipment, and Prosthetics, Packaging and Board Level Assembly, Advanced Materials and Reliability. (see page 11)

THE BODY ELECTRIC

2019 Medical Electronics Symposium May 21 & 22, 2019

MEPTEC Advisory Board

Lorain County Community College, Elyria, Ohio

page 11

Board Members Ivor Barber AMD Jack Belani Indium Corporation Joel Camarda Altierre

DARPA’s CHIPS Program for IP Reuse and Heterogeneous Integration page 15 Packaging & Assembly for High-Temperature Electronics Part I – Devices and Materials page 19

Tufts University researchers have developed a “smart” bandage that will actively monitor the condition of wounds and deliver drug treatments to improve healing. The bioelectronics bandage features integrated pH and temperatures sensors that electronically trigger drug release when it senses that wounds are not healing properly.

page 28 -Corp.

INSIDE THIS ISSUE

12 24 SoC Silicon and Software 2018 Design Cost Analysis

ISO 9001 is viewed by most people as the minimum table stakes of good business practice.

Ensuring the reliability of package designs has become essential to long-term performance.

Volume 22, Number 4

ON THE COVER

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Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

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The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council

Advancements in “connected” medical electronics are revolutionizing the health care industry.

Jeff Demmin Booz Allen Hamilton Douglass Dixon Henkel Corporation Nick Leonardi SMART Microsystems Phil Marcoux PPM Associates Gamal Refai-Ahmed Xilinx Herb Reiter eda 2 asic Consulting Rich Rice ASE (US) Inc. Scott Sikorski STATS ChipPAC Jim Walker WLP Concepts Special Advisors Ron Jones N-Able Group International Mary Olsson Gary Smith EDA Honorary Advisors Seth Alavi Sunsil Gary Catlin Rob Cole Skip Fehr Anna Gualtieri Elle Technology Marc Papageorge ICINTEK In Memoriam Bance Hom

ANALYSIS – Silicon designers and system architects are constantly looking for ways to reduce their design costs and still meet market requirements and ASP targets. This article references data and analysis from Semico’s report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, SC103-18. RICH WAWRZYNIAK PRINCIPAL ANALYST: ASIC & SOC, SEMICO

INTEGRATION technologies are integrated. With a standard CHIPS interface for heterogeneous integration, IP reuse is enabled at the chiplet level. Heterogeneous design will become essentially the same as monolithic design, with the knowledge that IP blocks can be integrated successfully. Finally, a modular design paradigm is needed to enable designers to take full advantage of interface standards and heterogeneous IP reuse. Design tools and process design kits (PDKs) will account for different device technologies and their integration, with the appropriate design, simulation, and analysis capabilities in place. CHIPS Program Structure The CHIPS program is structured in two Technical Areas (TAs) – Modular Digital Systems (TA1) and Supporting Technologies (TA3). System performers are Intel, Lockheed Martin, Northrop Grumman, and the University of Michigan. Each of the System performers is designing a system using the CHIPS approach, and the teams are also collaborating to specify and implement an interface standard. Since convergence on the interface standard is required before designs can be finalized, this was the first major milestone in the CHIPS program. The Supporting Technologies performers are providing IP blocks and design tools that will be used by the system designers, although the IP blocks and design tools will be developed with broader usage in mind. Performers developing design tools are Georgia Tech and Cadence, while IP blocks are being developed by Intrinsix, Jariet Technologies, Micron Technology, North Carolina State University, and Synopsys. The system designers will also be providing IP blocks. To ensure successful integration, the CHIPS program is also pursuing multiple integration strategies. The first will be a leading edge but broadly available industry standard interconnect on a silicon interposer, while at least one other approach with much finer pitch will be developed in parallel for Phase 2 of the four-year program. CHIPS Interface Standard The performers in the CHIPS program have agreed to base the CHIPS 16 MEPTEC REPORT

Figure 1. The basic AIB I/O cell (left) and clock forwarding architecture (right). (Source: Intel)

interface standard on Intel’s Advanced Interface Bus (AIB) standard. This was enabled by Intel offering a paid-up, royalty-free license for the relevant IP and documentation. After extensive discussion and debate among the CHIPS performers, AIB was chosen as the basis for the CHIPS interface. The key factors in that decision were: 1) performance metrics that meet the CHIPS requirements, 2) the flexibility to meet a range of applications, with CHIPS-specific “lite” and “turbo” options, for example, and 3) silicon-proven maturity based on Intel’s use of AIB. The I/O cell and details of the clock forwarding architecture are shown in Figure 1. Chiplets, IP Reuse, and Design The success of the CHIPS program depends on creating a set of IP blocks with numerous applications, since a key

Table II. Chiplets in Process for CHIPS Phase 1 or Proposed for Phase 2.

part of the CHIPS premise is reuse of common IP blocks. The CHIPS program has selected several performers to provide IP blocks for the program, whether for their own system demonstrations or for use by others in the program. Chiplets currently being designed and manufactured in Phase 1 and those under consideration for Phase 2 are summarized in Table II. The chiplet sizes range from approximately 0.5mm2 to 15mm2, with most being 1-4mm2. Plans for chiplet fabrication include leveraging multi-project wafer (MPW) runs at GlobalFoundries (14nm, 32nm, and 65nm) and TSMC (16nm node via DARPA’s CRAFT program). Design tools for a vertically-integrated design flow for IP reuse and heterogeneous integration are under development by Georgia Tech. That team’s tasks include protocol implementation, analysis of chiplet options, interposer routing analysis, and power delivery network analysis. A sample analysis indicates a 33% reduction in power with an integrated voltage regulator chiplet, and the voltage response in that scenario is shown in Figure 2. Cadence Design Systems is contributing to the CHIPS design environment by creating models of different interconnect schemes and verifying them with measurements performed by NIST. Their studies are covering organic and silicon interposer options. Modular Design and Applications The pieces of the CHIPS program are being brought together in a phased sequence of demonstrations: interface functionality (Phase 1), modular systems (Phase 2), and rapid modular system

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upgrade (Phase 3). A number of teams are developing systems with the CHIPS approach. Intel is developing a platform based on its Stratix-10 FPGA (Figure 3), which enables a wide range of applications, including those that leverage machine learning. The CHIPS interface based on Intel’s AIB is used to connect the FPGA to various chiplets (e.g., data converters, ASICs, processors, and analog functions), and memory can be integrated with other standard interfaces. The CHIPS team at the University of Michigan has made rapid progress with its first set of chiplets being taped out in April 2018 for a 16nm MPW run at TSMC via DARPA’s CRAFT (Circuit Realization at Faster Timescales) program. This includes a deep neural network (DNN) accelerator and neuro-coding chiplets for visual processing applications, as well as the first CHIPS instantiation of the AIB-based interface (Figure 4). Lockheed Martin Advanced Technology Laboratories has proposed an application that addresses a spectrum of common DoD challenges [10]. Along with the inherent cost reduction of decreasing the total design and manufacturing effort required for system upgrades, the CHIPS approach improves reliability, qualification cost and time, and diminishing manufacturing sources (DMS) challenges. With a modular electronics sub-system based on IP reuse and standard interfaces, it is possible to swap in just the components that need an upgrade, thus preventing a total overhaul of the system to retain leadingedge performance. This is particularly critical for applications with life cycles measured in decades, such as aircraft. Lockheed is pursuing this approach in a network interface unit in a major avionics platform. Northrop Grumman Mission Systems (NGMS) is also pursuing CHIPS-based systems for defense applications and has identified digital transceivers as an application that could benefit from a chipletbased approach. By separating the SoC into separate functions, it is possible to optimize the device node and even the foundry source [11]. For this application, a key enabling technology for SoC disaggregation is sub-10µm interconnect pitch, and NGMS is working with Micross to develop this.

Core chiplet IVR chiplet

Passive chiplet

IVR

L, C

LDO

0.8

0.4 0.2 0

PCB

Droop

0.6

interposer package

Interposer VR

DC drop

VOUT

Settling time

ΔIL 1.9

1.95

2.05

2.1

2.15

Time (µs)

2.2

2.25

2.3

2.35

Figure 2. Georgia Tech’s design tools enable analysis of chiplet integrated voltage regulator performance, among many other features. (Source: Georgia Tech)

Figure 3. Intel’s CHIPS application platform is based on its Stratix-10 FPGA. (Source: Intel)

Figure 4. Michigan’s initial set of chiplets were taped out in April 2018 for a 16nm CMOS MPW foundry run and included an AIB test chip. (Source: U. of Michigan)

Manufacturing and Supply Chain Early in the CHIPS program, the performers settled on 55µm Cu pillar interconnect as the primary path, since this represents the finest pitch interconnect that has an established supply chain and user base. As the first step in the CHIPS program, it is a convenient compromise using leadingedge but broadly available technology.

In parallel, two CHIPS teams are developing alternative interconnect approaches with much finer pitch interconnect to extend the CHIPS roadmap well into the future. Micross and NGMS are collaborating on ultra-fine-pitch interconnect, which NGMS has shown to be a critical enabler for their target applications. Micross has demonstrated both Cu WINTER 2018 MEPTEC REPORT 17

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William Boyce SMART Microsystems Ltd. Jeffrey Demmin Booz Allen Hamilton Ira Feldman Feldman Engineering Corp.

State-of-the-Art Technology Briefs

organization. This means that the executive level manager in the organization can no longer just push the requirements on to the quality representative, they must be engaged. This approach fosters a top down effect that demonstrates to everyone in the organization that the top management is quality centric, and has real buy-in. I think that we can all agree that this is good for any organization. When most people that have been in business for some time think of ISO compliance, they think of a lot of meaningless paperwork and painful audits. But this is quite simply not the case, because the current ISO compliance does

William Boyce is the Engineering Manager at SMART Microsystems. He has served in senior engineering roles over the last 19 years with accomplishments that include manufactured automotive sensors. He is certified in EIT and Six Sigma Green Belt and is an industry recognized expert in Al wire bonding. Additionally, he designed and led the metrology lab and machine shop at Sensata. Mr. Boyce earned a Bachelor of Science in Engineering degree from the University of Rhode Island and has been a member of the IMAPS New England Chapter for over 10 years.

The SMART Advantage. Lowest Overall Development Time and Cost.

Rose Guino Henkel Electronic Materials LLC Ron Jones N-Able Group International

Custom Prototype and Process Development

Custom Environmental Life Test and Failure Analysis

ISO9001:2015 C E R T I F I E D

Custom Manufacturing Services

DEVELOPMENT, TESTING, AND MANUFACTURING OF UNIQUE CUSTOMER-DESIGNED PRODUCTS

26 MEPTEC REPORT WINTER 2018

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A special feature courtesy of Binghamton University We are pleased to continue this feature in the MEPTEC Report, brought to us by new Advisory Board member Dr. Gamal RafaiAhmed from Xilinx. The State-of-the-Art Technology Briefs contains articles from the Binghamton University S3IP “Flashes.” Full text is available upon request through the IEEC Site at: http://www.binghamton.edu/s3ip/index.html.

Additive 3-D printing manufacturing can be used to manufacture porous electrodes for lithium-ion batteries. However, because of manufacturing process limitations the design of these 3-D printed electrodes is limited to only a few architectures. Carnegie Mellon University researchers have developed a revolutionary new method of 3-D printing battery electrodes that creates a 3-D microlattice structure with controlled porosity. This structure used as batteries’ electrodes can improve battery performance with a fourfold increase in specific capacity and a twofold increase in areal capacity when compared to a solid block electrode. (IEEC file #10749, EIN 007, 8/1/18) Harvard University researchers have developed a new printing method that uses sound waves to generate droplets from liquids with a large range of composition and viscosity. This technique could enable the manufacturing of new biopharmaceuticals, cosmetics, and food, and expand optical and conductive materials applications. The use of acoustic forces enables myriad materials to be printed in a drop-on-demand manner. The researchers built a subwavelength acoustic resonator that can generate a highly confined acoustic field resulting in a pulling force exceeding 100 times the meptec.org

Dr. Randall K. Kirschman R&D Consultant

normal gravitation forces at the tip of the printer. (IEEC file #10793, Printed Electronics World, 9/11/18) University of Delaware engineers are developing the next-generation smart textiles. Their approach is an application of flexible carbon nanotube composites coatings on a series of fibers, such as nylon, cotton, and wool. Fabric suited with this sensing technology can lead the charge toward future “smart garments.” The carbon nanofibers release electrical changes in the fabric when squeezed. The coatings measure a large range of pressures. The nanocomposite coatings “are created on the fibers using electrophoretic deposition (EPD) of polyethyleneimine functionalized carbon nanotubes. (IEEC file #10768, Design News, 8/16/18)

University of Illinois researchers found that by “sandwiching” two-dimensional (2D) materials used in nanoelectronic devices between their three-dimensional silicon bases and an ultrathin layer of aluminum oxide they can significantly reduce the risk of component failure due to overheating. Many silicon-based electronic components contain 2D materials (such as graphene), hence incorporating 2D materials into components allows them to be several orders of magnitude smaller than if they were made with conventional, 3D materials. (IEEC file #10792, R&D, 9/12/18) A new method to 3D print lithium-ion batteries in virtually any shape has been developed by Duke University researchers. Electric vehicles and most electronic devices, such as cell phones and laptop computers, are powered by lithium-ion batteries. Until now, manufacturers have had

to design their devices around the size and shape of commercially available batteries. To print the lithium-ion batteries with a 3D printer, the researchers increased the ionic conductivity of PLA (polylactic acid) by infusing it with an electrolyte solution. In addition, they boosted the battery’s electrical conductivity by incorporating graphene or multi-walled carbon nanotubes into the anode or cathode, respectively. (IEEC file #10865, Science Daily, 10/17/18)

Chinese researchers have developed a hybrid conductive material that is part elastic polymer and part liquid metal. Circuits made with this material can take on most two-dimensional shapes, are highly conductive, stretchable, fully biocompatible and able to be fabricated conveniently across all size scales with micro-feature precision. This will have broad applications for both wearable electronics and implantable devices. (IEEC file #10803, US Tech, 9/14/18) RMIT University researchers have developed an option for scalable quantum computers using a topological photonic chip to process quantum information. The team demonstrated that quantum information can be encoded, processed and transferred at a distance with topological circuits on the chip. The new chip design will open the way to studying quantum effects in topological materials and to a new area of topologically robust quantum processing in integrated photonics technology. The breakthrough could lead to the development of new materials, new generation computers, and a better understanding of fundamental science. (IEEC file #10801, R&D, 9/14/18) WINTER 2018 MEPTEC REPORT 27

Design Complexity Levels Within each process geometry, there are differing levels of effort that directly relate to how expensive a particular design start is. These complexity levels are driven by several factors: • Gate count • Transistor budget • Architecture • Compute resources • Communications channels • Number and type of IP blocks • Feature sets and functionality dictated by market requirements • Software complexity

Advanced Performance Multicore SoC 1st Time Design Starts by Design Effort

Source: Semico Research Corp.

* Forecast

While software is not included in Semico’s analysis as a direct design cost, it does have a significant impact on the overall silicon architecture created to run that software. One of the major reasons for increasing design cost is the complexity of the software intended to run on the silicon and the architecture necessary to run these software applications efficiently and with good performance. As the software applications have become more feature rich, the silicon must also adapt to accommodate this rising complexity and the increase in the number of lines of code being run. With these thoughts in mind, the costs for each type of SoC are subdivided into different levels of effort to reflect that not all designs must function at the highest possible performance or functionality to be competitive in the market. Semico analyzes design activity based on a variety of different market segments and has created a model to gauge the impact of rising design costs on SoC design starts. Following is a review of the three categories of SoCs: Advanced Performance

Basic SoC 1st Time Design Starts by Design Effort

Multicore SoC, Value Multicore SoC and Basic SoC. The Advanced Performance Multicore SoC design starts represent the most complex and expensive designs at the beginning of each process node. Over the forecast period, the average silicon design cost for an Advanced Performance Multicore SoC will increase as designs become more complex and the effort to accomplish them increases. Silicon design costs for a first-time Advanced Performance Multicore SoC at the 7nm node are projected to be 23% higher than at the 10nm node. The increase in cost hasn’t pevented the released of new designs because there are a range of design costs which indicate differing levels of effort and complexity. A higher complexity part would require more tools, more IP, more people to complete and would take longer to accomplish than would a part with less complexity. As the number of design starts transition from older nodes to newer nodes, with their higher associated costs, the

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Source: Semico Research Corp.

* Forecast

average design cost for all Advanced Performance Multicore SoCs increases over the forecast period. However, since activity continues at the older nodes, the average design cost is not increasing as fast as the overall silicon design costs for this type of SoC at the most advanced nodes. The CAGR for average design costs for an Advanced Performance Multicore SoC is 2.5% for the period 2017 – 2023. The number of Value Multicore SoC design starts is almost double compared to the Advanced Performance Multicore SoC design starts. This is due to the fact that the Value designs are easier to accomplish, cost less and take less time to finish. This can give an advantage to companies that do not need to offer the most complex solution to their customers yet want to participate in their market with acceptable solutions that meet market requirements. The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017. Over the forecast period, the average silicon design cost

for a Value Multicore SoC will increase as designs become more complex and the effort to accomplish them increases. The fastest growing category as it relates to new designs is the Basic SoC. Basic SoC designs represent the least complex and least expensive efforts at the beginning of each process node. These design costs continue to decline over time as more designs are created, more expertise is gained, the costs of EDA tools decline over time and the reuse of IP increases. Removing derivative designs and respins shows that the number of 1st time efforts for Basic SoCs is growing the fastest of the three SoC types with a CAGR of 12.0% over the forecast period. An interesting note to the Basic SoC category is that many of these designs will be targeted at Internet of Things (IoT) applications. Semico believes that there will be a segment of these applications that will require higher functionality and will be a candidate for 28nm solutions over time. The total number of designs at 28nm starts out small

but increases over time. These designs will cost more and are responsible for the increase in average costs starting in 2014. Thereafter, these costs still increase but at a slower rate. This is also the reason for the large number of Basic SoC designs and the higher CAGR for these designs. They are coming from a relatively small base starting in 2008, but ramp quickly driven by IoT demand for lower cost solutions and reasonable functionality. Unlike Advanced Performance Multicore and Value Multicore SoCs, Basic SoCs see lower amounts of design activity below 28nm over the forecast period. Currently, this is due to the end applications for which Basic SoCs are used. These applications do not need the same complexity levels as the other two types of SoC. This will especially be true for Basic SoCs aimed at IoT solutions. These parts simply don’t need high complexity and their design costs are correspondingly lower, leading to a lower average design cost overall. In general, Semico believes that although design costs for complex SoCs have increased, and that re-spins and long design cycle times are not optimum conditions for the SoC market, their effect on market growth has not been overly detrimental. New, more efficient tool sets from EDA companies and semiconductor intellectual property blocks from 3rd party IP companies, make designers more productive and are well received by the market. Companies with innovative solutions are targeting the appropriate market application and are the main reason why design starts continue to grow. For more information on SoC design costs and SoC design starts by market application, contact Rick Vogelei at rickv@semico.com. ◆

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INTEGRATION – The path to higher performance requires a broader set of feasible device technology options. DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will address these challenges by developing interface standards, IP reuse methodologies, and modular design approaches. JEFFREY DEMMIN, BOOZ ALLEN HAMILTON ANDREAS OLOFSSON, DARPA

DR. RANDALL K. KIRSCHMAN R&D CONSULTANT FOR ELECTRONICS TECHNOLOGY

not dictate the method you use, only the results. Having just completed our annual registration reassessment audit with no findings, we often get the question “how do you do that?”. The answer is actually quite simple. As a microelectronics assembly business, we were ISO compliant long before we achieved ISO registration. In fact, internally as an organization, our audits are a non-event because nothing changes and no special preparation is required by the staff. We simply keep doing those things we have been doing all along. So, if your organization is doing all of the things that are required to be a good and customer focused business, you are already ISO compliant, so why not get credit for it and achieve registration. At SMART we use ISO registered suppliers, and we love to have ISO registered customers. For more information about SMART services visit smartmicrosystems.com. ◆

THE RISE IN SILICON AND software design costs has impacted and influenced design activity in the semiconductor industry and is shaping company strategies and the decisions designers are making as it relates to number and type of designs. While it is true that SoCs with the highest design costs probably contain the most complexity, it does not necessarily follow that every product in a given geometry must also incur the same high costs to be competitive. Silicon designers and system architects are constantly looking for ways to reduce their design costs and still meet market requirements and ASP targets. This article references data and analysis from Semico’s report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, SC103-18.

improve. In our case, we conduct regular quality training of the entire staff to continuously improve our implementation of the QMS. We also perform regularly scheduled reviews of our processes and customer feedback at our scheduled management review meetings. Evidence-based decision making is a process like any other. It takes a certain level of organizational discipline to establish and maintain the process. There are a lot of tools that are available to facilitate the effort, like DFMEA, PFMEA, SPC, design reviews, and DOE. We use all of these tools and some others, on a regular basis, to bring quantitative data to the decision making process. The microelectronics assembly business is a very technical and detail oriented business, so tools like a FMEA and DOE are a natural fit. Over time, these tools have become a staple of our business, it just so happens that they also fit the ISO evidence based decision making model. Leadership, engagement of people, and relationship management are all basic requirements of good and effective leadership in any business. In the new ISO 9001 standard there is a very real focus on the engagement of management. In fact, the quality representative position in an organization has been eliminated in the new standard. This is driving action and engagement to higher levels in the

Rich Wawrzyniak Principal Analyst: ASIC & SoC, Semico

12 MEPTEC REPORT

PACKAGING – For more efficient use of resources, and to reduce energy waste and pollution, electronics must be extended into new areas. A key area is operation beyond the present “standard” or “military” temperature range of −55°C to +125°C. Power systems for electric vehicles and airplanes could be more efficient using high-temperature electronics (HTE).

TECH BRIEFS

Contributors

ANALYSIS

Impact of Rising Design Costs on SoC Design Starts

PACKAGING

INTEGRATION

Figure 5. Micross has demonstrated bonding on test structures at 5µm Cu/Cu pitch (left) and 10µm Au/Au pitch (right). (Source: Micross)

Figure 6. UCLA is developing an interconnect scheme that leverages silicon wafers as the substrate (left) with 10µm and below pitch Cu interconnections. (Source: UCLA)

and Au metallurgies for 10µm and below pitch (Figure 5) with non-collapsible bumps [12]. A team at UCLA is also developing sub-10µm interconnect for CHIPS. They have demonstrated Au-capped Cu pillar interconnect at 10µm pitch (Figure 6) and have roadmap options to eliminate the Au cap and decrease the pitch further. A novel part of UCLA’s approach is the use of a silicon wafer as the substrate. This Silicon Interconnect Fabric (Si-IF) provides performance and mechanical advantages, and UCLA is developing system-level approaches for integrating the Si-IF. The interconnect strategy is a critical part of the CHIPS eco-system. Along with the technical capabilities for finepitch interconnect, there also needs to be access to foundries, MPW runs, volume assembly, PDKs, and other critical supply chain capabilities. DARPA is paving the way for some of this, but the eco-system also needs industry support that arises from the market potential of the CHIPS approach. In parallel, business models that fill new needs in the

CHIPS eco-system are being explored. For example, silicon IP companies are pursuing the option of becoming chiplet suppliers. Instead of just providing soft or even hard IP, they will sell verified chiplets ready for assembly. This is one example of the innovation brought by the CHIPS approach to the semiconductor marketplace. Conclusion DARPA’s CHIPS program aims to serve as the necessary piece of the puzzle that lets heterogeneous integration gain momentum in the marketplace by leveraging proven approaches of the semiconductor industry. With advantages for both defense and commercial applications, a critical mass of CHIPS adopters is expected. The industry has recognized the great challenges before us in IEEE’s newly revamped International Roadmap for Devices and Systems [13], and an important step was made when the IEEE, SEMI, and ASME jointly established the Heterogeneous Integration Roadmap[14] in recognition of the importance of het-

18 MEPTEC REPORT WINTER 2018

erogeneous integration to the solution set for these upcoming challenges. In this spirit, DARPA has been at the forefront of heterogeneous integration for many years and is now focused on enabling the traction needed to drive broad adoption via the CHIPS program. ◆

Packaging & Assembly for High-Temperature Electronics

References

Dr. Randall K. Kirschman R&D Consultant for Electronics Technology

[1]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “Heterogeneous Integration for Revolutionary Microwave Circuits at DARPA,” Microwave Journal, June 2015, pp. 22-38.

[2]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “A Revolution on the Horizon from DARPA,” IEEE Microwave Magazine, March/April 2017, pp. 44-59.

[3]

www.darpa.mil/Our_Work/MTO/Programs/ DAHI/DAHI_Foundry_Technology.asp.

[4]

D. Scott, et al., “Diverse Accessible Heterogeneous Integration (DAHI) Foundry Establishment at Northrop Grumman Aerospace Systems (NGAS),” Proc. IPRM, Santa Barbara, 2015.

[5]

Y.-C. Wu, et al., “InP HBT/GaN HEMT/ Si CMOS Heterogeneous Integrated Q-Band VCO-Amplifier Chain,” Proc. IPRM, Santa Barbara, 2015.

[6]

Andrew Carter et al., “Wafer-Scale InP/Si CMOS 3D Integration Using Low-Temperature Oxide Bonding.” Compound Semiconductor Week, 2015.

[7]

Lawrence J. Kushner et al., “A 30 GS/s, 12-bit, 8-Vpp, Arbitrary Waveform Generator with Integrated 25 fs Clock in the DARPA DAHI Process.” GOMAC 2016.

[8]

D. Green, “DARPA’s CHIPS Program and Making Heterogeneous Integration Common,” 3D ASIP, December 2017.

[9]

D. Green et al., “Heterogeneous Integration at DARPA: Pathfinding and Progress in Assembly Approaches,” ECTC, May 2018.

[10] R. Stevens et al., “An Application Specific IP (ASIP) Approach Offers a Design Solution Between ASICs and FPGA,” 3D ASIP, December 2017. [11] P. Borodulin et al., “Disaggregation of Advanced Node SoCs into 2.5D Modular Architectures for Rapid IP Reuse,” 3D ASIP, December 2017. [12] M. Lueck et al., “High Density Interconnect Bonding at 10µm Pitch and Below Using Non-Collapsible Microbumps,” 3D ASIP, December 2017. [13] “International Roadmap for Devices and Systems,” irds.ieee.org/roadmap-2017. [14] “Heterogeneous Integration Roadmap,” eps.ieee.org/technology/heterogeneousintegration-roadmap.html .

meptec.org

Part I – Devices and Materials

FOR MORE EFFICIENT USE OF resources, and to reduce energy waste and pollution, electronics must be extended into new areas. A key area is operation beyond the present “standard” or “military” temperature range of −55°C to +125°C. Power systems for electric vehicles and airplanes could be more efficient using high-temperature electronics (HTE), capable of operation at environmental temperatures from 200°C to 500°C or beyond.* Closely related is the move toward “distributed systems”: placing more of a system’s electronics close to sensors and actuators to enhance performance (Figure 1). High-temperature electronics is needed because these sensors and actuators are often in high-temperature environments. Additional applications—with an inherent high-temperature environment— include spacecraft, electric-generating plants, and petroleum and geothermal wells[1][2]. For a high-temperature application, operating electronics within the “standard” temperature range exacts a substantial toll in size, weight, power, and system complexity and efficiency. To keep electronics below +125°C, either (a) the electronics must be located in a “standardtemperature” ambient, which is likely remote from where it needs to be for best system performance, or (b) a cooling or refrigeration system, with its associated issues, must be employed. How does electronics extend its operational temperature range upward? Assembly and packaging technology has a major role. It must provide an electroniccomponent-friendly environment—thermal, electrical and mechanical—while not compromising the component’s intrinsic

Figure.1 The idea of a distributed system. (*Aircraft or auto engine, oil well, hot planet, …)

performance. In other words, an extension of the same requirements as for “standard” temperatures [3]. This brief article cannot go into details, but will touch on a few of the major points. Moving to higher temperatures requires assembly and packaging based on (a) materials that can survive and are stable, (b) designs and techniques that prevent interactions among the materials, and (c) processes that are compatible with the materials and electronic components. Extending the thermal, electrical and mechanical design presents an extra challenge because many materials characteristics are strongly temperature dependent, more so as temperature increases. Furthermore, there are nearly always additional environmental stresses to be considered: EMI, magnetic fields, chemicals, dirt, shock/vibration, or radiation. A basic requirement for any electronic system is suitable semiconductor devices (diodes and transistors). Thus, a first question is what are the high-temperature capabilities of semiconductor materials and devices?

Semiconductors Silicon is the mainstay, and a range of Si ICs rated up to ≈ 200–225°C is commercially available (Figure 2); a few can be used to even higher temperatures if derated. Also, SiGe ICs are appearing commercially, rated up to 250°C. Although Si devices have been operated to over 400°C [4], a practical limit for Si is about 300°C for non-power circuits and about 200°C for power circuits. To go beyond the extended-temperature capabilities of Si, the frontrunners are silicon carbide (SiC) [5], gallium nitride (GaN), and diamond (C) [6]. These

Figure 2. Si COTS ICs rated at 175°C (left, V reference) and 210°C (right, 8-ch MUX) (note difference in packaging, plastic vs ceramic). Photos courtesy Analog Devices.

* Unless noted otherwise, all temperatures in this article are environmental/ambient temperatures. meptec.org

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TECH BRIEFS – The State-of-the-Art Technology Briefs contains articles from the Binghamton University S3IP “Flashes.” Binghamton University currently has research thrusts in healthcare/medical electronics; 2.5D/3D packaging; power electronics; cybersecure hw/sw systems; photonics; MEMS; and next generation networks, computers and communications. DR. GAMAL RAFAI-AHMED XILINX

Nicholas Leonardi SMART Microsystems Ltd. Andreas Olofsson DARPA Dr. Gamal Rafai-Ahmed Xilinx

DEPARTMENTS

8 Coupling & Crosstalk 10 Industry Insights

24 SMART Microsystems News 30 Henkel News

34 Opinion

Rich Wawrzyniak Semico

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