INTEGRATION erogeneous integration to the solution set for these upcoming challenges. In this spirit, DARPA has been at the forefront of heterogeneous integration for many years and is now focused on enabling the traction needed to drive broad adoption via the CHIPS program. ◆ References
Figure 5. Micross has demonstrated bonding on test structures at 5µm Cu/Cu pitch (left) and 10µm Au/Au pitch (right). (Source: Micross)
[1]
D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “Heterogeneous Integration for Revolutionary Microwave Circuits at DARPA,” Microwave Journal, June 2015, pp. 22-38.
[2]
D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “A Revolution on the Horizon from DARPA,” IEEE Microwave Magazine, March/April 2017, pp. 44-59.
[3] www.darpa.mil/Our_Work/MTO/Programs/ DAHI/DAHI_Foundry_Technology.asp. [4]
Figure 6. UCLA is developing an interconnect scheme that leverages silicon wafers as the substrate (left) with 10µm and below pitch Cu interconnections. (Source: UCLA)
and Au metallurgies for 10µm and below pitch (Figure 5) with non-collapsible bumps [12]. A team at UCLA is also developing sub-10µm interconnect for CHIPS. They have demonstrated Au-capped Cu pillar interconnect at 10µm pitch (Figure 6) and have roadmap options to eliminate the Au cap and decrease the pitch further. A novel part of UCLA’s approach is the use of a silicon wafer as the substrate. This Silicon Interconnect Fabric (Si-IF) provides performance and mechanical advantages, and UCLA is developing system-level approaches for integrating the Si-IF. The interconnect strategy is a critical part of the CHIPS eco-system. Along with the technical capabilities for finepitch interconnect, there also needs to be access to foundries, MPW runs, volume assembly, PDKs, and other critical supply chain capabilities. DARPA is paving the way for some of this, but the eco-system also needs industry support that arises from the market potential of the CHIPS approach. In parallel, business models that fill new needs in the 18 MEPTEC REPORT WINTER 2018
CHIPS eco-system are being explored. For example, silicon IP companies are pursuing the option of becoming chiplet suppliers. Instead of just providing soft or even hard IP, they will sell verified chiplets ready for assembly. This is one example of the innovation brought by the CHIPS approach to the semiconductor marketplace. Conclusion DARPA’s CHIPS program aims to serve as the necessary piece of the puzzle that lets heterogeneous integration gain momentum in the marketplace by leveraging proven approaches of the semiconductor industry. With advantages for both defense and commercial applications, a critical mass of CHIPS adopters is expected. The industry has recognized the great challenges before us in IEEE’s newly revamped International Roadmap for Devices and Systems [13], and an important step was made when the IEEE, SEMI, and ASME jointly established the Heterogeneous Integration Roadmap[14] in recognition of the importance of het-
D. Scott, et al., “Diverse Accessible Heterogeneous Integration (DAHI) Foundry Establishment at Northrop Grumman Aerospace Systems (NGAS),” Proc. IPRM, Santa Barbara, 2015.
[5] Y.-C. Wu, et al., “InP HBT/GaN HEMT/ Si CMOS Heterogeneous Integrated Q-Band VCO-Amplifier Chain,” Proc. IPRM, Santa Barbara, 2015. [6]
Andrew Carter et al., “Wafer-Scale InP/Si CMOS 3D Integration Using Low-Temperature Oxide Bonding.” Compound Semiconductor Week, 2015.
[7]
Lawrence J. Kushner et al., “A 30 GS/s, 12-bit, 8-Vpp, Arbitrary Waveform Generator with Integrated 25 fs Clock in the DARPA DAHI Process.” GOMAC 2016.
[8] D. Green, “DARPA’s CHIPS Program and Making Heterogeneous Integration Com mon,” 3D ASIP, December 2017. [9] D. Green et al., “Heterogeneous Integration at DARPA: Pathfinding and Progress in Assembly Approaches,” ECTC, May 2018. [10]
R. Stevens et al., “An Application Specific IP (ASIP) Approach Offers a Design Solution Between ASICs and FPGA,” 3D ASIP, December 2017.
[11]
P. Borodulin et al., “Disaggregation of Advanced Node SoCs into 2.5D Modular Architectures for Rapid IP Reuse,” 3D ASIP, December 2017.
[12]
M. Lueck et al., “High Density Interconnect Bonding at 10µm Pitch and Below Using Non-Collapsible Microbumps,” 3D ASIP, December 2017.
[13] “International Roadmap for Devices and Systems,” irds.ieee.org/roadmap-2017. [14] “Heterogeneous Integration Roadmap,” eps.ieee.org/technology/heterogeneous integration-roadmap.html .
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