MEPTEC Report Summer 2022

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A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 26, Number 2

On the Road to Chiplets New Opportunities Emerge with 3D IC Multi-die System Design page 14

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Identifying Key Design Factors for Holistic Chiplet System Design and Integration page 17

Francesco Bisignani/Shutterstock.com

INSIDE THIS ISSUE

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UP FRONT With the arrival of August, it is easy to start thinking about what’s next when things “ramp up” in the fall.

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CALL TO ACTION Stakeholders need to initiate a shared vision to ensure a robust and sustainable supply chain for FPGA devices.

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COUPLING & CROSSTALK The entire landscape of the IC supply chain is shifting to accommodate heterogeneous integration (HI).

CATCHING UP WITH Neal Edwards, Principal Member of Technical Staff, AMD, joined the MEPTEC Advisory Board in 2020.

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MEPTECReport



UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: bcooper@meptec.org Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Zoë Conroy Cisco Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Joel Camarda Ron Jones

Contributors Ira Feldman Feldman Engineering Corp.

Summer Daze Ira Feldman Executive Director, MEPTEC

With the arrival of August, it is easy to start thinking about what’s next when things “ramp up” in the fall. Or perhaps the time is best used for a little relaxation by postponing these thoughts of work a little longer. In any case, I hope you were able to have some summer fun even if travel was not in your plans. Beyond experiencing new places and things, I find vacation travel refreshing as it simultaneously lets you ignore and look anew at day-to-day obligations, commitments, and routines as suits your mood. The MEPTEC Advisory Board is similarly taking the time to explore what our programming (events and activities) should look like for next year from a fresh perspective. Our goal is to not simply recycle-and-repeat the same events and topics but to determine what we can bring of value to the industry’s challenges. I would like to thank all the MEPTEC Advisory Board members – listed to the left – for volunteering to help direct the organization and contributing to the various technical program committees. Please share your thanks and ideas with them! The next scheduled MEPTEC event “KGx” will catapult us into the future as Known Good Die (KGD) is so last century! Even though true KGD remains elusive, today’s advanced packaging requires thinking beyond the die. The need for Known Good Stacks, Chiplets, Modules, Packages, Subsystems, Systems and more is essential to achieve the highest possible end-product quality. We will hold KGx as a two-part virtual event on September 7 and 8, 2022. Please save the dates to join us and we will be announcing the program in mid-August. If your company is interested in sponsoring, please let us know. I look forward to hearing your suggestions and feedback as to how MEPTEC can best serve you. Please don’t be shy! Stay safe and healthy!

Martin Hart TopLine Corporation Nitin Srivastava AMD Inc. Hing “Thomas” To AMD Inc. Dr. Ming Zhang Synopsys

Ira Feldman Executive Director, MEPTEC ira@meptec.org +1 650-472-1192

MEPTEC Report Vol. 26, No. 2. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.

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CALL TO ACTION

FPGA Blueprint for Havoc Martin Hart TopLine Corporation

Company CAGE CODE BAE Systems 1RU44 CAES (Aeroflex) 65342

AN EXPEDIENT WAY TO CREATE havoc in the Defense Industrial Base would be to acquire control of a particular Silicon Valley subcontractor, then close down its operations. Alternatively, one could take a less aggressive approach by keeping the subcontractor open and tripling the cost of services offered to its best customers. The price to acquire subcontractors of similar size is probably a rounding error for a cash rich investor. However, the collateral damage caused by such market disruption is upward of several billion dollars. This is a frightening prospect. Monopoly Businesses have Power Let’s take a better look into understanding how a tiny subcontractor can wield such power. Let’s consider that the above mentioned subcontractor is responsible for performing a supply chain service to attach solder columns to 90% of the free-world’s production of ruggedized Field Programmable Gate Array (FPGA) components. Why is this the case? Ruggedized FPGA components with solder columns are essential to the operation of warfighters and many aerospace applications. National security would be compromised without such ruggedized FPGA components. The monopoly business described above is basically supported with the blessings of the Department of Defense (DoD) and the Defense Industrial Base that has been in place for over 20 years. The policy of relying on just one supplier can only have justification if this sole-source subcontractor stays in business ad infinitum, which is a risky bet no matter how you consider it. Simply stated, one tiny business has a vulnerable choke hold on the industry. The Nation does not have a Plan B, even in case that the sole-supplier fails to deliver. 4 | MEPTEC REPORT

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Cypress Semiconductor Infineon Technologies

65786

Data Device Corporation 19645 / 7NV27 Honeywell International 34168 Microchip (Actel/Microsemi)

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Microchip (Atmel) F7400 Teledyne Technologies OC7V7 Texas Instruments 01295 Xilinx 68994 FPGA and ASIC Makers using Solder Columns. 3 Years for Supply Chain to Fill the Void Decision makers - most of whom are civilians - within the Defense Industrial Base are aware that it can take many years for an alternative supplier to jump through all of the necessary hurdles to become certified to attach solder columns on FPGA components. One reason for this is that the U.S. Defense Logistics Agency (DLA) is backlogged 3 years for conducting field audits for the purpose of certifying a second source of solder column attachment services. Another reason is that providing column attachment services is an artisan endeavor in a constrained niche market. Any subcontractor who is interested in providing column attachment services needs to be willing to invest millions of dollars in specialized equipment and commit to training employees for years to be proficient in the art and science of making and attaching solder columns. A lot of havoc can occur while the Defense Industrial Base remains vulnerable during a 3-year period, even as the Nation’s warfighters and aerospace capability remains idle, due to a lack of FPGA components with solder columns. Summary Defense-grade FPGA and ASIC component makers comprise an impressive list of market leaders.

Sadly, these prominent companies are reluctant to move beyond the current supply chain status-quo for the critical last step of attaching solder columns. The industrial base is not taking action to expand their reliance beyond the current single source subcontractor who provides 90% of America’s solder column attachment services. Conclusion Stakeholders need to initiate a shared vision to ensure a robust and sustainable supply chain for FPGA devices with solder columns. Fortunately, alternative manufacturing of copper wrapped solder columns and attachment services is already available domestically, pending certification. Action should be taken now to qualify multiple subcontractors who are ready and willing to provide the critical process of copper wrapped column attachment services for FPGA packages. A prudent investment today can mitigate the risk of waiting for an unexpected disaster to strike, with its potentially unimaginable cost to the defense industry. An unplanned production stoppage of critical FPGA components could imminently severely diminish market readiness at any time. The Defense Industrial Base has the means to act swiftly and proactively to build a solid foundation for the long term.◆ meptec.org


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MEMBER NEWS

IN MEMORIUM | Joel Camarda IT IS WITH GREAT SADNESS that we announce the passing of Joel Camarda, a valued colleague and longtime friend of the MEPTEC community on May 27. Joel was a native New Yorker educated at the prestigious Brooklyn Technical High School and New York University’s School of Engineering. Like so many others not from California, Joel and his wife Valerie set out on a one-way road trip to California, settling in San Francisco. Originally envisioning a career in aeronautical engineering, opportunities within the semiconductor industry presented themselves and Joel carved out a forty-sevenyear career as a sought-after leader. National Semiconductor was his gateway and operations and manufacturing became his specialty. There, his first foreign assignment was a three-year stint in the Philippines managing NSC’s manufacturing operation. Building and operating wafer fab manufacturing plants in Malaysia, Thailand, Indonesia, and Singapore (his favorite), as well as numerous forays into China followed.

 industry always far surpassed the present situation. We will always remember his unique voice. We have lost a friend, colleague and charismatic and energetic member of the semi-industry team. Joel will be missed, but never forgotten. ◆

His work travel also took him to Haiti, Scotland and France. Over the years Joel’s positions at various companies steadily rose from Engineering Manager to Senior Director of Manufacturing to Senior VP of Operations to Division President. Upon hearing of his passing, some of Joel’s colleagues shared that he had one of those larger-than-life personas... he was one-of-akind in the industry and as a person overall. He was a brilliant engineer, cheerful and reserved. We loved hearing him talk about things, anything. Joel was a very kind person and was always willing to help others. He always showed up with positive energy, and his vision of our

I know this announcement will come as a great shock to the many MEPTEC members, colleagues, and friends who have followed us over the last few decades. Over the years Joel became a great personal friend of mine and a loyal supporter as a member of our Advisory Board, which he joined in 1997 – one of our longest serving Board members. If you ever attended a MEPTEC event or luncheon, you would have likely seen him there. For many, many years we worked together and through his vast expertise in the industry he was always there to gladly lend his participation to whatever activity or event that was going on at any given time. We may have lost him, but I for one will never forget him. – Bette Cooper

NXP Collaborates with Foxconn on Next Generation Vehicle Platforms NXP SEMICONDUCTORS ANNOUNCED that it has signed a memorandum of understanding with Hon Hai Technology Group (“Foxconn”) to jointly develop platforms for a new generation of smart connected vehicles. Hon Hai (Foxconn) will leverage NXP’s portfolio of automotive technologies and its longstanding expertise in safety and security to enable architectural innovation and platforms for electrification, connectivity and safe automated driving. The collaboration builds on the company’s initial digital cockpit partnership, based on the NXP i.MX applications processors and NXP Software Defined Radio platform. The primary focus of the expanded collaboration is aimed at Foxconn’s efforts in electrical meptec.org

vehicle platforms, leveraging NXP’s system expertise and comprehensive electrification portfolio, from NXP S32 processors to analogfront-end, drivers, networking and power products. Another innovation priority is connectivity solutions using the latest NXP S32 domain and zonal controller family for gateways and vehicle networking control, while also advancing secure car access with ultra-wideband and Bluetooth Low Energy. A third pillar is safe automated driving augmented by NXP’s leading radar solutions. NXP will also offer hardware and software support and will leverage the expertise of its well-rounded 3rd-party ecosystem in the areas of electrification, connectivity and automation. Find out more at www.nxp.com. ◆

PROMEX APPOINTS SEMICONDUCTOR INDUSTRY VETERAN CHIP GREELY AS VP OF ENGINEERING

PROMEX INDUSTRIES has announced that Chip Greely has signed on as the company’s new VP of engineering. In his new role, Greely is responsible for the assembly process engineering organization at Promex’s Santa Clara headquarters. He will focus on ensuring the company’s service offerings are aligned to customers’ dynamic, advanced manufacturing requirements. Greely has more than 35 years of industry experience working with a wide range of semiconductor companies, including Qualcomm, GE and Amphenol, as well as OSAT providers, such as CORWIL Technologies. www.promex-ind.com

NATIONAL CHENG KUNG UNIVERSITY BESTOWS HONORARY DOCTORATE ON ASE CHAIRMAN CHANG

ASE TECHNOLOGY HOLDING Co. Ltd. Chairman and CEO Jason Chang has received an honorary doctorate from the National Cheng Kung University for his outstanding contribution to Taiwan’s semiconductor industry. This award recognizes Jason’s strategic vision, perseverance, and meticulous execution enabling ASE to become an influential industry player and a role model in corporate responsibility. Under Jason’s leadership, ASE has been on the leaderboard of the Semiconductors and Semi Equipment segment on the Dow Jones Sustainability Indices for 6 consecutive years (2016-2021). www.aseglobal.com

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MEMBER NEWS 

SHINKO ELECTRIC TO OPEN A NEW PLANT

SHINKO ELECTRIC INDUSTRIES CO., LTD. (SHINKO) has begun construction of a new plant in Chikuma City, Nagano Prefecture. The Chikuma Plant is located at 2789-1 Amenomiya, Chikuma City, Nagano Prefecture, Japan. Products produced will be Flip-chip type packages for high-performance semiconductors. The manufacturing plant is a six-story, steel frame structure with a total floor area of 50,000 m2. Construction was scheduled to begin in June 2022 with a completion date of November 2023. Operations are expected to begin in the second half of FY 2024. www.shinko.co.jp

 TI BREAKS GROUND ON NEW WAFER FABS IN SHERMAN, TEXAS

TEXAS INSTRUMENTS broke ground May 18th on its new 300 mm semiconductor wafer fabrication plants in Sherman, Texas. In a groundbreaking ceremony attended by elected officials and community leaders, TI Chairman, President and CEO Rich Templeton celebrated the start of construction on the largest private-sector economic investment in Texas history and reiterated the company’s commitment to expanding its internal manufacturing capacity for the long term. The potential $30 billion investment includes plans for four fabs to meet demand over time, supporting as many as 3,000 direct jobs. The new fabs will manufacture tens of millions of analog and embedded processing chips daily that will go into electronics everywhere. www.TI.com/Sherman

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Roger Grace Associates Celebrates 40th Anniversary of its Founding During Sensors Converge 2022 ROGER GRACE, PRESIDENT OF ROGER GRACE ASSOCIATES, the world’s leading marketing consultancy specializing in sensors and MEMS celebrated the 40th anniversary of its founding as a technology marketing consultancy during a most festive cocktail party/ reception held at the San Jose Marriott Hotel during the 37th annual Sensors Converge Technical Conference and Exhibition. Joined by over 30 well-wishers including clients, editors, colleagues and speakers from its successful Sensors Converge Preconference event on printed and functional fabric sensors, a fun time was had by all. In a brief address, Roger thanked the attendees for their valuable support and especially called out the Sensors Converge team who have assisted many of the Roger Grace Associates’ clients as well as his consultancy for over several decades to effectively address the sensors market vis-a-via exhibiting and making presentations at their annual event. He specifically recognized several of his long-term clients/ friends in attendance including MEMS industry luminaries and NovaSensor co-founders Janusz Bryzek and Kurt Petersen (third founding member Joe Mallon was not in attendance) with whom he collaborated as marketing counsel to create, plan and execute an integrated marketing communications program focusing on branding and positioning for this early client

including the organization and its participation at the first Sensors Expo in 1995. The results of which successfully introduced and helped propel NovaSensor to become an industry-wide recognized leading MEMS innovator over 35 years ago. His address concluded with…”we all here could not have realized the level of success that we have come to experience without the dedication and valuable contributions of Sensors Expo/Converge and their team of professionals”. The piece de resistance of the evening was the serving of a 40-year-old Port wine accompanied by a Portuguese custard tart desert, reflecting Roger’s Portuguese heritage, and which were thoroughly enjoyed by all the attendees. ◆

Intel and MediaTek Form Foundry Partnership MediaTek will use Intel Foundry Services to manufacture new chips for a range of smart edge devices. INTEL AND MEDIATEK have announced a strategic partnership to manufacture chips using Intel Foundry Services’ (IFS) advanced process technologies. The agreement is designed to help MediaTek build a more balanced, resilient supply chain through the addition of a new foundry partner with significant capacity in the United States and Europe. MediaTek plans to use Intel process technologies to manufacture multiple chips for a range of smart edge devices. IFS offers a broad manufacturing platform with technologies optimized for

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high performance, low power and always-on connectivity built on a roadmap that spans production-proven three-dimensional FinFET transistors to next-generation breakthroughs. “As one of the world’s leading fabless chip designers powering more than 2 billion devices a year, MediaTek is a terrific partner for IFS as we enter our next phase of growth,” said IFS President Randhir Thakur. NS Tsai, corporate senior vice president of Platform Technology & Manufacturing Operations at MediaTek, said, “MediaTek has long adopted

a multi-sourcing strategy. We have an existing 5G data card business partnership with Intel, and now extend our relationship to manufacturing smart edge devices through Intel Foundry Services. With its commitment to major capacity expansions, IFS provides value to MediaTek as we seek to create a more diversified supply chain. We look forward to building a long-term partnership to serve the fast-growing demand for our products from customers across the globe.” For more information, visit intel.com. ◆

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COLUMN COUPLING & CROSSTALK By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Strange Bedfellows With apologies to The Bard, it is more than misery that acquaints a person with strange bedfellows. Today’s technology landscape has produced some rather interesting relationships and industry dynamics. Yes, it was surprising to many when it was disclosed in 2018 that Facebook (now Meta) the social media platform – which really is a ‘marketing’ company that happens to run hyperscale data centers – was designing its own artificial intelligence (AI) integrated circuits (IC). You may have also been surprised with the recent news that Google is working with SkyWater Technology to continue developing open-source cloudbased IC design tools. They have already developed an electronic design automation (EDA) tool and process design kit (PDK) for the SkyWater 130 nm fab process. And with support from the US Department of Defense (DoD), they are now working on tools and PDK for the SkyWater 90 nm process. It may be more interesting that Google is also covering all the costs to fabricate open-source IC designs (i.e. all the design details are freely available)! True, there are only a handful of chips per design being built on a multi-project wafer (MPW) using the Google tools and the SkyWater process. But nonetheless, they are giving away IC fab services for those willing to share their designs. Clearly paradigm shifts in so many ways disrupting the status quo! As explored at the MEPTEC Road to Chiplets workshops, including the most recent one focused on Design Integration held in May 2022, the entire landscape of the IC supply chain is shift8 | MEPTEC REPORT

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ing to accommodate heterogeneous integration (HI). Conceptually integrating diverse functionality into a single device is rather simple. However, the real-world implications of delivering high volumes of such devices cost effectively at the required quality levels is proving to be a significant challenge. The approaches to HI range from incorporating widely varying circuit functionality on a monolithic die to packaging multiple dies or sub-dies (“chiplets”) in one package. The single die approach is challenging both in terms of the design tools and the fabrication process. Design tools are often

Clearly all members of the team will need to operate crossfunctionally – even if beyond their comfort zone! optimized for a given process technology which in turn is targeted for a certain type of device. Different fabrication processes are used for analog, digital logic, wireless, and memory devices. And each fabrication process is optimized to yield the highest performing devices of the given class. Therefore, attempting to add a mix of functions in a single device is challenging as the selected fab process is likely optimal for just one of the functions. For example, building a microprocessor with large amounts of embedded memory and analog functionality is very challenging when the fab process is optimized digital logic. Multi-die integration into a single package has always been challenging even when there were just two die. This integration progressed from multi-chip modules (MCMs) in the 1970’s and 1980’s to 2.5 and 3D in the mid-2010’s to the most recent chiplet approaches. A typical MCM has two or more die placed on a single substrate. And the MCM substrate usually requires very high inter-

connect density and is typically made of ceramic, hence they are expensive to produce. On occasion, there have been MCM substrates that have cost more than the die placed on them. The 2.5 and 3D integration approaches have been likened to Lego building blocks. Having dies next to each other on a common substrate made of silicon, glass, or organic materials is the “2.5D” version. Stacking thinned die using through-silicon vias (TSVs) is the “3D” approach as often is done with memory die. Regardless of how the die are stacked or interconnected, there are plenty of packaging challenges as each of the heterogeneous devices is different. Two side by side die may not be thinned to the same thickness. Or they may not have the same thermal profile – especially if the die types are different. A logic die may run much warmer than a memory die. Therefore, the packaging needs to accommodate a wide thermal variation across the die while also handing any variation within each individual die. And with chiplets, the number of individual pieces of silicon (die or chiplet) in a given package may explode to 10 to 20x the current number. Instead of multiple intellectual property (IP) blocks in the device that are represented by a software library which is integrated in the end device design when built monolithically (i.e. on a single die), chiplets will allow IP vendors to simply ship a small piece of silicon (much less than the size of a single die) that contains just their functionality. Hence, assuming the chiplet market becomes established, IP development companies will need to shift from providing designs to having to ship Known Good Chiplets. These companies which are accustomed to “shipping” software or data today will almost instantly be in the business of supplying and distributing physical hardware. Many of the challenges that HI designs need to solve are “cross domain”. The packaging engineer needs to make sure the IC package can properly dissipate the heat the device generates. Both when the chip is packaged in “mission-mode” and when it is being tested. This may require a close collaboration between the packaging engineer, the product manager, the system engineer, and the test engineer to ensure the proper operation of the device – from meptec.org


wafer test to final test to module test to system level test. Each of the engineers will likely need to learn something from another domain – the electrical engineer from the thermal, the material engineer from the test, the mechanical engineer from the system engineer, etc. These types of problems will not be solved with the expertise from just one domain. Clearly all members of the team will need to operate cross-functionally – even if beyond their comfort zone! At the same time, companies will need to cooperate with others. Quite possibly a company’s archrival maybe the only company supplying a particular chiplet with the desired functionality. Or competing companies within the supply chain may both be engaged in the same project for a silicon provider as each may be providing different expertise as requested by the end customer. As we get further into the world of HI, what can an individual contributor or manager do to brave this new landscape? The first is to learn more about the technology requirements – including from other domains - and the overall

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business. Instead of asking “why are we doing _____”, spend time to learn “what business problem are we solving”. To assist with this, MEPTEC will continue to look at the technical challenges crossfunctionally and include market overviews with the technical presentations as we develop our programming. It is also helpful to contribute to the development of and use industry standards. In addition, participating in groups developing best known methods and road mapping such as the Heterogeneous Integration Roadmap (HIR) from the IEEE Electronic Packaging Society allow the pre-competitive sharing of knowledge to better align industry activities. Sharing knowledge of your company’s technology, activities, and even technical challenges at industry events such as those hosted by MEPTEC provides an outreach function that allows others to offer solutions or assistance. At a minimum, it provides the opportunity to talk with others who may either have solutions or similar problems. Lastly, it is important to tap the power and knowledge of networks

– either yours or that of an industry consultant. Both can be done discretely if you are not permitted to publicly “tip your hand”. Consultants may have worked on a similar challenge and at a minimum know who to ask. And your industry colleagues may be able to help confidentially or a one-on-one basis. So don’t be a stranger! Reach out to a consultant today for immediate assistance and take the time getting to know others at events proactively. As technology is rapidly being developed to bring to market devices that were science fiction fantasies of our youth, crazy collaborations of companies will come together to bring these ideas to life. Don’t worry about how strange your new bedfellows are. Instead, get to know them and stay focused on the business challenge being solved. For more of my thoughts, please see my blog http://hightechbizdev.com. As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆

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INTERVIEW

Catching Up with Neal Edwards Principal Member of Technical Staff Advanced Micro Devices, Inc.

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With…” features stories from and about our members. Neal Edwards (https://www.linkedin. com/in/neal-edwards-b4a53b5/) joined the MEPTEC Advisory Board in 2020. This interview was conducted via email and edited for clarity. What interested you about Product Development Engineering at AMD right after obtaining your Bachelor from University of Illinois UrbanaChampaign? Was the position what you expected? Any interesting surprises or stories? I got my start with Product Development Engineering (PDE) as a cooperative education student with AMD. Prior to graduation I did two co-op terms with AMD as a PDE. At the time AMD was in the MHz race with Intel and during my first tour AMD launched the world’s first 1GHz CPU. As coop I did not know what to expect as a PDE. The first co-op term was a lot of learning about the Teradyne J973 and the software environment around using it. The was a lot of software involved at the time in test program development. AMD developed a very custom environment around the tester hardware. While this provided significant advantages the high level of customization leads to difficulty in support and scalability. I think later in my career I strove to avoid the same level specialization. With eight months of experience as a co-op, going back to AMD full time was an easy transition from school.

meptec.org

How well do college programs prepare one to do test development and/ or software development in the commercial world? How well prepared where you at the time? Has the situation changes/improved since then? If not, what are the gaps that need to be closed? I feel I was adequately prepared for software development from my college courses. The nature of software development is that the technologies and practic-

AMD developed a very custom environment around the tester hardware. While this provided significant advantages the high level of customization leads to difficulty in support and scalability. es can change very rapidly. One of the key skills from college is to the ability to evaluate the needs of a problems and find the appropriate tools to solve the problem. With the rapid expansion of software and tools, often you don’t need to develop a very custom solution. But choosing the wrong technology can lead to large amounts of wasted effort and

deliver poor results. The ability to evaluate and build small trials are critical. Software management wasn’t covered in my school program, but I believe it is a larger part of curriculums today. Often greater than 60% of the cost of a software project is in maintenance; it means following industry practices like Agile, Continuous Improvement/Continuous Delivery (CI/CD), and Feedback. CI/CD more critical for the long-term success of a project. The importance continues to increase with the rise of Data Projects and Machine Learning projects. You did test program development in your Product Development Engineering position when you joined AMD. Where does the product engineering role end and the test programmer role begin? Both roles have a lot of overlap. I see a product engineer is focused on ensuring the product meets the business requirements in terms of power and performance. The Test engineer is ensuring there are no defects in the product while the cost is minimized.. As a PDE, did you also work with test engineers? On the very earliest work there wasn’t a big differentiation between Product and Test engineers. We all worked together on the test program and development. As AMD grew the roles got further differentiated but still work closely together. How steep was the learning curve about semiconductor manufacturing, especially AMD’s for high end processors? Any advice you would give to people new to the field? SUMMER 2022 MEPTEC REPORT | 11


While I think the learning curve is steep, most semiconductor companies understand this and are willing to put in effort to train. If you come with a willingness to learn and some key skills you can learn much of the specialized knowledge. It does take a significant effort internal to a company to learn those and it requires a new engineer to seek out internally resources to help grow their knowledge. At the time you were working on three of the four major test platforms - Credence Sapphire (now Cohu), Verigy 93000 (now Advantest), and Advantest T2000. How similar was test development between the platforms and how different was it? Did you have to “think differently” depending on the test platform you were working on? Architecturally I don’t think any of the platforms requires a different mindset. Each platform does require some level of software layer to accompany the ATE build in test methods. Did you build tools that took AMD specific tests and deployed to all three platforms? Was this an efficient way to go? Fundamentally we have tried to abstract the differences in ATE software and Test program development interfaces to allow a write-once use-multiple approach. For most of our common use cases it works very well. The edge cases or the special features of a given platform tend to break the common abstractions and force a customized approach. Please describe your role as Member of Technical Staff that you have been in since 2010. I’ll just cover my various roles at AMD: I started my career as a product/test engineer on the K7 and K8 line of processors working on the J973. I moved internally to the team to bring up the Credence Sapphire ATE platform. I worked on enabling our first Dual Site 12 | MEPTEC REPORT

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test program and strategy. I then got pulled into a software team to develop an ATE test software to support multiple ATE vendors. We evaluated Ultraflex, T2000, 93k and still supported Sapphire. This team spent a lot of time bringing in the best practice software development practices. Things like Agile, Git, CI/CD. From that team I moved back to Test Engineering on the Ryzen line of processors. Here we brought those software practices into the test and product engineering side. Finally, I arrived on our Data Analytics team and pioneered a move from onpremise Hadoop cluster warehousing our data to a cloud-based data analytics platform. This really enables AMD to scale our efforts and apply data in a broad scale across all of Global Operations and Quality. How big is your software team? Did most of them start from the test/ production side or more right out of college? For our ATE software team we started with about eight people all of whom were from test/product engineering who also had an interest in software development. For our Data team is still about 8-10 people, but only 1 or 2 of them come from the product side. The others were hired specifically as Data Engineers, Data Scientists, and Software Engineers. Which is a greater challenge – teaching test/product engineers about software development or teaching data engineers/scientists and software engineers about test? I don’t think there is a greater challenge in teaching either group. Putting those teachings into practice and the accompanying challenges will depend more on the specific team and the organization than anything else. Most of us know about Agile and Continuous Integration as software development methodologies. Please explain Test Driven Development (TDD). What does someone need to

do or think differently? How well does it fit into a product test environment? Test Driven Development is the idea that you write a unit test prior to writing any code. Once you have a test you can then develop the code required to meet the test. It forces developers to think about the outcome and ensure the software is testable and modular in its design. I believe you get involved with both data warehousing and machine learning (ML). Both of which involve humongous datasets. Are you surprised or disappointed by what ML can do with sufficiently large data sets? The struggle with ML is that 80% of the work revolves around the data preparation and maintenance of the software product. The 20% left is the most interesting algorithms that do the work. A lot of teams want to leverage ML but leave out that 80% of work and that often leads to failures on the project. Additionally, ML is usually developed for a very specific question it is trying to solve. It doesn’t often scale to other applications without redoing a lot of work. I take a very practical approach to ML. ML is a tool I can use to solve a problem, but it isn’t the Swiss Army knife of Data Analytics and often a simpler approach is preferable. Do you like to travel? If so, where or what do you enjoy most? Yes, anywhere in the woods or mountains. What else do you do for enjoyment or relaxation? I enjoy playing ultimate frisbee around Austin and anywhere else I can find a game while travelling. Our family enjoys camping and visiting national parks. This past year we got to spend a week in Yellowstone and the Great Smoky Mountains. We’d like to do a bunch of parks in Utah in the next few years. ◆

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Save the Date ­


SYSTEM DESIGN

On the Road to Chiplets – New Opportunities Emerge with 3D IC Multi-die System Design Dr. Ming Zhang, Distinguished Architect Synopsys

DISRUPTIVE CHANGE IS AT HAND in the semiconductor market. Every year, greater functionality is being jammed into chips of every conceivable size, yet fabrication costs and complexity remain sky-high. Today’s designers must consider the most effective way to grow chip size, speed, and capabilities to meet their specific requirements, particularly for advanced segments like artificial intelligence (AI) and machine learning (ML), high-performance computing (HPC), and mobile devices. There has already been an evolution in play, from design with schematics in the 1980s to hardware description language (HDL) in the 1990s and intellectual property “blocks” (IPs) in the 2000s. Now many leading companies are leaning on design with a system of “chiplets.” Today’s big transition is from designing a system on chip (SOC) to a system of chips, triggering a disruptive transformation in the industry. The trend is taking monolithic chips and building them with a more modularized approach, turning to advanced packaging to aggregate chiplets to optimize functionality. “Successful 3DIC Multi-Die Silicon System Design Using Synopsys 3DIC and Ansys Multiphysics Analysis” was recently presented in May at the MEPTEC Road to Chiplets – Design Integration virtual event. The presenters Kenneth Larsen, director of product marketing at Synopsys, and Marc Swinnen, director of product marketing at Ansys, covered these timely topics in depth as they outlined the advent of multi-die system design using Synopsys’ 3DIC solution and Ansys’ multiphysics analysis to build and leverage chiplets more efficiently. The Rise of Chiplet-based Solutions Integration is the key driver in the 14 | MEPTEC REPORT

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innovative move to a system of chiplets. Designers can break large designs into smaller parts, then re-integrate them into a new system. This results in a smart system design where each of the parts can be optimized in the node that is providing the best performance and cost, says Larsen. “The process of disaggregation of chips takes a large SOC and breaks it down into smaller, more manageable pieces.” This process is motivated by lowering costs and raising system yield. The need for chiplets spans multiple customer segments, including computing and storage, communication, and automotive. Chiplets provide a range of benefits, including: 1. Better yield with smaller dies and an opportunity to build larger systems 2. Significant savings and lower costs from optimal chiplet technology

3. Chiplets can be reused, targeting many different markets and products 4. Lower system power while increasing throughput of the system itself Larsen reports that the industry has grand ambitions to eventually get one trillion active transistors on a single package in the next iteration. Synopsys and partner Ansys are focused on helping the market realize that goal. The Next Leap in IC Design – 2.5D and 3D The next big step in IC evolution is 3DIC, which takes advantage of the vertical dimension for even denser circuits and even faster interconnections. Stacked 3DICs contain multiple dies stacked, aligned, and bonded in a single package, using through-silicon vias (TSVs), bumps, and hybrid bonding techniques

Figure 1. 3DSOC Image credit: Synopsys

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for inter-die communication. According to Larsen, “Three-dimensional ICs has emerged as a fantastic solution to multiple design challenges. They combine multiple devices in ways that provide faster interconnections and greater density than mounting chips side by side on a traditional 2D planar printed circuit board, or PCB.” 2.5D ICs, which were first seen as a short-term compromise when 3D ICs were not yet practical, continue to find adoption in many use cases. In the 2.5D IC approach, bare dies are placed next to each other on an interposer and connected with wire bonds. This consumes less space than multiple packages on a PCB and provides faster connections from die to die since there are no device pins or PCB traces in the paths. One significant advantage of 2.5D is the ability to mix dies from different nodes or even entirely different chip technologies. This makes it possible, for example, to shrink the digital portion of the design to a new mode while continuing to use existing analog and memory dies with no re-design required. This approach also makes modifying a design for different target applications easier. Leveraging the 3DIC Compiler Larsen continues, “The 3DIC Compiler is our unified multi-die system design platform, an all-in-one exploration-to-signoff solution for 3D heterogeneous integration, chip stacking, and advanced packaging.” The holistic platform allows you to work on the entire technology stack spanning multiple technology and material layers, from top chips, interposers, and RDL packages to the BGA/LGAs. “It’s a flexible, modular platform that allows you to design and integrate very large systems of chiplets, 3D stacks, and other advanced packages,” he concludes. The 3DIC Compiler streamlines four key processes: 1. Architectural planning, which encompasses exploration, pathfinding, system topology, and helping to determine the best architecture to leverage, such as 2.5 or 3D. 2. Design creation and integration, which spans design partitioning, 3D meptec.org

Figure 2. 2.5D Silicon interposer with Through-Silicon-Via (TSV) Image credit: Synopsys

floor planning, and managing connectivity for 100s of billions of transistors. 3. Design implementation, which includes optimizing die stacking, ensuring the correct power, clocking, and routing across the whole stack, all the way down to the package. 4. Trusted Golden Signoff and multiphysics analysis, which is achieved in conjunction with partner Ansys. “We are extending 3D-system integration solutions for next-gen highperformance computing designs,” says Larsen. Iteratively Explore, Create and Optimize All in One Place What is really revolutionary about the new approach is that the architecture is built to accommodate both the 2.5D Interposer and the 3D Stacked Die. As Larsen explains, “In the past, it wasn’t possible to create the entire system of chips and package layers as one. We’ve created new capabilities to move things around to improve the design’s overall performance. That means designers can be creative with how and when they design and execute at different layers of the system to make it more optimal for specific requirements. Think of it as two chiplet generations in one!” Larsen continues, “In the system

creation phase, we’ve woven in fast, analysis-driven ‘what-if’ design exploration and prototyping to enable you to mix and match designs and chiplets in different technologies, build them together and optimize them as one,” explains Larsen. “We also automate design implementation to help speed up the packaging turnaround time for our customers and streamline the full spectrum of system analysis to ensure it’s being performed as early in the process as possible. He also tells us that “abstraction is an essential part of the process. We take a different approach, selecting levels of details that you want when working with large multi-die systems. You’re able to design with hundreds of chiplets by hiding some information from chiplets when not needed in the design cycle.” And a final thought on manufacturing: “When you’re sticking things really closely together, you must make sure your design is meeting manufacturing rules,” Larsen says. “3DIC Compiler helps you fill in the missing pieces, manage chip placement, connectivity, and alignment, and has visualization for 3D DRC/LVS design checks. The solution also helps you test all the new requirements to determine if the connections are degrading, using thermal cycling simulations, and gives you early indications if they are.” Better Team Collaboration Today, package design teams are often separated from the chip design teams, with limited inter-team communication. Now, says Larsen, the 3DIC Compiler enables a more collaborative environment to bring designs to market more quickly. As Larsen explains, “You might have one engineer working on one die who makes various changes that impact other areas. Now you can consolidate this information, creating a co-developed environment for your 3D design. Engineers working on individual dies or parts of dies can easily collaborate to make sure everything is working properly in the full system.” Overcoming Multiphysics Challenges “For most 3DIC projects, power design and thermal management are SUMMER 2022 MEPTEC REPORT | 15


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Figure 3. Thermal Results for mBump Image Credit: Ansys

among the biggest challenges,” says Ansys’ Marc Swinnen. “Multiphysics system analysis is a powerful tool for teams to master their design constraints, including thermal analysis throughout the design flow.” This is where Synopsys partner Ansys comes into the picture, with RedHawk-SC Electrothermal Thermal Analysis. They have collaborated with Synopsys to make their electro thermal analysis suite of products available in the 3DIC Compiler. “It’s a multi-physics signoff suite that provides analysis across the entire spectrum, seeing how they all interact together and delivering the ‘golden analysis’ for the entire system,” says Swinnen. “The system prevents overdesign and under design by analyzing the chip and interposer for accurate power distribution.” As Swinnen reports, “Thermal analysis is the limiting factor on multi-chip design. It’s not uncommon for a design to work perfectly, but it ultimately overheated, both across the chip and the package. The key is to catch design issues before they can have an impact.” In one use case, the product identified a meltdown issue with a high-power HPC design, catching an electro-thermal 16 | MEPTEC REPORT

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issue on the micro-bumps that carry the current. “If it doesn’t cool down fast enough, the solder will melt, creating a catastrophic failure,” explains Swinnen. Summary Synopsys and Ansys are excited about the opportunities that the new 3DIC Compiler and Ansys’ thermal analysis tools bring to the chip market. Larsen and Swinnen at the MEPTEC Road to Chiplets Design Integration virtual event discussed this next evolution in chip design and development as a path to leveraging chiplets, which will bring new efficiencies to advanced markets like AI, automotive, mobile, 5G, and HPC. Whether it’s 3D or 2.5D development, the needs of every designer and manufacturer can be accommodated in the new model. ◆

Synopsys, he was a circuit designer at Intel specializing in low-power and faulttolerant designs, foundry engineer at Samsung specializing in DFX, software developer at AI startups working on algorithm development and cloud deployment, and, most recently, the co-founder and CEO of a chiplet startup, zGlue. Dr. Zhang holds a Ph.D. EE in VLSI from the University of Illinois at UrbanaChampaign (UIUC), an M.S. in MEMS from UIUC, and a B.S. in Physics from Peking University in China. ◆

Dr. Ming Zhang Distinguished Architect Ming Zhang is a Distinguished Architect at Synopsys, leading technology strategy and market development for the Silicon Realization Group. He led corporate strategy for 3DIC technology upon joining Synopsys in 2021. Prior to meptec.org


INTEGRATION

Identifying Key Design Factors for Holistic Chiplet System Design and Integration Hing “Thomas” To, AMD Inc. Nitin Srivastava, AMD Inc.

TRYING TO MEET EVER-INCREASING computing workload demands, silicon System-on-Chip (SOC) semiconductor devices has been integrating more and more features with the most advanced silicon technology nodes. However, the explosion in computational workload diversity means no single computing system fits all applications. Also, the cost of monolithic IC (Integrated Circuit) integration and scaling has skyrocketed in recent years. The functional and feature benefits offered by process technology shrinkage are diminishing at each process node. Adding all the features of interest in the most advanced process node will make the design more complicated and challenging. Instead of cramming all these features in a single monolithic die, chiplet implementation uses a selection of modular dies, referred to as chiplets. These chiplets will have different functions and even are developed at different silicon process nodes. System developers can mix and match these chiplets to meet the feature and performance needs. This heterogeneous integration approach provides best-in-class technology among the selected chiplets. It is gaining attention and momentum to keep SOC performance scaling forward. One of the challenges, however, is moving data at high speed between chiplets and identifying critical areas for optimization. Further, when chiplets are implemented by different companies, the critical design factors that need specification are crucial in enabling the development ecosystem. In this article, a methodology focusing on chiplet interconnect jitter modeling is proposed. A behavioral jitter model, which is based on an analytical expression of power supply induced jitter and jitter accumulation along the path, is first developed. The jitter at each stage is integrated with the previous stage’s jitter as meptec.org

Costs and ROI of Mono Silicon Die Development

Process Node

Figure 1. ASIC Development Costs and Return Of Investment [5].

an input. The model captures the source synchronous architecture behavior by referencing the data path jitter to the source synchronous reference strobe. It also can model the system clock accumulative jitter should the chiplet interconnect architecture use global system clocking for retiming. The model is extended to represent different input factors for the system output data path jitter. These input factors include, multiple supply power frequencies, their corresponding noise amplitudes, data path delay as well as channel routing configurations. An output jitter response surface model, with different power tone frequencies and noise amplitudes, is then developed, with an optimal channel interconnect. The response surface model provides a contour to identify critical input design factors. With that, system platform designers can evaluate the multiple input factor effects and their interactions. This approach allows for a more holistic and broader consideration for optimization. Also, based on this analysis, critical

design factors can be defined as key system specifications to enable the efficient ecosystem development. This article will illustrate the development methodology and chiplet interconnect system lab results from a High Bandwidth Memory (HBM) package using InFO and interposer correlation. Key Terms – Chiplets, Monolithic Silicon, Chiplet Interconnects, Jitter Accumulations, Power Noise Tones, Response Surface Model 1. Introduction Traditional method to improve system performance is by scaling with advanced silicon technology node [1], [2]. Advanced silicon process technology node provides faster and denser transistor implementation. This scaling method works well in conventional CPU computing environment. This is because besides CPU core speed, system performance is also strongly dependent on transistor density. In general, the more transistors that can SUMMER 2022 MEPTEC REPORT | 17


INTEGRATION

be implemented in the same area, the more features that can be packed in the System-On-Chip (SOC). However, the limitations of putting more transistor in a silicon die is dictated by the silicon reticle yield limit. Process technologies is scaled to improve this limit over time to provide the scaling requirements. However, scaling to smaller process nodes increases the silicon die yield cost. The 7nm process node implementation is estimated to be to 7 times of the 28nm cost per yielded mm2 [3] . It is expected that the cost will continue to increase even more in 5nm and 3nm nodes. The cost of monolithic integrated circuit (IC) integration and scaling has skyrocketed in recent years [4]. The increasing cost severely impacts the return of investment (ROI) offered by process scaling. Based on a recent study [5] which compares the return of investment of monolithic silicon and development costs, shown in Figure 1, the ROI is unattainable. In addition, modern computational requirement is more diverse, such as machine learning applications, from the traditional SOC. For example, analog components and IO circuitry get a smaller shrink factor improvement than digital logic and SRAM when moving to smaller advanced technology nodes. Adding all the features of interest in the most advanced process node will make the design more complicated, costly & challenging. Chiplet implementation uses a selection of modular dies to integrate and form a combined SOC. These chiplets can have different functions and even can be developed in different silicon process nodes. The chiplets are connected via interconnect channel to establish functional communications. System developers can mix and match these chiplets to meet feature and performance needs. This heterogeneous integration approach provides best-in-class technology among the selected chiplets. It is gaining attention and momentum to keep SOC performance scaling forward. Figure 2 is an example of using a passive silicon interposer connecting multiple FPGA SLR (Field Programmable Gate Array Super Logic Region) [6]. The SLR can be programmed to serve different 18 | MEPTEC REPORT

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Figure 2. An Example of Chiplet Implementation [6].

Figure 3. Chiplet Implementation Evolution Timeline.

application requirements. Section 2 of this article will further elaborate the opportunities and challenges of chiplet heterogenous implementation. Among many system design considerations, the needs to ensure high-speed data transmission between the chiplets will be highlighted. Also, the requirements on managing chiplet IO channel jitter and time uncertainty will be elaborated. Section 3 describes an analytical method to combine the underlying design factors that contributed to system timing uncertainties/jitter. Section 4 outlines the key design factors sensitivity analysis flow and the method to identify the most influential design factors. This analysis reveals the most influential design factors to the overall outcome which, guides the optimization of the key factor specification and improvement gradient. Section 5 will showcase an empirical application of HBM which was implemented in silicon interposer and Integrated Fan-Out (InFO) channel. The conclusions and a summary of the key takeaways are in Section 6.

2. Heterogenous Chiplet Implementation: Opportunities and Challenges Chiplet implementation in general is not a new concept. Back in the 1980s, multiple chipped module (MCM) was introduced and later followed by system in package (SiP) approach. The 2.5D IC interposer implementations appeared around 2008. A couple of years later implementations such as embedded bridge (EMIB) and fan-out wafer level packaging (FOWLP) as integrations solutions were developed. Recently, system like HBM utilizes 3D IC integrations using through silicon via (TSV) approach has been rolled out. The latest evolvement of chiplet implementation focuses on heterogenous implementation and disaggregating SOC. Figure 3 summarizes the development and evolution timeline. Chiplet heterogenous implementation value proposition includes: a. Better Sub System Yield because of smaller silicon die size implementation. b. Shorter Time to Market Development Cycle by using existing proven Chiplets. meptec.org


c. Flexibility to select the best process node for special IP functional features to meet system Power, Performance and Area needs. d. Reduce Development cost by buying known good die (KGD), reusing existing chiplets. The opportunity to materialize these benefits also comes with system challenges. The integration flow will cover both silicon development and to package integration design flow. System considerations, such as holistic thermal design optimization, testing of known good die (KGD) before assembling the heterogeneous system, establishing common process design kit (PDK) and common interconnection interface for a chiplets ecosystem are some of the key areas to tackle. Several organizations from the industry as well as U.S. government programs and standards development bodies have started to establish chiplet ecosystems, such as the Open Compute Project/Open DomainSpecific Architecture (OCP/ODSA) and Universal Chiplet Interconnect Express (UCIe) consortium. One of the challenges in chiplet implementation is to ensure high-speed data transmission between the chiplets. This is because adding an additional chiplet naturally increases the transmission latency. As shown in Figure 4, the interconnect link between the compute die chiplet to chiplet 1 & 2 need to be high speed as well as low latency. In order to enable high speed interconnect link, the link timing uncertainty/jitter must be managed & designed well. These chiplets can be developed by the same company or by different companies. Identifying the underlying critical design factors for system integration optimization is crucial whether it is vertically in-house or horizontally through third-party company collaborative development. Further, defining critical factors allows key design specifications to be defined and to enable a more effective industry ecosystem. 3. A Unified System Timing Uncertainty/Jitter Model In this section, a unified system timing uncertainty/jitter modeling approach will be described. The model objective meptec.org

Figure 4. A Conceptual Chiplet Link Highlights Fast & Low Latency Link Requirement.

Chiplet 0

Chiplet 0

Transmit

Channel

Receive

Figure 5. A Typical Chiplet Connection with Source Synchronous Architecture.

Channel

Figure 6. A Transmit Path Jitter Induced and Jitter Accumulation Path.

is to combine the IO link segments, the transmitter layer, the channel layer and the receiver layer together in terms of the system timing uncertainty/jitter. The timing uncertainty/jitter for each segment will have the underlying contributing factors. By formulating this unified model, the underlying factors are linked to the system performance of interest. While studying

the impact of these underlying factors to the performance of interest, the relative importance of each of these factors can be revealed and quantified. Figure 5 illustrates a typical chiplet to chiplet connection architecture. This is a source synchronous architecture, and it has a source synchronous strobe transmitted together with a set of data lines. It will SUMMER 2022 MEPTEC REPORT | 19


INTEGRATION

be used to demonstrate the concepts. 3.1 Timing Uncertainty/Jitter Modeling: From Transmitter to Receiver through IO link Channel Timing uncertainty/jitter will be induced by different noise sources such as the noise from the clock elements like PLL, the power noise and will be accumulated also the length of the on-die clock tree when the data are transmitted. Figure 6 shows a typical transmit data path architecture. Power-induced jitter will be incurred and accumulated along the on-die clock path and along the pre-driver and driver stage [7]. In Figure 7, a typical clock buffer is shown. The buffer is subjected to power noise and induced jitter to output at each stage. The output jitter will also accumulate from stage to stage. The power noise jitter transfer function is inversely proportional to the large signal gain Gmn and the transfer function has a low pass filter characteristic versus noise frequency [9]. Figure 8 shows a typical jitter transfer function of a single clock tree buffer over the voltage noise frequency. The graphs in Figure 8 & Figure 9 provide several key insights that will be related to the factors that contributes to overall timing uncertainty. a. First, when the noise frequency is below a certain frequency, the powerinduced jitter is relatively constant. When above this knee frequency, the clock buffer will not be fast enough to respond to the noise. The buffer acts as a low pass filter to the high-frequency noise. Itemizing the system noise source block toggling frequencies are critical. The noise tone characteristics will depend on the aggressor activity and coupling profile [10]. b. Also, a longer delay clock buffer will have higher transfer jitter than the shorter delay buffer. The noise tone frequencies, the noise tone amplitude (which is an outcome of power delivery network PDN integrity design), and the clock buffer delay will be considered as the underlying factors to the overall system jitter. The power noise amplitude, which is a function of PDN 20 | MEPTEC REPORT

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Figure 7. General Transmitter Path Clock Buffer Responding to Power Noise.

Figure 8. Jitter Transfer Characteristic over Noise Frequency.

design, is another underlying factor so as the length of the on-die clock tree. c. Source Synchronous Architecture will create a high pass jitter to noise transfer characteristic, which is indicated by the period jitter in Figure 9. The peaking of the transfer is a function of the skew between data path and source synchronous clock/strobe path. This also form another underlying factor for system timing uncertainty/jitter. The jitter-induced and accumulated path in the receiver end is like the transmitter layer. For a source synchronous architecture, the relative jitter at the receiver is referenced to the strobe and the required receiver eye sensitivity is abstracted to the receiver eye mask. The eye mask is the system criteria for passing and failing the specification, as shown in

Figure 9. Source Synchronous Jitter Transfer Characteristic over Noise Frequency.

Figure 10. When a signal is transmitted through a channel media, the channel losses and dispersion also modulate the jitter of the signals propagating through it, as shown in Figure 11. Prior study [11] shows that a linear, passive, and noiseless lossy channel can amplify the signal jitter. A lossy channel has a low pass characteristic, it decays with frequency exponentially as illustrated in Figure 11. The main reason for jitter amplification is the smaller attenuation at the jitter lower sideband than at the signal carrier. This attenuation difference amplifies the phase modulation which is seen as jitter in the channel output signal. Jitter is amplified by the lossy channel at every frequency below Nyquist, and the effect grows exponentially with jitter frequency and data rate. meptec.org


The amplification happens to different types of jitter including sinusoidal jitter, duty cycle distortion, and random jitter. Two separate channel designs were selected to compare the jitter amplification. The amplification difference is a function of the channel stack up and the channel design geometry. Design 1 is a channel implemented in passive silicon interposer [12] and design 2 is using Integrated Fan-Out (InFO) media [13] as the channel. Design 1 is the first design that was improvised by changing dimensions and material to make Design 2. For both designs, the jitter amplification factor vs noise frequency plot for a carrier frequency of 10GHz is shown in Figure 12. 3.2 Combining System Jitter Model Figure 14 shows the combined system jitter model. This model allows a topdown understanding of tradeoffs among the input design factors & the design factors are listed in Table 1. The unified jitter model is used to create output response samples. The response samples will in turn feed into the development of the response surface. This response surface links these input factors together. With that, the sensitivity of the gradient of each input factor to the output response (Receiver Side Effective Jitter) can be understood and the input design factors can be compared to their influences on the outcome. Table 1 includes the input variables that potentially impact the output jitter response. The selection of input variables is formalized by prior experience and knowledge of circuit blocks. The first ten variables are power supply noise amplitudes at multiple frequency tones. These noise frequency tones are harmonics of the switching frequency of the driver and other nearby logic blocks of the controller. Two main power supplies are considered here, the first one is the supply of Tx clock buffer and the second one is a combined power supply of driver and receiver blocks. Variables x1 to x5 are Tx clock buffer power noise amplitude at multiple frequency tones whereas variables x6 to x10 are Driver and Receiver (RCV) power noise amplitude at different frequency tones. Variable x11 is channel meptec.org

Figure 10. Power Noise Induced Jitter and Jitter Accumulation in Receiver End with Receiver Eye Mask.

Figure 11. Channel Jitter Amplification & ISI on Receiving Signal.

Figure 12. Lossy Channel Low Pass Characteristics.

Figure 13. Design 1 and Design 2 Jitter Amplification Comparison for Analysis Study.

jitter amplification factor and x12 to x15 are buffer delays of Tx on die clock, Tx driver, receiver DQS and receiver DQ respectively. The notations for the iteration with any number of input variables will be defined as: xj(i) = value of input feature j in the ith

training example

x(i) = the input of the ith training example m =the number of training examples n =the number of features The unified timing uncertainty/jitter model allows different combinations of design factor perturbation. Figure 15

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INTEGRATION

below captures the simulation runs and the outputs are the system timing uncertainty/jitter. The output amount difference will feed into the procedures described in the next section. 4. Key Input Factors Profiling and Sensitivity Read Out Methodology Response Surface Methodology (RSM) provides the benefit of producing a polynomial regression model which allows the electrical designers to statistically explore the solution design space. By varying the input variables listed in Table 1, an RSM-based design of the experiment matrix was created. The power supply noise tone amplitude variables were varied from 0 to 20% and the Buffer delay variables are varied +/-30% from their default values. The combined system jitter model described in the previous section is used to simulate each entry of Design of Experiment (DoE) matrix to get an actual output jitter response. The DoE matrix with a combination of input variables and their simulated output jitter response, is used to fit a model. A list of input variables and their interactions, as per their significance in the prediction of the output response, is presented in Figure 16. Individual input variables, x1, x2, and the interaction between input variables x3 and x8 show the maximum significance to predict the output response. As itemized in Table 1 input variables x1, x2 are noise amplitude values of the Tx clock buffer power supply at two different frequency tones Frequency 1 and Frequency 2. Input variables x3 and x8 are noise amplitude of a specific noise tone Frequency 3, on Tx clock buffer power supply and Driver & RCV power supply, respectively. This case study specifies that for the given design modifications the channel is not a limiting factor. Effect summary in Figure 16 quantifies the significance of channel design selection variable, over output jitter response, which is three to four times less than the logarithm of the Worth value (“LogWorth”) compare to the supply noise amplitude. The prediction profiler shown in Figure 17 is an interactive graph to show the relationship between input variables and output jitter response based on the fit 22 | MEPTEC REPORT

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Figure 14. Combining Induced Jitter & Accumulation.

Table 1. Input Design Factors of Considerations. *Assuming the Tx Driver Voltage Rail and Rx Receiver Voltage rails are connected.

Figure 15. Combined System Jitter Model Run [14].

model. A prediction profiler can be used to select and tune input variables to achieve desired output response. For this case, the design can be constrained to have a maximum amplitude of power noise at a specific frequency tone to achieve the required output jitter.

Figure 18 presents the surface plot of output jitter vs input variables x1 and x2. The surface model shows the degree of the dependency. The steeper the slope, the stronger dependency of the input variables to the output.

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5. An Empirical Case Study The system sensitivity analysis was applied to a case study of changing the channel media from interposer to InFO channel. Based on the effect and worth analysis, the impact of the channel media was less than 3 times the top design factors. If the other factors were kept being the same, the overall performance would be similar. Two system performances, one with interposer and the other with InFO channel were compared. In this case study, the other design factors are kept the same. The results are in Figure 19. The two-dimensional eye shmoo shows that the eye margins are within 1 % of the unit interval (UI) at the reference voltage (Vref) between the two systems. Even though the shmoo shapes are different, the change of the channel media (for this case study) does not negatively impact the performance at this Vref level. The overall performance was very similar as predicted by the effect summary analysis. 6. Summary and Conclusions Implementing a Chiplets System provides additional system benefits than traditional monolithic SOC approach. However, integration of a chiplets system will also create challenges. Identifying the key design factors and optimizing these factors are important to successfully development. A unified system timing uncertainty/ jitter model is presented in this article. The model forms the basis to analyze the relative significance of each of the underlining design factors. The unified system jitter model was correlated with experimental data. The model correlation reaches a reliable result. Then, the unified system jitter model was used to generate different training samples for response surface modeling. The sensitivity and the effect of the design factors were quantified. Based on the effect and worth summary table, the system design tradeoffs and impacts from the design factor of concern can be assessed holistically. A case study showed the methodology application and the empirical measurement lined up with the assessment. This methodology systematically meptec.org

Table 2. Input Design Factors Generation of Training Examples.

Figure 16. Input variable effect summary.

Figure 17. Input Design Factor Influence Profile.

quantifies the significance of each design factor and provides a systematic way to specify key design factors. Because Chiplets can be implemented by different third-party vendors, a better understanding and definition of the key design factors for specification is necessary to improve design collaboration. ◆

Acknowledgements The authors would like to express their gratitude towards Jennifer Wong, John Schmitz, Chong Ling Koh, and Ajay Kumar for their valuable discussions, encouragement and support.

SUMMER 2022 MEPTEC REPORT | 23


INTEGRATION

Author Biographies Hing Y (Thomas) To (SM’11) is a Fellow in AMD focusing on System Memory Platform Architecture Development. Prior to AMD’s acquisition of Xilinx, Thomas was a Distinguished Engineer in System Memory Signal Integrity group. Before joining Xilinx, Thomas was with NVIDIA Advanced Technology Group focused on highspeed circuits & system channel designs. Before NVIDIA, Thomas worked for Intel for more than 16 years covered and led many different types of system memory IO development. Thomas received his PhD degree in Electrical Engineering from the Ohio State University in 1995 and he is the inventor of over 38 patents in the fields of mixed signal IO circuits and system memory configurations as well as high speed clocking for highspeed memory designs.

Figure 18. Response Surface Captures Output System Jitter.

Nitin Srivastava is a Senior staff Engineer in System Memory Signal Integrity & Device Power Group in AMD Singapore. Previously he worked at INTEL, India and SAMSUNG, South Korea for a total of 11 years, primarily on signal integrity and power integrity of parallel and serial interfaces. He received his M.S. degree in electronics and communications from Manipal University, Manipal, India, in 2009. His research interests include SIPI and heuristic analysis of high-speed designs and systems. References

[1] Victor Peng, “Adaptive Intelligence in New Computing Era”, IEEE ISSCC 2021 Keynotes.

[2] Prasun K Raha, et.al., “A Verstile 7nm Adaptive Compute Acceleration Platform Processor”, IEEE ISSCC 2020.

[3] Dr. Lisa Su, “Cost per Yielded mm2 for 250mm2 die”, IEDM Keynote Presentation 2017, Dec 2nd to 3rd 2017.

[4] Herb Reiter “IEDM 2017 Looks Way Beyond Moore’s Law”, Jan 3rd, 2018, IEDM 2017 Looks Way Beyond Moore’s Law (3dincites.com) [5] Kenneth Flamm, “Measuring Moore’s Law: Evidence from Price, Cost, and Quality Indexes”, Nov, 2017.

[6] Mike Wissolik, et.al., “Virtex UltraScale+ HBM FPGA: A Revolutionary Increase in Memory Performance”, Jul 15th, 2019, Virtex UltraScale+ HBM FPGA: A Revolutionary Increase in Memory Performance (WP485) (xilinx.com)

[7] Xiaoqing Wang, et.al., “On-Die supplyinduced jitter behavioral modelling”, Oct 27-30th 2013, IEEE 22nd Conference on Electrical Performance of Electronic Packaging and System.

24 | MEPTEC REPORT

SUMMER 2022

Figure 19. System Jitter Shmoo Comparison between Channel Implemented by Interposer and InFO. [8] Heegon Kim, et.al., “Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains”, 7-11th Aug 2017, IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMI).

[9] Hyo-Soon Keng, et.al., “Analysis of power supply noise induced jitter of I/O subsystems with multiple power domains”, 5-7th Oct 2020, IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems. (EPEPS) [10] Hing Y. “Thomas” To, et.al., “Top-Down Jitter Specification Approach for HBM System Optimization”, Jan 2019 Design Con 2019. [11] Fangi Rao, et.al, “Mechanism of Jitter

Amplification in Clock Channels”, Jan 2014, Design Con 2014.

[12] Tom Dillinger, “Highlights of the TSMC Technology Symposium 2020”, https://semiwiki. com/semiconductor-manufacturers/tsmc/290560highlights-of-the-tsmc-technology-symposiumpart-2/

[13] TSMC InFO technology Overview, TSMC Technology Symposium 2020, https://www.tsmc. com/english/dedicatedFoundry/technology/InFO

[14] Hing Y. “Thomas” To, et.al., “Holistic Power Supply Induced Jitter Accumulation Response Surface Modeling for HBM Chiplet Interconnect System”, Oct 2021 Design Con 2021.

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