MEPTEC Report Summer 2022

Page 14


On the Road to Chiplets – New Opportunities Emerge with 3D IC Multi-die System Design Dr. Ming Zhang, Distinguished Architect Synopsys

DISRUPTIVE CHANGE IS AT HAND in the semiconductor market. Every year, greater functionality is being jammed into chips of every conceivable size, yet fabrication costs and complexity remain sky-high. Today’s designers must consider the most effective way to grow chip size, speed, and capabilities to meet their specific requirements, particularly for advanced segments like artificial intelligence (AI) and machine learning (ML), high-performance computing (HPC), and mobile devices. There has already been an evolution in play, from design with schematics in the 1980s to hardware description language (HDL) in the 1990s and intellectual property “blocks” (IPs) in the 2000s. Now many leading companies are leaning on design with a system of “chiplets.” Today’s big transition is from designing a system on chip (SOC) to a system of chips, triggering a disruptive transformation in the industry. The trend is taking monolithic chips and building them with a more modularized approach, turning to advanced packaging to aggregate chiplets to optimize functionality. “Successful 3DIC Multi-Die Silicon System Design Using Synopsys 3DIC and Ansys Multiphysics Analysis” was recently presented in May at the MEPTEC Road to Chiplets – Design Integration virtual event. The presenters Kenneth Larsen, director of product marketing at Synopsys, and Marc Swinnen, director of product marketing at Ansys, covered these timely topics in depth as they outlined the advent of multi-die system design using Synopsys’ 3DIC solution and Ansys’ multiphysics analysis to build and leverage chiplets more efficiently. The Rise of Chiplet-based Solutions Integration is the key driver in the 14 | MEPTEC REPORT


innovative move to a system of chiplets. Designers can break large designs into smaller parts, then re-integrate them into a new system. This results in a smart system design where each of the parts can be optimized in the node that is providing the best performance and cost, says Larsen. “The process of disaggregation of chips takes a large SOC and breaks it down into smaller, more manageable pieces.” This process is motivated by lowering costs and raising system yield. The need for chiplets spans multiple customer segments, including computing and storage, communication, and automotive. Chiplets provide a range of benefits, including: 1. Better yield with smaller dies and an opportunity to build larger systems 2. Significant savings and lower costs from optimal chiplet technology

3. Chiplets can be reused, targeting many different markets and products 4. Lower system power while increasing throughput of the system itself Larsen reports that the industry has grand ambitions to eventually get one trillion active transistors on a single package in the next iteration. Synopsys and partner Ansys are focused on helping the market realize that goal. The Next Leap in IC Design – 2.5D and 3D The next big step in IC evolution is 3DIC, which takes advantage of the vertical dimension for even denser circuits and even faster interconnections. Stacked 3DICs contain multiple dies stacked, aligned, and bonded in a single package, using through-silicon vias (TSVs), bumps, and hybrid bonding techniques

Figure 1. 3DSOC Image credit: Synopsys

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