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A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 25, Number 2

Road to Chiplets: ARCHITECTURE July 13–14, 2021 page 10


Everything’s Coming up Chiplets at the 2021 Global Business Council page 11

Adding Value with Unit Level Traceability (ULT) in Automotive Packaging page 19

Interview - Catching Up with Dave Armstrong page 23



UP FRONT California has officially “reopened” just as the summer heat has arrived on the West Coast.


CALL TO ACTION 90% of FPGA device makers seem to be accepting the status quo – casting their lot with a single source subcontractor.


MEMBER NEWS from Gel-Pak, Dyconex, Apex Microtechnology, Finetech, JCET, Infineon, MST, Analog Devices and more.


COUPLING & CROSSTALK Most companies will permit increased, but lower than prepandemic, levels of travel and conference attendance.



UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Ron Jones

Contributors Adam Cron Synopsys Stephen Crosher Synopsys

Summer ‘Road Trip’! Ira Feldman Executive Director, MEPTEC

California has officially “reopened” just as the summer heat has arrived on the West Coast. Things are heating up – literally and figuratively – as we all contemplate the new normal now that major Covid-19 restrictions are behind us. Different people and organizations are thawing at different rates so it will take some time for everyone to establish their new routines. Summer is usually a time for a vacation, especially for those with children who are in a school summer recess. With everyone craving a change of pace, but perhaps not wanting to commit to long haul flights, classic road trips appear to be the way to go. MEPTEC is joining in on the fun with a road trip of our own! The Road to Chiplets series has just been launched as a mix of virtual and in-person events that will be held over the next year. These events will be focused on the practical aspects of designing, implementing (packaging), and testing Chiplets as this cross-functional knowledge is critical to transitioning such devices from science projects to commercial reality. We hope these events will serve as a roadmap as we all explore this new frontier of integrating multiple die smaller than complete “standalone” semiconductor devices (i.e. Chiplets) using advanced packaging. Road to Chiplets – Architecture is first up and will focus on the highlevel decisions that need to be made to implement a product using a Chiplet approach. It will be held as a free virtual event on July 13 and 14 and you can see the great agenda at Join us for the start of this road trip and register today to not miss it! 2021 is off to a good start and we hope it is an even better year for everyone. Do share your suggestions and feedback as to how MEPTEC can best serve you. And don’t be shy!

Ira Feldman Feldman Engineering Corp. Martin Hart TopLine Corporation Vineet Pancholi Amkor Technology, Inc. Herb Reiter eda 2 asic Consulting, Inc., Retired

MEPTEC Report Vol. 25, No. 2. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For nonmembers, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.

Stay safe and healthy! Ira Feldman Executive Director, MEPTEC +1 650-472-1192



Does the FPGA Industry Face Peril? Pt. VIII Martin Hart TopLine Corporation

IN CASE YOU MISSED IT, A 6000 WORD editorial titled “Call to Action” published in the past 7 issues of the MEPTEC REPORT described the peril facing the aerospace and defense industries, which can be summarized as thus: Ninety-percent of the Free World’s component makers of defense grade and radiation hardened (RADHARD) FPGA devices rely on a single source subcontractor to perform the final assembly step involving solder column attachment. Lack of an Ordinary Fastener Can Disrupt the Supply Chain Concerns over a diminishing supplier base are ongoing. Think of a scenario involving a disruption in the supply of solder columns for FPGA devices in the same way that a production line can be shut down due to a lack of a specific type of fastener such as a screw, nut or washer. Today, a single source vendor (Six Sigma) provides solder column attachment services to nine out of ten FPGA device makers. As a consequence, this production choke point could disrupt delivery of FPGA devices to downstream customers. Liquidity Post-retirement Let’s take a deeper look into an important factor that could cause industry disruption of FPGA deliveries. Generally, owners of privately-held, single source companies seek ways to achieve liquidity prior to retirement. Business continuity is a common problem that most small company owners face. Often, the owner’s net worth is tied to an asset in the form of common stock in the company that they founded. Owners of privately-held companies have limited avenues to cash-out before their retirement. After working decades to build a successful business, typically founders will sell their company to the highest bidder. Often, we think of business disruptions being caused by unplanned natural disasters such as fire, flood, earthquakes, and the like. However, interruptions caused by planned (man-made) events such as the selling of a business can be disruptive as well. 4 | MEPTEC REPORT


Stakeholders It is unclear what influence the FPGA industry and all associated stakeholders, including the DoD, have over the eventual sale of America’s sole subcontractor to attach solder columns. The Committee on Foreign Investment in the United States (CFIUS) has authority to unwind a transaction under certain circumstances. It is uncertain what role industry stakeholders could affect in case the controlling owner of a single source supplier dies or becomes incapacitated without heirs willing to continue the business. If all goes well, this subcontractor’s founders will earn a handsome profit that will provide them with a comfortable retirement for years to come. Post acquisition, new ownership must find a way to retain the process know-how in order to continue providing quality column attachment. Potentially, operations could be relocated to new facilities, which might cause column production to be delayed during the transition. As a consequence, the new owners may need to raise prices for column attachment services to offset the cost of buying the company. As a single source, Six Sigma runs unchallenged because there is no free-market competition discouraging price increases. A doubling in the price of column attachment services might raise the price of an individual defense-grade FPGA device by several thousand dollars. While the transfer of ownership of Six Sigma to an unfriendly foreign controlled entity is unlikely, it could suddenly put into motion a series of events that negatively affects the entire defense and aerospace supply chain. Single source suppliers have a degree of freedom to affect the industry that precludes a level playing field. For a number of reasons, the acquirer may downscale production, disrupt a level playing field by selectively favoring certain customers, move the facility overseas or simply be unable to offer column attachment services with the required level of quality. There may be no easily found remedy

assuring continuity and resiliency if any of the aforementioned scenarios come to pass. Delays to Qualify Alternative Subcontractors Starting from scratch, it might take years for alternative column attachment subcontractors to secure certification by the Defense Logistic Agency (DLA). In March 2020, after the commencement of COVID-19, travel by DLA employees to conduct facility audits was shelved. Due to a growing backlog, it may take 2 years, or even longer, for DLA to conduct QML38535 audits and to certify subcontractors for column attachment. Summary 90% of FPGA device makers seem to be accepting of the status quo by casting their lot with a single source subcontractor. The main reason for inaction that is cited by FPGA device makers is the lack of funding to qualify another supplier. The cost could be a few hundred thousand dollars to qualify alternative subcontractors to provide column attachment services for each FPGA device. Conversely, the cost of inaction may exceed hundreds of millions of dollars. Solder column attachment is the “Achilles Heel” in the assembly process of defense grade FPGA devices. Fortunately, alternative subcontractors such as VPT Components and Micross Components have experience attaching TopLine-made solder columns. Golden Altos is developing plans to provide column attachment services. A few FPGA makers are taking steps to vertically integrate column attachment under their own control. Conclusion Measures can be taken by government and industry to avoid a sudden shortage of mission critical FPGA components to keep warfighters flying. Affirmative steps to elevate the priority in securing and qualifying a second source capability to attach solder columns should be taken now rather than waiting for disaster to strike. ◆


MEMBER NEWS Gel-Pak Collaborates with Bae Systems On Innovative Packaging Solution for Thin Semiconductor Devices

GEL-PAK, A DIVISION OF Delphon and leading manufacturer of protective device carrier and film products for the semiconductor and optoelectronics industries announces its collaboration with BAE Systems on an innovative new product called the Lid/Clip Super System (LCS2™). The patent pending LCS2 product is designed to prevent thin semiconductor components from migrating out of the pockets of waffle

pack chip trays during shipping and handling. “The new LCS2 product has the potential to save semiconductor manufacturers millions of dollars in costs associated with yield loss, rework labor and RMA’s caused by die migration” said Darby Davis, VP of Sales and Marketing for Delphon. Shipping today’s thin semiconductor die in industry standard waffle packs presents a challenge for

many semiconductor manufacturers. Thin devices packaged in these chip trays have a tendency to migrate, causing costly Component-OutOf-Pocket (COOP) damage to occur. Together Gel-Pak and BAE Systems studied the root causes of COOP and created this unique solution. The LCS2 product, designed to work with industry standard waffle pack trays, consists of pad and interleaf materials integrated into a static dissipative gold lid along with a highly engineered single piece clip that uniformly compresses the tray and lid together to seal each waffle pack pocket. This lid/lip system has been shown to eliminate thin die migration issues. For more information visit ◆

Sensry GMBH and MST Group Enter Strategic Long-Term Cooperation SENSRY GMBH (SENSRY) AND MICRO SYSTEMS TECHNOLOGIES (MST GROUP) have announced the entering of a strategic long-term cooperation using synergies between and interests of both companies to grow together in the Internet-of-Things (IoT) market. Sensry and MST Group intent to cooperate in the areas of semiconductor systems design, development, assembly, interconnect, packaging, SMT processes and electrical test of IoT solutions developed by Sensry. The packaging needs inherent in the Sensry business model with an universal sensor platform solution kit are widely covered by the service offer and philosophy of the MST Group. “We are proud to have MST Group as development partner and volume manufacturing supplier for our highly flexible IoT solutions for our customers. As we are specialized to build customized solutions with multiple sensors, communication concepts and form factors based on leading edge technologies, the MST Group is a perfect addition to our

turing network.”, said Konrad Herre, CEO of Sensry, and added speaking for both partners: “With our cooperation we support the growth of Semiconductor Industry and the related Supply Chain in Europe, by easing customer access to the IoT market field, shortening timeto-market, and offering “Security Made in Germany” products at reasonable prices.” Christian Rössle, President Sales & Marketing of MST Group, commented: “We are delighted to join forces with Sensry and to offer our “One-Stop-Service” capabilities to IoT module customers, in many different industries, from our high-end semiconductor packaging facility in Berg, Germany. Our partnership approach comprises semiconductor packaging based on our inhouse PCB and IC-Substrate manufacturing, and electrical test services, joint package development projects from samples to volume manufacturing, the programming and calibration of sensors, logistics for wafer, chip, component, and subassembly storage, marking, labeling, packing and drop-shipment to Sensry customers.” ◆


Driven by leading-edge customers over the past 30 years, DYCONEX has continuously been at the forefront of developments in printed circuit board (PCB) manufacturing, and has repeatedly set important technological milestones, beginning with the introduction of high-reliability rigid-flex multilayer boards (DYCOflex®). Today, DYCONEX is the world’s leading manufacturer of highly reliable, high quality and flexible PCBs for the medical industry, especially for medical implants. Biocompatible interconnect solutions are also one of the company’s strengths.


INFINEON TECHNOLOGIES AG has successfully signed a $1.3 billion US private placement of notes. The proceeds of the transaction will be used to repay existing US Dollar bank term loans related to the acquisition of Cypress Semiconductor. A broad group of more than 40 institutional investors, including almost all investors in Infineon’s outstanding 2016 US private placement, are participating in the transaction. The current transaction consists of four tranches with maturities of six, eight, ten and twelve years. Closing of the transaction and receipt of the proceeds is subject to customary closing conditions. Bank of America Securities and Mizuho acted as Joint Lead Agents on the transaction.





Apex Microtechnology Receives Patent for Thermally Conductive Electronic Packaging


AEHR TEST SYSTEMS has announced it has received a $2.9 million follow-on order for a FOX-XP™ Wafer Level Test and Burn-in system and multiple WaferPak™ Contactors from its lead silicon carbide customer to provide additional capacity for production test and burn-in of the customer’s line of silicon carbide devices. This system is expected to ship during Aehr’s current fiscal first quarter ending August 31, 2021.



AXONICS MODULATION TECHNOLOGIES, INC., a global medical technology company has announced it has entered into a strategic alliance with Micro Systems Technologies (MST), a leading manufacturer of medical microelectronics. This strategic alliance expands Axonics’ relationship with MST, with the parties collaborating on the nonrechargeable SNM device Axonics has developed and anticipates bringing to market following FDA approval. Raymond W. Cohen, chief executive officer of Axonics, commented, “As Axonics develops new SNM embodiments for the benefit of patients suffering from bladder and bowel dysfunction, working with an experienced, best-inclass contract manufacturer with proven implantable device experience and the ability to rapidly scale is critical to support our longterm growth objectives.” ◆


APEX MICROTECHNOLOGY INC., A HEICO company and industry leader in high power analog devices, is pleased to announce the expansion of its patent portfolio through the successful filing of its 16th patent, titled Thermally Conductive Electronic Packaging. This patent includes novel apparatuses and methods for configuring a circuit board to contain a plurality of die having different bottomside electrical potential. The apparatus itself consists of a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. In this package, each of the two output die is coupled with a respective metallic pad, with the first die configured to exhibit a first bottom-side electrical potential, and the second die configured to exhibit a second bottom-side electrical potential. This apparatus’s ability to maintain excellent thermal conductivity is achieved

through its configuration - the metallic base plate, the thermally conductive dielectric, and the metallic pads allow for heat to be conducted away from the plurality of die. This novel packaging is integral to the protection of certain power amplifiers, such as Apex Microtechnology’s PA164 and PA165, where the superior thermal conductivity of the package enables these products to expand upon the previous boundaries of power output. Looking to the future, Apex Microtechnology will continue to research innovative analog and mix-signal solutions in the field of power electronics as we strive to enable, advance, and accelerate the development of complex electrical systems. The patent grant notification was issued on March 23, 2021 by the United States Patent Office (USPO). More information is available at https:// ◆

Analog Devices Completes Allocation of Semiconductor Industry’s First Green Bond ANALOG DEVICES, INC. has published its 2020 Green Bond Report, which provides an update on the full allocation of the proceeds from its inaugural green bond offering, which closed on April 8, 2020. ADI allocated nearly $400 million to the development of eco-efficient products for its customers and green buildings and renewable energy for its operations. “At ADI, we are putting our great engineering minds and resources behind tackling some of society’s greatest threats, especially climate change. In support of this, ADI completed the semiconductor industry’s first


green bond offering last year and invested the nearly $400 million in proceeds in transformational, energy-efficient technologies and greener buildings at our corporate campus,” said Vincent Roche, President and CEO of Analog Devices. “While our work is far from done, the progress we have made is representative of the immense impact we can have on the world around us. We will continue to act urgently and identify new, innovative ways to help mitigate climate change and environmental destruction, and their effect on communities globally.” As of May 1, 2021, net

proceeds of $394.6 million from the green bond offering have been allocated over several projects The project categories for the green bond offering were designed to advance the United Nations Sustainable Development Goals. Additionally, ADI’s green bond framework was reviewed by Sustainalytics to ensure that it aligns with the four core components of the Green Bond Principles 2018. More information on ADI’s sustainability initiatives can be found in ADI’s 2020 Corporate Responsibility Report published earlier this year. ◆

Henkel Invests in Technology Start-up ioTech

HENKEL ADHESIVE Technologies strengthens its capabilities for innovative electronics solutions by investing in ioTech, a UKbased start-up with an R&D footprint in Israel. ioTech has developed a disruptive Continuous Laser Assisted Deposition (C.L.A.D.) technology that enables the further miniaturization of a variety of applications in the electronics industry. With the investment, Henkel aims to drive synergies between its customer demands and its material solutions, laser jetted with ioTech´s disruptive technology. “We are scouting for novel and scalable technologies complementing our existing portfolio in adhesives, sealants and functional coatings”, explains Paolo Bavaj, Head of Corporate Venturing, Adhesive Technologies. “Electronics is among our core markets where we are supporting our broad customer base to strive with innovative solutions enabling higher performances, new functionalities and improved efficiency. We are convinced that ioTech’s technology will perfectly complement our existing materials portfolio, drive the

further miniaturization in the industry and provide value to our customers. We also aim, in collaboration with ioTech, to unlock further opportunities for innovative mass-manufacturing applications across Henkel´s large customer base.” Founded in 2016, ioTech has developed an extremely fast, precise and unique noncontact deposition technology for almost any material as an open system. The nozzle-free laser jetting system enables high-resolution printing for up to six different materials at the same time, including polymers, metals, ceramics and bio-based materials. The speed and capacity of the technology allow for mass-manufacturing applications such as semi-conductor packaging and printed circuit boards manufacturing and assembly. Being an additive manufacturing technology, it creates an eco-friendly alternative to many traditional electronic manufacturing methods. For more information, please visit For information about ioTech Group Ltd please visit www.i-o-tech. com. ◆

FINEPLACER® femtoblu - Micro Assembly Cell for Photonics Component Assembly

FINETECH HAS ANNOUNCES THE latest addition to the FINEPLACER® family, the FINEPLACER® femtoblu die bonding system. This automated micro assembly cell is an efficient and economical solution for dedicated photonics production. These demanding applications will benefit from a placement accuracy of 2.0 µm @ 3 Sigma and ultra-low force bonding capability down to 0.05 N. Designed for prototyping and highyield production duties, the system supports all bonding technologies specifically required for the assembly of e.g. Silicon Photonics and photonic/ optoelectronic components in the field of data and telecommunications, high power lasers and other industrial semiconductors, as well as 3D sensors/ LiDAR for augmented reality, automotive applications and many more. Depending on specific needs, the modular FINEPLACER® femtoblu can be individually configured and upgraded infield to support additional applications and technologies. A complete machine enclosure minimizes external influences to ensure a stable process environment and protects the operator against gas, vapor and UV radiation. The FINEPLACER® femtoblu is part of Finetech’s “Prototype to Production” concept. It enables users of manual FINEPLACER® R&D die bonders of the latest generation to get started with fully automated manufacturing of state-of-the-art photonics in a cost-effective and streamlined way. Learn more about the FINEPLACER® femtoblu at ◆ 8 | MEPTEC REPORT


Accelerating its Globalization, JCET Completes Acquisition of ADI’s Singapore Test Facility

JCET GROUP, A LEADING GLOBAL provider of integrated circuit (IC) manufacturing and technology services, has announced that it has officially completed the acquisition of Analog Devices Inc.’s (“ADI”) Singapore test facility, with its test staff to be transferred to the JCET operations team in the near future. Details of the sale were not disclosed. JCET was one of the first providers of packaging and test manufacturing services in Singapore, and the acquisition of ADI’s Singapore test facility will further enhance its market competitiveness. “ADI and JCET’s subsidiary STATS ChipPAC have been working very closely together in Singapore for over more than 20 years,” said Mr. Lid Jian Chiou, Managing Director of JCET’s Singapore subsidiary. “With the success of this acquisition, it once again endorses our Best-in-Class Test Manufacturing and Engineering capacities at JCET and also shows the high level of confidence and trust ADI places in our partnership.” Singapore has been ranked at the top of the Global Innovation Index for several years, and its outstanding innovation system and innovation environment have provided lasting momentum to drive the global semiconductor industry forward. “The semiconductor sector is a key pillar of the manufacturing industry in Singapore, and companies undertake a diverse range of activities here, including R&D and high

value-added manufacturing activities. We congratulate JCET on its expansion in Singapore, which opens up new capabilities in advanced test operations. This is testament to Singapore’s competitiveness as a hub for advanced manufacturing and innovation, and a key node in the global semiconductor value chain. We look forward to partnering with JCET in their next phase of growth and creation of new business and job opportunities in the sector,” said Terence Gan, Senior Vice President and Head, Semiconductors, Singapore Economic Development Board. JCET has been deeply rooted in the Singapore market for a long time and this opens another chapter for JCET in this technology and manufacturing hub. Mr. Li Zheng, Chief Executive Officer of JCET, said, “We are pleased to see that JCET’s subsidiary operation, STATS ChipPAC Singapore, is now fully prepared to receive the factory facility together with an excellent engineering and operational team from ADI in Singapore. We are very appreciative of the great collaboration between our two companies, and we are confident that launching this new project will further enhance our now two decade long partnership with ADI, and will also provide additional high quality test capacity for the global semiconductors industry.” Visit JCET at https://www.jcetglobal. com. ◆

COLUMN COUPLING & CROSSTALK By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Road Trip! The dog days of summer are upon us! This is typically the time of year my family takes a trip traveling to interesting places but this year most of them have been far warmer and hotter than Silicon Valley’s Mediterranean climate. We are home this summer for a mix of reasons. So this column will be my road trip, hitting a mélange of topics with a few detours on the way. Starting a few thousand miles away from the relative calm of Silicon Valley I get news from the crazy state of Florida. My parents tell me it’s a beautiful sunny day but the meteorologists predict a tropical storm or maybe even a hurricane tomorrow. My father as a retired consultant knows many of his neighbors will only believe their eyes and do nothing. He however will listen to the experts and shut his storm shutters tonight! Back home, California has just “reopened” by lifting most COVID-19 related restrictions, but I share with many a “confusion” about the “calendar”. It is not that we do not know the month or the season, but more likely we are just so far out of the normal routines that give us a feeling of time and place. There are plenty of clues – such as the heat of the summer and children being out of school – but our sense of time (and urgency) is off due to the disruptions of the pandemic. Didn’t February feel like it was ninety days long? Coupled with the confusion of the schedule, there is the rush to “get back to the new normal” combined with cautious trepidation about what we can and should do. (Sorry, but some things will be forever changed and will never

return.) Decisions made consciously and unconsciously are totally unique to each person’s situation based on a large array of factors: What is one’s health situation? Vaccination status? Employer rules? Tolerance for risk? Government rules? etc. And as much as we would all like to ignore these and “get on with things,” they are still part of our daily lives. Business “Road Trips”? I have a love-hate relationship with travel. I love in-person meetings with friends and colleagues. A big plus is there are so many things to see and great food to enjoy all over the world! What I hate is the actual mechanics and logistics of travel – the

I foresee a crop of Harvard Business Review articles debating, but never reaching consensus on, the true cost and value of business travel in the next year or two. sitting, the waiting, and the planning of all the details like flights and hotels. Not to mention packing and poor customer service. And I can assure you that with the constant changes and challenges of the last year and a half, things did not improve travel wise. Travel is often a discretionary expense for businesses, especially when there are sales and support teams close to their customers. As has been demonstrated by the temporary elimination of all travel, businesses can survive with travel at a significantly lower level than pre-pandemic. And some have seen their best “bottom lines” ever with the elimination of this discretionary spending. However, the long-term impacts of skipping strategic in-person engagement with one’s customers and co-workers remains

to be seen. Most companies will permit increased, but lower than pre-pandemic, levels of travel and conference attendance going forward. This will require everyone to prioritize which trips are really worth doing. And for those road warriors who crave zipping down the jetway at the last minute, be prepared for greater management scrutiny of your trips even after justifying why the meetings cannot be held virtually. I foresee a crop of Harvard Business Review articles debating, but never reaching consensus on, the true cost and value of business travel in the next year or two. While working from home, many colleagues have found themselves in a never-ending stream of Zoom, WebEx, or Microsoft Teams online meetings. These web calls run from sunrise to sunset and typically back-to-back without breaks. In real life (IRL), this would not have happened as one would often need time to travel to meetings even if just across the building, and social conventions like allowing time for meals at appropriate hours would often provide some breaks. There is plenty of training and bestknown methods to run effective meetings from many sources. Therefore, knowledge on how to hold good meetings is not lacking. What has happened is that individuals have not treated online meetings with the same seriousness as in-person meetings with a “high cost of attendance”. Would you fly cross-country or across the globe for a meeting without an agenda or without being fully prepared? Unlikely. It is also unlikely you would not schedule or otherwise reserve time to follow up on your action items from a high stakes inperson meeting before the next meeting. Clearly many organizations and teams have lost their good meeting discipline and practices. What this demonstrates is a failure of strategy and corporate culture. The strategy failure is due to not establishing and clearly communicating a strategy for the specific project or the operation of the business. Employees then get caught up in meetings without questioning how the meetings align to their activities or how the specific meeting advances the strategic goals of the team. This may be further compounded by the team leads confusing tactics for strategy. (Continued on page 18) SUMMER 2021 MEPTEC REPORT | 9

July 13–14, 2021

Road to Chiplets:


MEPTEC presents the first in a series of cross-functional workshops focused on the practical aspects of designing, implementing (packaging), and testing Chiplets. Join us online for two days of lively discussion of the highlevel “architecture” decisions required to implement a product using a Chiplet approach.

The concept of “Chiplets” - integrating multiple die smaller than complete “stand alone” semiconductor devices using advanced packaging – has firmly captured the attention of the semiconductor industry. The foundational technologies to enable this advanced packaging have been explored in detailed at industry events. MEPTEC through a series of events will cover the practical aspects of designing, implementing (packaging), and testing Chiplets as this cross-functional knowledge is critical to transitioning such devices from science projects to commercial reality. Road to Chiplets – Architecture will focus on the high-level decisions that need to be made to implement a product using a Chiplet approach. Join us at Road to Chiplets - Architecture July 13 - 14, 2021



Everything’s Coming up Chiplets at the 2021 Global Business Council Francoise von Trapp 3D InCites

THE BUSINESS OF PACKAGING MEPTEC events focus on technology with a sprinkling of market information for context. It is important to understand the business aspects as they drive the demand for technology and ultimately determine success. The recent IMAPS Device Packaging Conference and Global Business Council virtual event shared great presentations and discussions providing important context for the recent MEPTEC Supply Chain Security workshop and the upcoming MEPTEC Road to Chiplets series. We very much appreciate Francoise von Trapp’s highlights shared here courtesy of 3D InCites. LEAVE IT TO BILL CHEN, ASE, TO set an optimistic tone for the 2021 Global Business Council Spring Meeting. It was exactly what the packaging community needed to hear. The last time many of us met in person at an industry event was at the 2020 IMAPS Device Packaging Conference and Global Business Council. We had all hoped that by March 2021, we would be gathering again in Fountain Hills, AZ for these co-located events. But that was not to be. The airwaves were crackling with nostalgia as we gathered virtually once again and tried to make the best of it. So when Chen cranked up Bob Dylan’s, The Times They are a Changin’, I could picture us all swaying arm in arm, singing along. The chatbox started filling with comments thanking him for playing it, and what a great song it is… But I’m getting ahead of myself.

Figure 1. Electronics industry forecast. (Courtesy of Prismark Partners)

The Semiconductor Times Are A-Changing In his opening remarks, Lee Smith said that nobody expected the importance digital communications would have on our lives. We will likely remember 2020 as the year the semiconductor industry was brought to the forefront. As scary as last year was, with the pandemic and so much illness and death, Chen pointed out the acts of individual heroism and sacrifice, and collective resilience we’ve displayed. He said the rapid development and deployment of the vaccine demonstrated “tremendous achievements in global collaboration.” Chen presented the semiconductor news of the world, citing TSMC’s impending gigafab in Arizona, nVidia’s acquisition of ARM, AMD’s acquisition of Xilinx, Intel’s IDM 2.0 strategy, President Biden’s inclusion of $50B for R&D semiconductor spending, the White House convening a summit to address the automotive chip shortage and more. All this, he says provides proof of our changing industry landscape that will affect our industry and its eco-economics.

“Technology companies are leading the digital transformation of the global economy and fueling the AI revolution,” said Chen (see Figure 1). He cited a talk, “The Future is System integration” by Prof. Philip Wong, of TSMC, who remarked that as we near the end of Moore’s Law, it’s like coming out of a tunnel into green fields and sunlight. Following Moore’s Law put us on a laser-focused path of miniaturization towards the next node. Coming out of that tunnel brings us into a broader scope, where opportunities for research and innovation abound. Using innovations such as Intel’s EMIB advanced packaging and Foveros chiplet integration, and TSMC’s SoIC, and Samsung’s X-Cube 3D wafer-level integration as examples, Chen showed how chip and system integration are converging in heterogeneous integration (see Figure 2). Die Stacking Update AMD’s Bryan Black, well known for his work with die stacking and on the team that introduced the Fiji processor, SUMMER 2021 MEPTEC REPORT | 11

TECHNOLOGY considers it to be 3D IC integration. He defines heterogeneous integration as using packaging methods to integrate different chips on an organic substrate. The advantage of the substrate vs. silicon approach is time-to-market, flexibility, fewer IP issues, and optimized signal integrity and power.

Figure 2. Chip and system integration convergence.

Figure 3. AMD Leadership packaging. (Courtesy of Bryan Black)

focused his talk, Enabling the Transition to Heterogeneous Integration, on how to move through the challenges he’s seen with AMD products (see Figure 3). Different sources of die in the package are what makes it so challenging, he said. Developing new packaging solutions calls for creating IP for the die in parallel. “Fundamentally, there are endless configurations and complexities. This needs to be managed moving forward with heterogeneous integration,” he said. Eliminating memory interfaces and scaling AMD’s infinity fabric will be needed going forward, he said. Bridge approaches look interesting as we outpace the capability of stitching interposers together. “We’re solving the knowngood-die (KDG) issue by re-defining it as sufficiently good die.” Additionally, we’ll need new ways of testing going forward. Black added that this can’t happen overnight but requires planned migra12 | MEPTEC REPORT


tion over a period of time. Bottom line: “Heterogeneous integration is inevitable. It will be prolific across the industry,” he said, adding that he sees challenges as opportunities to innovate across the industry. Chiplets 101 Unimicron’s John Lau, well-known industry-wide for his years of research in advanced packaging and 3D integration, educated us on the different types of chiplet integration, providing a history lesson of different approaches. He categorizes chiplets into two categories: silicon-based, and substrate-based. He also described the difference between split chips and partitioned chips. (see Figure 4). Chiplets can lead to denser chips, Lau said, depending on the approach and the substrate. Because Intel’s Foveros involves chiplets stacked on an active through silicon via (TSV) interposer, Lau

Speaking of Substrates… Because substrates are such a broad topic, Jan Vardaman focused her remarks on high-performance computing applications. She noted that we are entering a new era of heterogeneous integration that includes 3D and chiplets, and as a result, substrates are increasing in size and layer count to meet the needs of these architectures. As the number of build-up layers increases, we need to add more substrate capacity. While the industry’s substrate capacity is currently constrained, suppliers are concerned about adding capacity because demand could fall and drive prices down. As a result, lead times are stretched out. Vardaman noted that this fear of over-capacity happens a lot in the industry. Today, new production lines for substrates with finer feature sizes cost $300M or more per line. Adding capacity is an expensive solution. The industry needs to come up with alternative approaches such as putting the density in the redistribution layer (RDL) by using an RDL Interposer. This reduces the number of build-up layers needed and improves yield. Samsung talked about this in the IMAPS keynote. Another way to reduce layer count is to use a Si interposer and put the density in the chip-tochip connections. TSMC is implementing this approach with its SoIC. Glass Substrates Santosh Kumar, of Yole Developpement, concluded the Global Business Council meeting with an update on glass substrates. He talked about the benefits of using glass substrates for things like fan-out wafer-level packaging, microfluidics, power packaging, photonics, RF, devices MEMS actuators and sensors, CMOS image sensors, and memory. Kumar predicted a 20% CAGR from $196M in 2019 to 2025 to $ 580M. He noted that CMOS image sensors are still the biggest market, and microfluidics

• Veer Dhandapani, Sr. Director Automotive Package Innovation NXP Semiconductors • Rebeca Jimenez, Corporate VP Advanced SiP Business Unit Amkor Technology • Paul Mescher, Senior Director IC Packaging Technology Microsoft • Devan Iyer, Educator and Executive Advisor Technology Management Together, they put the current situation in perspective, and offered some practical wisdom for how to address the current crisis, while also preparing for the future.

Figure 4. Comparison of substrate-based and silicon-based chiplet solution. (Courtesy of John Lau)

Virtual IMAPS DPC April 2021 panel of industry experts.

is also seeing growth. Lastly, Kumar noted that the number of glass substrate suppliers continues to grow, which will help with adoption as it allows for multisourcing. The Electronics Supply Chain: Is it Broken? It’s been quite a time for the entire electronics supply chain. Here’s what we know. This current strain on chips and substrates was not caused by any one thing. Consider that we’re still in the midst of a global pandemic that has simultaneously catapulted our need for high volumes of chips while impacting lead times for manufacturing and

ery. We’re also all embroiled in the Tech War between China and the U.S. that is impacting our globally integrated industry. Throw in an automotive industry that wasn’t prepared for the slow down caused COVID 19, followed by a rapid rebound, and you’ve got a recipe for potential disaster. At Virtual IMAPS DPC in April, Jan Vardaman went out on a limb to assemble a panel of industry experts to tackle some hard questions about whether our electronics supply chain is broken, and if it is, how do we fix it? These brave souls include: • Ivor Barber, Corporate VP Packaging AMD

The Automotive Electronics Supply Chain Because the automotive industry is at the forefront of the current shortages, Vardaman started her line of questioning here. She asked the panel to comment on maintaining inventory the practice of dual sourcing. Overall, the panelists agreed that dual sourcing has become standard practice, and in some cases “mandatory” particularly in the automotive industry. The greatest benefit of dual sourcing is that it mitigates risks of potential shortage, particularly in the event of natural disasters that might impact a supplier’s ability to fulfill its orders. Mescher noted that dual sourcing works when we’re dealing with products that can be manufactured in tens of million units per year. But if it’s lower volume, it’s a different discussion. Bottom line, the decision for dual sourcing is generally a decision made by balancing the cost, complexity, and qualification of a device. Dhandapani said that for NXPs products that go into consumer products, the company doesn’t dual source. Instead, they have targeted conversations with their suppliers. Jimemez cautioned that in the case of substrate materials, qualification of a new supplier takes time, so doesn’t immediately solve the issue. Additionally, considering the current chip and substrate shortages, it’s difficult for companies to carry enough inventory to meet dual sourcing needs. SUMMER 2021 MEPTEC REPORT | 13

TECHNOLOGY Electronics Supply Chain Inventory Control Inventory control tricky business. The lower the volume of product required, such as mid-range devices for data centers and high-end compute, the more difficult it is to stockpile. At some point, we need to stop making decisions based on the cost/complexity/ qualification balance and think more about the importance of supply continuity. Or as Mescher so eloquently stated. “We’re making decisions that make sense if I was Wall Street, vs. making decisions as if I’m Department of Defense, or the Automotive Industry, where supply trumps pretty much everything.” He says managing inventory is more a matter of accurate forecasting and understanding what needs to be built. Mescher also pointed out that there has always been a “semi-broken conversation”’ in the supply chain, and our current situation is just shedding light on that. People double-book because they don’t know what they will need, then cancel the second orders when they see there will be an oversupply, and that impacts the entire system. The bottom line: unlike the automotive industry. Just-in-time manufacturing doesn’t really work for the semiconductor industry, noted Barber. Right now, while he reports that AMD has a solid stash of chips, they are experiencing a “hand-tomouth” situation with substrates and will use “any that we can get our hands on.” The company is actively expanding its product portfolio to include different types and volumes and is adding supply partners to ensure a consistent supply. Like Barber, the other panelists noted that supply shortages are not impacting their leading-edge chip supplies, but rather trailing edge nodes, and substrates that are impacting assembly and test. Changing the Conversation If anything, this electronics supply chain situation has shed light on the need for different and more consistent conversations between the parties involved. And that’s a good thing. Without stepping on the toes of direct partners, Mescher says he sees “engagement at management levels in background conversations that we’ve never had before.” The goal is to get a better understanding of future needs. 14 | MEPTEC REPORT


Iyer says we need a cohesive and collaborative approach to roadmapping. For example, what needs to be in place at the substrate and design level to support nextgeneration chiplets? Meeting high-speed requirements in a multichip solution is not an easy task for substrate designers. According to Barber, with chiplets, we’re dealing with more layers and larger body sizes, suggesting that we need to look closely at manufacturability and yield to maximize the number of good substrates. Standardizing on panel sizes will make multi-sourcing possible. One positive takeaway for Jimenez is the realization that to keep the entire supply chain healthy, we need more collaboration. Rapid Fire Response to Final Questions: With all the foundry expansion, will we end up with an over-capacity of chips? Jimenez says no. There are other applications besides automotive that are increasing our global chip demand. She says COVID raised our awareness of how much we all depend on technology. Computing, 5G, and the data revolution all are applications that require data storage and memory. Will substrate Capex be able to keep up? Barber said substrate expansions will be slower. But he also said that fab expansion will take time and will not solve the current supply chain issues. Will assembly and test also add capacity to keep up? Jimenez says OSATs like Amkor are also investing to keep up with the growth. What about skilled labor? Opinions were mixed. Jimenez sees the talent shortage as a regional issue, and that there is more available in some areas than others. She also noted that shifting to automation for some jobs will help solve that problem. Dhandapani pointed to the high attrition rate in Taiwan. The strategies used there include overstaffing and working with universities to create a robust college graduate program. He said understanding the geography you’re in is key to attracting and retaining talent.

Mescher said because we’ve made engineer jobs as simple as possible to reduce the possibility of errors, we’ve lost the ability to inspire people to improve skills and make them value a job. Iyer says we need to nurture the talent pipeline. Because of the interdisciplinary nature of advanced packaging, in particular, we need to bring more visibility to it as an attractive career. What will the impact of government investments be to sponsor local infrastructures in the US, Europe, and China to minimize our dependency on Taiwan? Jimenez pointed out that the industry is used to a global supply chain and does not see localization as a replacement for that. Barber explained how the geopolitical concentration of capabilities can cause its own supply chain issues, and that the industry will support spreading the capabilities not because they are anti-oneanother, but because it makes sense to do so. Summing it up Vardaman wrapped up the panel, noting that while we shouldn’t dwell on the problems, there are a lot of issues in the electronics supply chain that will be solved best by better communication between the participants going forward. There is a clear need for better planning. Some suggested solutions included coming up with ways to improve substrate yields, and standardizing panel sizes so that dual sourcing can be supported. While many fabs have taken on the packaging of advanced node devices, they certainly won’t be doing all of it, as the profit margins are still too low. However, as advanced packaging becomes more complex, it’s important to talk about it upfront rather than just “throwing silicon over the wall.” We need to make our supply chain work smarter, and everyone involved recognizes this and is working hard to improve the current situation. Where is the silver lining? The growth supercycle is expected to continue. So, despite the current conundrum, the semiconductor industry is a very good place to be! ◆ To read more news and event coverage about advanced packaging and integration – especially about 3D – please visit 3D InCites at

Conference Technical Tracks Advanced Packaging Flux, Solder, Adhesives Harsh Environment Applications Inspection/Counterfeit Electronics Lead-Free & Low Temp Soldering

Manufacturing Excellence Substrates/PCB Technical Innovations Womens Leadership Program

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Destructive Wire Bond Testing for Development and Production William Boyce SMART Microsystems Ltd.

WIRE BONDING IS GENERALLY considered the most cost-effective and flexible interconnect technology and is used to assemble the vast majority of semiconductor packages. In fact over 15 trillion interconnects are formed by wire bonding each year. With that said wire bonding interconnects have also long been the bane of the existence of many process and manufacturing engineers. The process engineering and development takes extensive effort involving destructive pull and shear testing as well as multifactorial design of experiments. Once the process is developed and released to manufacturing, the manufacturing engineering teams are tasked with the responsibility of keeping the process centered in the process window, also requiring some level of destructive testing. And the irony of destructive testing is that every bond we test does not ship to the customer and the only bonds that we ship to our customer are ones we have not tested. So how is it that wire bonding is still such a robust process to create low-cost and reliable electrical interconnects between microelectronic components and mechanical package assemblies? Perhaps one answer is in a rigorous statistical method of process control. The process of wire bonding is simply the joining of two metals through force and vibration. Thorough wire bond process engineering and development takes extensive effort. Once the design is complete with the wire size, materials, and loop geometry chosen, the next step is to establish a high strength quality weld between the wire and the base metal, commonly referred to as the bond foot. When two metals are joined as is the case with wire bonding, the best way to determine if the weld joint is strong enough and properly formed is through destructive shear testing. In the process of shear testing, a blade is used to shear completely through the wire bond 16 | MEPTEC REPORT


foot to determine the force required to shear through the welded joint. We also carefully examine the failure mode and the remnant left behind after shearing is complete. The maximum shear value can be used to determine if the overall strength is adequate and establishes an objective data point/s for analysis and statistical process methods. The evaluation of the remnant left behind provides evidence of potential weakness in the weld, and ways in which the wire bond weld can be improved. In the wire bond process development effort, destructive wire bond shear testing is still the most valuable tool. Bond Foot

Bond Angle ≈30˚ Example of wire bond showing location of bond foot.

Example of a sheared bond foot. Pull Tester F Bond Heal Bond Foot

Bond Angle ≈30˚ Wire bond pull test configuration.

After the wire bond weld has been properly optimized and dialed into the process window with shear testing, the actual wire loop formation needs to be optimized. This is typically accomplished through destructive wire bond pull testing. Bonding wire is typically provided with a tensile ultimate strength test certification on the wire spool. Using the wire tensile strength one can calculate the theoretical pull strength from the bond and loop geometry. In this case the part under test is secured to the base of the pull tester, a hook placed under the bond wire, and a pull force is applied until the wire fails in tensile load. And again we collect the maximum tensile value to be used to determine if the overall strength is adequate and establishes an objective data point/s for analysis and statistical process methods. The failure mode is also collected to insure that we fully understand such things as the heal formation and wire strength. As is the case any time we join metals, the weld joint should always be stronger than the components being joined. So we should never see a wire lift off the bond pad or see the plating (if the pad is plated) separate from the bond pad. Because the wire formation of the heal should always be the weakest element of the interconnect, a heal break should be the highest occurring failure mode. Once the product is released to production, manufacturing engineering would use pull testing as a leading indicator of bond tool wear. Keep in mind that the overall pull strength of the bond loop is a function of the loop geometry, not just the tensile strength of the wire. The bond angle determines the overall pull force required to reach the tensile strength of the wire. This is why in some ways, if the loop formation is not tightly controlled, the pull test results can be confounding. Once the wire bond process is fully developed, documented and released to

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WB1 and WB2 Pull Test Data 600

Force (g)

manufacturing, the manufacturing engineering teams are tasked with the responsibility of keeping the process under control. As stated earlier, we cannot destroy every bond with testing, and we cannot develop confidence in the process without testing. So process monitoring and control is typically accomplished through some level of statistical process control (SPC) methods. A testing plan will be established to pull and shear a specific number of wire bonds per lot of material and collect the data in a running chart. This method of statistical process control keeps testing to a minimum, maintains product quality within the process windows, and most importantly alerts the manufacturing engineering team when the process may be wandering out of control. Some manufacturers like to rely on Mil Std 883 for guidance on wire bond pull strength and testing. At SMART Microsystems, we like to use the published wire


Pull Data









300 1


15 22 29 36 43 50 57 64 71 78 85 92 99 106 113 120 127 134 141

Wire Bond SPC Pull Test Data.


strength and analytical data to establish our minimum wire bond tensile and shear strength. Then we use shear testing as the primary objective data for wire bond weld strength, and pull testing for loop formation, loop geometry, and overall formation process health. When products are released to production there is no substitute for rigorous in-process SPC shear and pull testing. For more about SMART Microsystems services visit ◆

William Boyce is the Engineering Manager at SMART Microsystems. He has served in senior engineering roles over the last 19 years with accomplishments that include manufactured automotive sensors. He is certified in EIT and Six Sigma Green Belt and is an industry recognized expert in Al wire bonding. Additionally, he designed and led the metrology lab and machine shop at Sensata. Mr. Boyce earned a Bachelor of Science in Engineering degree from the University of Rhode Island and has been a member of the IMAPS New England Chapter for over 10 years.

clear objectives and focusing on the results. For contractors and consultants (internal or external) this is typically best done with fixed deliverables for a fixed price. This not only helps clarify exactly what the client wishes to have done and the value of the work, it helps focus everyone’s energies on achieving the results desired versus just putting in effort (“running the clock”). And similarly having specific, measurable, achievable, realistic, with a time frame (“SMART”) objectives for internal resources which align to the overall strategy are essential to well-functioning teams. SMART objectives combined with consultant’s unique tools and knowledge enable consultants to guide the success of the team. Beyond helping to meet strategic objectives, a consultant can assist an organization by providing an unbiased (re)view of the situation. (More than once I have had to tell the emperor they have no clothes. Politely, of course, and always with realistic options.) Finally, the importance of language

and “dog days”. I’ve always known that language matters not only in terms of clear expression of one’s thoughts and information but expressing one’s values. Language can just as easily encourage and praise others as it can subjugate and demean them. As such, I am now double checking the idioms and folksy phrases I like to use. Luckily, the dog days of summer are safe as the phrase is based upon the astronomy of the Sun being in same region of the sky as the constellation Canis Major, the Greater Dog during the hottest part of our year. Now that we have had an armchair summer road trip, let us all get back to productive work online and in-person!

COLUMN (Continued from page 9) (I’ve touched upon this before, and this is always a good difference to keep in mind.) On the culture side: some organizations have attempted to create a virtual office where you and the “big boss” can see your colleagues “working” using their presence at online meetings as a proxy for work. Unfortunately, this desire to see employees in virtual web meetings consumes time which could be used for actual project work. And meetings (virtual or IRL) where people are working on something else on their computers are not effective either. It is far too tempting to multitask – which humans do not do well on a web meeting since we need to stare at our computer screen to attend. Might as well tackle some of the never-ending email or surf the web at the same time, right? Let us all hope that when teams are back in the office people do not continue to confuse being busy for being productive. How to be productive? By having 18 | MEPTEC REPORT


For more of my thoughts, please see my blog As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆


Adding Value with Unit Level Traceability (ULT) in Automotive Packaging Dr. Ajay Sattu, Sr Manager Automotive Product Marketing Amkor Technology, Inc.

AUTOMOTIVE PRODUCT TRACEABILITY has existed in one form or another for several decades. Traceability generally refers to tracking and tracing each component that comprises every sub-system in a car. Traditionally, this has been achieved with direct part marking on mechanical or electronic components, using 1D or 2D barcodes or radiofrequency identification (RFID). Since vehicle recalls are costly, this process was originated to capture the origins of critical components. Recently, manufacturing traceability has evolved from a defensive mindset of ‘minimizing recalls’ to a proactive posture of ‘compliance.’ As compliance mandates increase, so do the associated fines for non-compliance. The Federal Transportation, Recall Enhancement, Accountability and Documentation (TREAD) Act requires vehicle manufacturers to report to the National Highway Traffic Safety Administration (NHTSA) any excursions on the reliability of the components. As a result, manufacturers rely on traceability to keep abreast of gaps in the value chain to meet end user safety requirements. Created for the automotive industry, the functional safety standard ISO 26262 mandates traceability for safetyrelated systems. This requires tracing hardware, software and firmware back to the system-level design, validation and testing. Tier 1 system manufacturers and car manufacturers (OEMs) are the key stakeholders who uphold the ISO 26262 traceability. Semiconductor content in vehicles is on the rise making traceability of components increasingly important. While there’s no specific traceability standard for semiconductor integrated circuits (ICs), relevant work has been done by various stakeholders in the automotive semiconductor supply chain. For

example, the Single Device Traceability Task Force that emerged from the SEMI Collaborative Alliance for Semiconductor Test (CAST) has identified the need for device traceability through the supply chain[1]. This includes not just the traceability of devices but also semiconductor die, lead frames, epoxy, bond wires and printed circuit boards. Two key automotive application segments, advanced driver-assistance systems (ADAS) and electrification, are

Created for the automotive industry, the functional safety standard ISO 26262 mandates traceability for safety-related systems. expected to undergo significant innovation enabling autonomous electric vehicle (AEV) programs at various automotive OEMs. Several mission-critical safety systems are part of these efforts, including electronic stability control, lane departure warning, anti-lock brakes, adaptive cruise control and traction control that can reduce the number of traffic accidents. All of these systems require complex electronic components such as high-speed processors, memory, controllers and sensors to ensure the reliability and safety of a vehicle.

Figure 1. Annual Automotive Warranty Costs. Source: Warranty Week [2]

Considering the complexities of the modern age semiconductor supply chain, which includes fabless design houses, foundries, integrated device manufacturers (IDMs) and outsourced assembly and test (OSAT) suppliers, there is renewed emphasis on unit-level traceability (ULT). From an innovation perspective, the global automotive industry is in a perpetual state of change; while the underlying fundamental principles such as improving quality, reducing costs and optimizing processes can only be strengthened through a strong traceability initiative along the entire supply chain. As an assembly and test partner to automotive IC suppliers, Amkor offers ULT as an added benefit to our automotive assembly and test services. The motivation of traceability from automotive OEMs and Tier 1 suppliers arises from either warranty (field failures) concerns or pre-delivery (0 km or 0 hr) failures. According to one automotive OEM warranty report [2], approximately $40 billion was paid out as claims annually by the car companies over the last 5 years as shown in Figure 1. Note that the payout in 2017 was inflated significantly due to diesel emission scandal of Volkswagen. SUMMER 2021 MEPTEC REPORT | 19


Figure 2. Annual Automotive Warranty Costs Breakdown (Data presented by ELES Semiconductor at Automotive Electronics Reliability Workshop, courtesy of Semiconductor Management at BMW Group[3]).

To further understand the impact of warranty claims and the role of semiconductors, analysis of the estimates from the semiconductor management group at a leading European OEM provides an estimate that for every $1 of warranty costs, nearly 4 cents can be attributed to the failures of semiconductors. While the financial impact is clear, it may also result in reputation loss to OEMs as well as Tier 1 and Tier 2 (component) suppliers and puts significant stress on supply chain management. In the aftermath of a warranty problem, the chip supplier embarks on an eight disciplines (8D) problem solving effort to find the root cause and devise a short-term fix and a long-term solution.

Generally, OEMs require an 8D report in less than 10 days, especially if the failures are safety related. If the failure is related to a semiconductor component, ULT can help quickly pinpoint origins of the failed components. For ULT to be effective, manual processes must be replaced with automated ones, capturing, storing and managing information automatically. A sample ULT system flow is shown in Figure 3. While there is huge demand for traceability, the biggest challenge remains in identifying the protocols for manufacturing data across the supply chain. Formatting such diverse data sets and subsequent communication to all stakeholders is challenging. Amkor’s ULT provides information

from an assembled IC either electrically or using a 2D barcode marked on top of the device as shown in the Figure 4. The data includes die information such as wafer ID, die position (co-ordinates), substrate or leadframe strip information and equipment used for various steps in the assembly and test process. A modified assembly process flow for a leadframe product may include additional 2D laser mark on the leadframe, automated optical inspection (AOI) and openshort testing for robust control. In this approach, 100% manual optical inspection has been replaced with AOI. For the customers whose product is not turnkey, an additional open-short sample test provides fast feedback on maverick lots which deviate from yield targets. As the package moves along the assembly line, a 2D barcode reader verifies whether the strips are in the correct lot and based on processing information from each manufacturing step, final 2D barcodes are laser marked on top of the package. To ensure stringent automotive requirements for complicated products such as system-in-package (SiP), a sophisticated ULT may be required. For example, RFID cards are assigned to each assembly lot to track the product through the assembly process and ensure that the product follows specified manufacturing flow. Prior to mounting components on the printed circuit board

Figure 3. Unit Level Traceability (ULT) System Flow.



Figure 4. Examples of Packages with 2D Barcodes for ULT.


(PCB), substrate is laser-embossed with a unique two-dimensional identification (2DID) serial number for each module. This allows the collection of ULT data at key process steps, providing full traceability of the module assembly. After all the components are placed on the PCB, the units go through the reflow furnace where components are soldered to the board. To verify component placement after reflowing, the units go through AOI where each 2DID is scanned for ULT. The AOI tool inspects solder joints, detects any missing components and verifies accurate component placement. Since the solder joints on ball grid array (BGA) components are not visible, 100% of the units would also go through automated x-ray inspection. Finally, the units go through “open short” tests, where they are individually tested and sorted. At Amkor, ULT services include not just data collection of processes, materials and equipment history but also real-time retrieval and transmission. For automotive customers, the ULT data retention is at least 15 years

compared to 5 years for commercial products. Further, the benefits of ULT are not limited to providing traceability in manufacturing operations but also in shortening product development cycles. Data such as strip map, wafer map, bill of materials and the resulting assembly and test yields, can be datamined appropriately to shorten engineering data turns via data analytics. This type of ULT system ensures that the product meets ‘zero defect’ quality standards while providing real-time access to the manufacturing information with ultimate goals of increased customer satisfaction and meeting compliance mandates. References: [1] device-traceability-and-semis-single device-tracking-initiatives

[2] ww20180816.html

[3] Data presented by ELES Semiconductor at Automotive Electronics Reliability Work shop, courtesy of Semiconductor Manage ment at BMW Group © 2021, Amkor Technology, Inc.


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Catching Up with Dave Armstrong Principal Test Strategist Advantest

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With…” will feature stories from and about our members. Dave Armstrong ( joined the MEPTEC Advisory Board in 2020. This interview was conducted via email and edited for clarity. How does one do a triple major in college? Electrical Engineering (EE), Computer Engineering (CE), and Environmental Science Engineering? Did you have a particular vision of what you wanted to do with this combination? At University of Michigan, I took

classes which were interesting to me, and this is what it added up to. I could have received a master’s for this same amount of study but that wouldn’t have satisfied my curiosity. In the end, this mix of education has proven extremely valuable to me in Semiconductor testing. My dream back then was to do environmental instrumentation. This dream led me to my first job at TRW where I designed analog to digital (A/D) converters. It looks like you joined TRW out of school, where you worked on analog to digital (A/D) and digital to analog (D/A) converters. Were these for defense applications? Anything you can tell us about the application or the special challenges? Do you think any of these are devices or applications are still running?

Keytronic is a keyboard company. What did you do for them? I led their R&D efforts for new devices and technology. I designed two chips for them. One analog, one digital. Both used the then new ASIC design approach. They worked together to scan an array of capacitive keys to signal keypresses to the micro-control unit (MCU).

Dave at University of Michigan: c. 1972 – Dave working on the first MicroProcessor development system (8008 based) at University of Michigan. His goal was to build a analog interface & synthesize music with it.

TRW was an incredible first job. They were one of the first to develop fully integrated converter chips. I had full responsibility to design, simulate, and even layout these parts. One of them was designed into the now-retired space shuttle. I sure hope these parts are still performing well in the systems they are deployed in. Perhaps even more importantly, the techniques we investigated and developed are still being actively utilized today in many converters. For example, I spent many months back then exploring meta-stable states in A/D converter designs. This is a challenge that still plagues both A/Ds and pretty much all flip-flop designs and the methods we developed to test for it are still in use today.

Just how far has world come since the late 70’s in IC design and fabrication? It’s fascinating to see. There are whole companies today doing the tasks that we had do ourselves in order to get our product out the door. For example, we had to develop our own transistor models in order to do the simulations (in SPICE). Also, we designed custom testers at TRW and Keytronic to test the chips we were making. What a great way to learn the basics and how lucky I was to be part of such a fast-changing industry. SUMMER 2021 MEPTEC REPORT | 23

INTERVIEW Are there challenges that you faced then that still plague device designers or test engineers today? I really don’t think that the list of challenges has changed that much. The specifications and constraints may be multiple orders of magnitude tighter but the basic measurement metrics continue. Parameters such as maximum frequency (Fmax), signal-to-noise ratio (SNR), jitter, integral nonlinearity (INL) and differential nonlinearity (DNL), bandwidth, minimum operating voltage (Vmin), power, etc. are all still challenging today. One problem we didn’t really have back then, which has become quite difficult today is inner-team communications. When a small team did both the device design and tester development, we knew what needed to be tested and how to do it. Today, with large teams of engineers in separate design and test organizations the hand-off is much more difficult. I think that this results in both over-testing and under-testing of some aspects of our parts these days. Did you move to Colorado for Storage Technology? How has your area (north of Denver) grown since the late 1970s? Yes, Storage Tech moved me to Colorado. I picked Boulder and then found Storage Tech. I chose Boulder because of the skiing and mindset. One of the things Boulder did years ago was set aside greenspace around the city and limit growth. While the front range has experienced considerable growth, it is not as bad as what other cities in the country have experienced. The newest challenge to this area is new facilities for Google and Apple which have created many more jobs. What was your role at Storage Tech? My first role at Storage Tech was in the design of solutions for telephone systems. My most interesting project was an “echo canceller” which made use of adaptive filtering techniques (this was an early type of artificial intelligence). After a few years, Storage built their own IC fab and I jumped at the opportunity to help grow their internal ASIC capabilities. Here I managed both the product engineering and test engineering teams. Our goal was to have a fully 24 | MEPTEC REPORT


Colorado: c. 1980 – The first time Dave moved to Colorado he lived in the mountains and managed the StorageTek PE and TE teams.

automatic way to generate and update test programs. With a lot of work, we got very close but were not able to fully automate the process. Our higher-level test abstraction was exactly the right thing to do. What really challenged us were the ongoing changes to the underlying test system code from Schlumberger. Full automation like this continues to be the goal for many companies today.

this one-device at a time while focusing on our customers’ needs. My job in Business Development was to work with Advantest’s R&D group to develop what is needed for multiple customers while working with customers to see the value in our solution. I’m just now moving into a new role, Principal Test Strategist. In this new, technology focused role, I am being challenged to develop creative test solutions to meet the hardest test challenges facing the high-performance computing (HPC) industry. In addition to my long-term focus on high-speed input/output (HSIO), I am working on photonic testing solutions and helping pull together AI solutions for our HighPerformance Computing customer base. I’m also working with customers to confront the challenges of high-power delivery inherent in today’s AI devices while deploying a highly responsive DUT cooling approach I invented a few years ago.

I remember when Hewlett-Packard was one of the few, if not the only, technology companies in the Loveland and Fort Collins area with many more technology companies there now. Did HP serve as the catalyst for these other companies or are there other reasons for the growth? Certainly, some startups in both Fort Collins and Colorado Springs are here today thanks to HP.

What was the hardest thing you had to learn about applications and business development in your early days? The hardest thing back then and still today is overcoming obstacles and knowing our limitations. Recognizing hard limits and realistic solutions for a given challenge, and then effectively communicating these to both management and customers while maintaining a positive and supportive attitude is by far the hardest challenge of my job. The good news is that I’ve had the luxury that both HP and Advantest are 100% focused on doing the right thing. Even if some of my recommendations mean less business in the short term, management has consistently valued and supported my recommendations.

What prompted your move to HP and then your later move into Business Development? I had been researching jobs in HP because this had always been my dream company. When Storage Tech started going through yet another cutback in 1984 I literally laid myself off and joined HP. At HP I have always focused my efforts on providing a complete solution to all the challenges my customers identify. A System Engineers (SE) or Application Engineer’s (AE) job is to do

Did you move to Santa Clara, California for a while when you were doing Product Marketing for HP’s automated test business (now Advantest)? The San Francisco Bay Area was and is the heart of the semiconductor industry. It was very exciting to have the responsibility to bring to market what was effectively the first HP digital test solution (HP 82000). Being in the Bay Area was key to our success. The Bay Area is key to being able to quickly introduce a product into many customers and market segments.

You’ve worked in roles as HewlettPackard spun out the automatic test equipment (ATE) to Agilent Technologies and then you joined Advantest prior to Verigy being acquired by Advantest. These have been large changes even though the core products and customers have stayed the same. How would you compare the cultures of these companies? Obviously, all have been global businesses in terms of product divisions and customers, but they clearly don’t all do business in the same way. You’d be surprised by how similar they have been and are. All of them have had a solid quest for excellence and leadership in test. All of them do the right thing. The only real difference I have noted is that some teams and organizations are more open to new ideas than others are. I take this as an opportunity to sharpen my pencil and provide a stronger message around what the need and my recommendation is. Now in Advantest, due to the breadth of products and multitude of focused R&D teams, I have numerous paths available to me to pull together a solution to meet my customers’ challenges. In your role of HPC Test Strategist you must have been very focused on new technology and applications. What is the biggest technology or business jumps that you have seen that really surprised you at the time? How did these turn out? The recent changes in the data center to support highly parallel AI processors is clearly an inflection point. This move is driving I/O speeds (both SerDes and Photonic) and power deliver together with DUT cooling. Developing test solutions for this new breed of device certainly has its challenges. I never expected SerDes data rates to jump to the GHz speed let alone 100s of GHz we do today. Then, looking into the future with photonic interfaces I’m even starting to talk about chips which manage multiple Tbps data streams. I certainly never expected this. In a similar way, I never expected power draw of chips to jump to currents above 1 kA. Surprisingly these power density levels are not just for data-center components but also for edge and

power compute devices for automotive applications. In terms of I/O testing the SerDes ramp has been very successful although there remain some big challenges in test techniques to confirm known good die (KGD) for chiplet integrations. Of course, there is still more innovation needed to meet the need for highpower delivery and corresponding device cooling challenges at these new power levels. I’d say that the biggest challenges are still out there for testing multi-lane photonic devices. Testing many lanes, each with multiple wavelengths on them is going to be a tall order. Here, I don’t think that the industry has even decided where the photonic interfaces must be tested. Developing a photonic test solution for wafer probe will result in a very different set of test capabilities as compared to one developed for use in System Level Test. How has the pace of innovation changed over your career so far? I’m sure that most people think it’s accelerating today. I disagree. We simply have more people working in the industry today so more progress (not innovation) is occurring. True innovation occurs when there is a paradigm shift which affects everything moving forward. For example, transistors-to-ICs, or ICs to general purpose microprocessors, and now general purpose MPU’s to numerically controlled AI engines. What is needed to increase innovation and how much faster do you think it can get? What do you think the ultimate limiters will be? The new barrier to progress is most certainly in software. How do we effectively develop all the tools we need to support us moving forward? How do we effectively program AI toolsets to help us reliably? I believe that semiconductor manufacturing will be largely controlled by AI routines a decade or two from now. To my thinking, the ultimate (and necessary) limiter is conservative design methods which are back-tested with enough data sets so that we can avoid a fatal crash. The challenge here is that we don’t have the all the datasets needed to do all this back-testing. What we have

are experienced professional engineers developing algorithms. What we need are true data-driven methodologies. I believe that our traditional test program content will need to morph and change, just to provide the necessary data so that we can reliably identify failure conditions as soon as possible. Identifying and developing these new test methods. This will certainly limit how fast we can reliably deploy and realize the benefit of AI guided semiconductor manufacturing. Just as cars need a massive amount of data to learn how to avoid accidents, our fab lines will need something similar in order to fine-tune our response to the situations we will run into moving forward. You have chaired the Test Working Group (TWG) for the International Technology Roadmap for Semiconductors (ITRS) and now the Heterogeneous Integration Roadmap (HIR) for more than ten years now. What would you describe as the biggest challenge is for the TWG and the roadmaps? Roadmaps like these need to be tools for the industry. It’s always a challenge to keep them relevant - especially when semiconductor devices and tests continue to evolve rapidly. Some topics get figured out and go away while new challenges come on the scene and need to be explored and road mapped. I’m really proud of what this team has done. For example, eight years ago we developed a model for scan pattern growth over time which has proven to be quite accurate over all this time. With years of solid data behind it, the confidence in the model looking forward has grown. Getting it right is extremely satisfying intellectually, especially when it comes after a team effort involving lots of work by true experts in the field.

ITRS 2011: ITRS Test TWG meeting.



Chamonix: My French “family’s” chalet in Chamonix is where I often head during weekend breaks in my meetings in Boeblingen.

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Dave, thank you for sharing your story with us! We look forward to seeing you on your future travels in the not-toodistant future.


When you are not working, what do you enjoy doing? Travel is certainly #1. My wife and I have a long list of places around the world that we still want to explore. ◆







What have you done during the recent ‘work from home’ period to keep your sanity? Not enough. It seems to me that my meeting schedule has expanded to fill what used to be my time to think (on planes). With meetings going from early morning until late into the evenings I now need to carve out time each day to meditate.








Favorite places to travel to for work and for fun? Europe is very special to me. I lived in France while in high school for a while so going there is like going home. Of course, visiting our plant in Germany is always a great opportunity to both align with the rest of the [now] Advantest 93K team, visit great places, and buy incredible chocolate. It’s even better when I can pop down to France to visit my French “family” of very long-time friends.


You did a substantial amount of travel prior to COVID - roughly how much and to where? Do you see yourself returning to this level of travel? Yes, travel was a major part of my work life for years. Visiting my colleagues in Germany and Japan multiple times each year was critical to solid progress on many of my programs. We have certainly learned a lot about working over Zoom and Webex but this doesn’t replace personal interaction this is especially true with customer conversations. I fully expect that travel will once again become necessary - just

probably not at the same level. For me personally, this is a good thing. :-)


What is it like coordinating the large TWG with lots of very smart, but busy and opinionated volunteers? The volunteers who make this roadmap happen are incredible. I don’t think that we have any problems with “opinionated volunteers”. The respect level among us all is very high. We all know that there are multiple ways to solve most of the challenges we discuss, and we also know that the number of experts world-wide which can discuss these topics with is very limited. Our pre-competitive discussions provide the TWG members an incredible opportunity to “try out” new ideas and receive valuable feedback from true industry visionaries. I sincerely hope the 100+ experts we have today in the test TWG know how much I, and many others in the industry, appreciate them. This effort is extremely rewarding.



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MEPTEC Report Summer 2021  

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

MEPTEC Report Summer 2021  

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

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