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*3121*

3121

(Pages : 2)

Reg. No. : .................................... Name : .........................................

Third Semester B.Tech. Degree Examination, June 2009 (2003 Scheme) 03-305 : LOGIC SYSTEM DESIGN (RF) Time : 3 Hours

Max. Marks : 100 PART – I

Answer all questions. Each question carries 4 marks. 1. Explain the term “precision” and “accuracy”. 2. Represent the decimal numbers 699 and 873 in BCD, and then show the steps necessary to form their sum. 3. Determine the radix r. a) (BEE)r = (2699) 10 b) (365)r = (194)10 . 4. What is a tristate logic ? 5. What are universal gates ? 6. Derive the exclusive - OR/exclusive-NOR circuits for a three-bit parity generator and a four bit parity checker, using an even parity bit. 7. Prove that dual of the exclusive - OR is also its complement. 8. Derive the truth table of an octal to binary priority encoder. 9. Explain sequential circuit. 10. What is a serial adder ?

(10×4=40 Marks) P.T.O.


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3121 PART – II

Answer one full question from each Module. Each Module carries 20 marks. Module – I 11. a) Given the Boolean function F = xy + x′y′ + y′ z

i) Implement it with AND, OR and inverter gates. ii) Implement it with OR and inverter gates iii) Implement with AND and inverter gates. b) Express the complement of the following function in sum of minterms. i) F (x, y, z) = ∑ ( 1, 3, 7 ) ii) F (A, B, C, D) = Π ( 0, 1, 2, 3, 4, 6, 12 ) OR 12. Explain booth multiplication algorithm with the help of a suitable example. Module – II 13. a) Implement the following Boolean functions with an 8 - to 1 line multiplexer and a single inverter. F (A, B, C, D) = ∑ m ( 2, 3, 5, 6, 8, 9, 12, 14) b) Design a combinational circuit that accepts a 2-bit number and generates a 4 bit binary number output equal to the square of the input number. OR 14. a) What are multiplexers ? Design a Multiplexer 4 -bit by 3 -bit binary. b) Construct a 15- to- 1 line multiplexer with two 8- to -1 line multiplexers. Interconnect the two multiplexers and label the inputs such that any added logic required to have selection codes 0000 through 1110 is minimized. Module – III 15. Explain synchronous and asynchronous counters with suitable example. What are BCD counters ? Use D-type flip-flops to design a counter with the following repeated binary sequence 0, 1, 3, 2, 4, 6. OR 16. Construct a 16-bit serial parallel counter using four 4-bit parallel counters. Suppose all logic is NAND and NOT gates and serial connections are employed between the four counters. What is the maximum number of NAND gates plus NOT gates in a drain that a signal must propagate through in the 16- bit counter ? (3×20=60 Marks) ___________________


03-305 LOGIC SYSTEM DESIGN (RF)_0