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[CHAP. 12


Heretofore, the frequency response of a network has been exhibited by plotting separately the magnitude and the angle of a suitable network function against frequency !. This same information can be presented in a single plot: one finds the curve (locus diagram) in the complex plane traced by the point representing the network function as ! varies from 0 to 1. In this section we shall discuss locus diagrams for the input impedance or the input admittance; in some cases the variable will not be !, but another parameter (such as resistance R). For the series RL circuit, Fig. 12-28(a) shows the Z-locus when !L is fixed and R is variable; Fig. 1228(b) shows the Z-locus when R is fixed and L or ! is variable; and Fig. 12-28(c) shows the Y-locus when R is fixed and L or ! is variable. This last locus is obtained from Y¼

1 1 ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi tan1 ð!L=RÞ R þ j!L R2 þ ð!LÞ2

Fig. 12-28

Note that for !L ¼ 0, Y ¼ ð1=RÞ 08; and for !L ! 1, Y ! 0 908. When !L ¼ R, 1 Y ¼ pffiffiffi 458 R 2 A few other points will confirm the semicircular locus, with the center at 1/2R and the radius 1/2R. Either Fig. 12-28(b) or 12-28(c) gives the frequency response of the circuit. A parallel RC circuit has the Y- and Z-loci shown in Fig. 12-29; these are derived from Y¼

1 þ j!C R


R Z ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi tan1 ð!CRÞ 1 þ ð!CRÞ2

Fig. 12-29