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APD+ 17.4 QIR3 新功能介紹 • • • • • • • • • •

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增進鋪銅的效率與品質 DRC改進 模組管理增強 Scribble功能 DFM功能改進 佈線效率提升 3D 顯示功能強化 Silicon Layout Option功能更新 Clarity/Celsius整合功能 Symphony Team Design 功能增強

© 2021 Cadence Design Systems, Inc. All rights reserved.


增進鋪銅的效率與品質 3

© 2021 Cadence Design Systems, Inc. All rights reserved.


GPU Accelerated Rendering • Using GPU to render graphics in Allegro® Package Designer Plus NVIDIA®

o

o o

o

QIR2之前,只有兩個選項: OpenGL 與 non-OpenGL; QIR3新增第三種選項: GPU 需要 SiP Layout or Si Layout Option or Venture license 適用於 Windows and Linux 不適用於17.2 相容模式環境

Operation

Comparing Performance Old graphic engine

GPU engine*

Zoom fit

16 sec

1 sec

Show All Layer

3 sec

0.01 sec

Show/Hide single layer

2 sec

0.01 sec

Panning

1 sec

0.01 sec

Zooming in/out

1 sec

0.01 sec

*Using NVIDIA Quadro® RTX 6000 Augmented Quality of Display

• 使用GPU的優點 o

提升縮放/平移的效率

• Setup ➔ User Preferences 勾選 ‘disable_gpu’ 以關閉GPU功能

Old Graphics 4

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New GPU


GPU Accelerated Rendering

https://youtu.be/N7MTxJhXPl8

Beautiful Speed

*Using Nvidia Quadro RTX 6000 5

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互動效率增強 • QIR3 在 board 與 packaging 編輯環境效率增強的項目: o o

o

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在大型的設計案中,增強重定義與置換 Structures 的運行效率 增強Allegro® Constraint Compiler 對巨量的Pin數與Net數的運行 效率 增強Die-in/BGA-in (APD+ only) 過程的運行效率

© 2021 Cadence Design Systems, Inc. All rights reserved.


鋪銅效率增強 • 鋪銅 o

整板鋪銅效率增強

o

平均效率提升~21%

• FAST鋪銅模式 o

Fast 鋪銅模式首見於 17.42 版 –

‘Fast’ 模式取代 ‘Rough’模式

大幅提升動態銅編輯效率 (slide, add connect, move, etc.)

避銅結果與SMOOTH鋪銅相當類似,保留了連接性 和整體外觀

o

平均效率提升~48%

• SMOOTH鋪銅模式

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o

提升了 etch edit 相關過程的效率

o

平均效率提升~19%

© 2021 Cadence Design Systems, Inc. All rights reserved.


鋪銅品質增強

Voiding 品質增強 • Crosshatch Shape Fill improvement

• Fillet void quality improvement

Pre-QIR3 Result

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© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result


鋪銅品質增強 Voiding品質增強 • Trim void improvement o

• Trim void improvement

Reduction in void spikes at min aperture failures

o

Reduction in acute angles

Pre-QIR3 Result

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Prior QIR3 Result

© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result

QIR3 Result


鋪銅品質增強 Voiding品質增強 • Trim void improvement o

• Trim void improvement

Reduction in min width failures

o

Aperture=3.0 Actual =2.6

Pre-QIR3 Result

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© 2021 Cadence Design Systems, Inc. All rights reserved.

Aperture=3.0 Actual =5.4

QIR3 Result

Reduction in min width/thin protrusion failures


DRC改進 11

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Fillet DRC Control • 在 Design➔Spacing 設定 “Enable Line based check for fillets” 選項,可將Fillet 圖形為Trace的型 態(非 Pad) o

可決定DRC fillets 為 via/pin-to-object spacings 或是 line-to-object spacings

o

默認情況下,fillets 從它們附加到的連接對象繼承spacing constraints (pin or via)

o

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Pin/Via Pad的延伸在fillet 周圍保持一致的距離

新的 spacing option 可切換 DRC 檢查 fillet與 trace 間距的行為

不適用於17.2 相容模式環境

© 2021 Cadence Design Systems, Inc. All rights reserved.

Fillet as Pad

Fillet as Trace


Return Path DRC Check New Adjacent Void Spacing • ‘Return Path DRC’ is designed to ensure proper signal to reference plane adherence and detection of signals crossing voids​ (loss of reference) o

o

Routing/Segment Over Void –

Ability to set length of trace to ignore reference loss less than a specified value (Ignore Length)

Ability to set length of trace to ignore that loses reference due to the Antipad of the Via on the reference plane (Max Pad Gap)

Max Return Path Stitching Via Distance –

o

Ability to specify the distance from the signal net via within which the reference net stitching via must be found

Min Adjacent Void Spacing (New) –

Ability to specify minimum distance of signal net to adjacent void

Available in 17.2 Compatibility Mode •

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Adjacent Void Spacing rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4

© 2021 Cadence Design Systems, Inc. All rights reserved.


DRC Browser Updates • New Constraint Domain view option o

View constraint by Constraint Set view (default)

o

View DRCs by Domain type

o

View selection in DRC Browser Options form

Constraint View

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模組管理增強 15

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模組版本管理與套用

V1 V2 V3 …

V1.mdd

https://youtu.be/5nsr0Vyiw1A V2.mdd

V3.mdd o Modules files (.mdd) could be opened, adjusted and saved as a new variant as required

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置件後直接替換原模組 Placement Edit App Mode option to select a module and replace it with a different variant Replace module for multiple instances; Replace into current location

Module: DDR_TERM.mdd

Module: DDR_TERM_SHAPE.mdd

https://youtu.be/B7WSMnnw93Q 17

© 2021 Cadence Design Systems, Inc. All rights reserved.


Scribble功能 18

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Multi-Pin Scribble Support in Add Connect

先手拉大致 走向

確認後自動生 成實際走線

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Multi-Pin Scribble Support in Add Connect

https://youtu.be/4UJd_jIZnC8

Movie

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佈線效率提升 21

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Parameterized High Speed Structures Differential Pair w/Return Path Enhancements • New prototype to generate High Speed Structures based on parameters first released in 17.42 o

o o o

Create high-speed via transitions with return path vias, route keepouts, and pad entry/exit traces from a variety of available patterns Accessible thru Route>Unsupported Prototypes>Create Structure Requires SiP Layout Option or High Speed Option license Available in 17.2 Compatibility Mode

• Differential Pair Signal Vias o

New canvas selection of pre-existing via transitions seed Padstack, Spacing/Pitch

• New Route Keepout Void Shapes added to Structure Generator for more customized high speed structures in 17.43 o o o

Available keepout shapes: rectangle, oval, rings, goggles, owl Ability to define different keepout shapes and dimensions per layer Ability to define allowed objects (i.e. via, trace, etc) in keepout by layer

Oval 22

Rings

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Rectangle

Goggles

Owl


Layer Based Degassing • Ability to define degassing per layer o

To enable, attach ‘Degas_Layer_Based Enabled’ property to design/drawing level – Not Available in 17.2 Compatibility Mode

o

New Degassing Parameters tab in Shape➔Global and Layer Dynamic Parameters – Global level: Create patterns, add/remove/rearrange patterns for each layers – Layer level: Display patterns assigned to layer, add/remove/rearrange patterns for the layer – Ability to set multiple patterns per layer •

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Allow for multi-pass degassing runs in the order the patterns are specified

© 2021 Cadence Design Systems, Inc. All rights reserved.


Layer Compare Productized in 17.43 • 互動式 Layer Compare o

比對同一個檔案中兩個層的指定區域並且將差異產生在新的層

o

可以在被比較過的層執行 AND, OR, XOR, and ANDNOT 等操作

• 整批式 Layer Compare o

可以使用控制檔對不同的檔案的層順序執行比較 –

方便比較不同版本間的差異

可以用指令模式

• Difference Walker o

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顯示並瀏覽差異處

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Differences

Batch Layer Compare


Align Vias Update User Pick Reference • New ability to select ‘User Pick’ as reference for alignment of vias o

Click anywhere in canvas or use RMB>Snap Pick to

o

Available in 17.2 Compatibility Mode

https://youtu.be/w1U1Uv56tFc 25

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Pin 編號設定更新 Symbol Edit Mode • 可控制適用方案的“Label unused grid positions”選項(i.e. Alpha Horiz, Num Vert; Num Horiz, Alpha Vert, etc) o

QIR3之前的版本, 此選項是被強制勾選

o

當此項未勾選,行為是從左→右獲取每個唯一的 X 值並將每個唯一的值分配給下一個字母;從頂 部→底部的唯一 Y 值行為也相同

o

最適合不規則腳距零件,因此您的pin號不是大而長的字串 –

o

選中該選項後,將為每個唯一的列保留一個標籤

適用於17.2 相容模式環境

PRE-QIR3 26

© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3

Label unused grid positions = checked

Label unused grid positions = unchecked


DFM功能改進 27

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DesignTrue™ DFM Enhancements

Cu defined pad

SM defined pad

Soldermask Via and SMD Pad • Via Soldermask Pad to SMD Soldermask Pad Overlap Check o

Allow Via-in-pad Via mask to SMD mask Overlap –

o

o

Allows the mask of a via contained within a SMD pin to overlap beyond the SMD pin mask boundary • Via origin must be contained within the SMD pin pad boundary

Allow Same net Via mask to SMD mask Overlap –

o

Allow Via-In-Pad Via Mask To SMD Mask Overlap = OFF/NO

Allows the mask pad of a via outside the boundary of an SMD pin to overlap the SMD mask pad • Via origin outside of SMD pin pad boundary

Allow Via-In-Pad Via Mask To SMD Mask Overlap = ON/YES

Requires SiP Layout Option or Venture license Available in 17.2 Compatibility Mode –

Rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4 Allow Same Net Via Mask To SMD Mask Overlap = OFF/NO

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© 2021 Cadence Design Systems, Inc. All rights reserved.

Allow Same Net Via Mask To SMD Mask Overlap = ON/YES


3D 顯示功能強化 29

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3D 顯示功能強化 • 等距視圖現在包括頂視圖或底視圖的選擇

• Realistic Plating Thickness

• 數字鍵盤 “1” 鍵或是功能表 View➔Camera

Pre-QIR3 Result

QIR3 Result

• Increased Model Realism o

3D Canvas and JPEG/PNG Export

Isometric View - Top

Pre-QIR3 Result Isometric View - Bottom

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© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result


Silicon Layout Option功能更新 31

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Silicon Layout Option (SiP230) • 新的 GDSII 驗證 o

GDSII vs Design Verification – 更加確信 GDS 數據與 APD+ 中的相匹配

設計佈局 o

使用者不需具備相關知識或層比較工具 – 工具將提供實際差異數量的報告 – 使用者可用 Layer Compare Difference Walker 瀏覽 差異以評估問題

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© 2021 Cadence Design Systems, Inc. All rights reserved.


Clarity/Celsius整合功能 33

© 2021 Cadence Design Systems, Inc. All rights reserved.


Clarity/Celsius 與 Allegro ICP and PCB 整合 • Customer challenge; transferring and conditioning layout for 3rd party electrical and thermal analysis – –

Complex multi-step process involving IPC2581 transfer or another file exchange format Missing and misinterpreted design data

• Direct launch of Clarity™ 3D-EM from APD+ –

– – – – –

APD+ layout is automatically converted and opened in Clarity GUI Direct, simple transfer of layout reduces cycle time and human error User can select only critical nets or entire layout GUI-driven layout conditioning parameters when passing layout to analysis Side-by-side to review layout and electrical/thermal results Dynamic layout update across APD+ and Clarity

• Direct launch of Celsius Thermal from Allegro PCB and APD+ – 34

Similar benefits © 2021 Cadence Design Systems, Inc. All rights reserved.


Symphony Team Design 功能增強 PA3160 Option license 35

© 2021 Cadence Design Systems, Inc. All rights reserved.


Symphony Team Design 是什麼? o o

o

一個可以多個使用者同時編輯同一個brd 檔的環境 與 design-partitioning solution 差異很大,必須將檔案 切成多個部分並給多個使用者在各自的電腦上編輯, 最後在整合成一個檔案。 Symphony Team Design 需要 PA3160 license

Symphony Team Design Option VS

Design Partitioning 36

© 2021 Cadence Design Systems, Inc. All rights reserved.


支援新的Structures • 在Symphony 中可以創建Structures o

可以經由圖形視窗選擇目標創建structure或是使用參數設定視窗生成 structure

o

在Symphony 中可以Place Structures

o

可以從library中放置或即時創建Structures添加到Server端的database以 供其他client端使用 –

Structures➔Place, copy/paste

• 在Symphony 中可以 Export 所有的 Structures

• 拉線指令 Add Connect 支援動態加 Structure • 按滑鼠右鍵選擇 Unlock 可以編輯 Structure

Route>Structures now Available 37

© 2021 Cadence Design Systems, Inc. All rights reserved.

Create

Place


佈局優化/分享連結 • In-session Component Placement o

圖形化多用戶鎖定,以防止元件放置期間發生衝突

• Share Button o o

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簡單生成Symphony Server的分享連結 按下 Share button, 複製連結給其他的 clients

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http://pcb.maojet.com.tw

T E L : +886-3-271-1599 Mail : sales@pcb.maojet.com.tw

39

Profile for KairosGlobal

APD+ SPB 17.4 QIR3 新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: sales@pcb.maojet.com.tw Web: http://pcb.maojet.com.tw/

APD+ SPB 17.4 QIR3 新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: sales@pcb.maojet.com.tw Web: http://pcb.maojet.com.tw/

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