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17.4 QIR3 新功能介紹 • • • • • • • • • • • 2

支援簡體中文/日文介面 增進鋪銅的效率與品質 DRC改進 模組管理增強 Scribble功能 佈線效率提升 Component Lead功能 DFM功能改進 3D 顯示功能強化 Symphony Team Design 功能增強 Allegro 新產品架構 © 2021 Cadence Design Systems, Inc. All rights reserved.


支援簡體中文/日文介面 3

© 2021 Cadence Design Systems, Inc. All rights reserved.


Allegro PCB Editor 中文界面

4

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Allegro System Capture 中文界面

工 具 選 單

設 置

分 析 結 果

報 錯 和 題 示

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Allegro 日本語化した画面のイメージ

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© 2021 Cadence Cadence Design Design Systems, Systems,Inc. Inc.Cadence All rightsconfidential. reserved. Internal use only.


增進鋪銅的效率與品質 7

© 2021 Cadence Design Systems, Inc. All rights reserved.


GPU 加速鋪銅圖形顯示 • 使用NVIDIA® GPU to render graphics in Allegro® PCB Designer o

o o

Pre-QIR2,原先只有兩個選項: OpenGL and nonOpenGL,在QIR3後新增第三種選項:GPU。 適用於Windows and Linux 適用於17.2 相容模式

• 使用GPU的優點 o

Comparing Performance

Operation

Old graphic engine

GPU engine*

Zoom fit

16 sec

1 sec

Show All Layer

3 sec

0.01 sec

Show/Hide single layer

2 sec

0.01 sec

Panning

1 sec

0.01 sec

Zooming in/out

1 sec

0.01 sec

*Using NVIDIA Quadro® RTX 6000 Augmented Quality of Display

提升縮放/平移的效率

• Setup ➔ User Preferences 勾選 ‘disable_gpu’ 以關閉GPU功能

Old Graphics 8

© 2021 Cadence Design Systems, Inc. All rights reserved.

New GPU


GPU 加速鋪銅圖形顯示

https://youtu.be/N7MTxJhXPl8

*使用 Nvidia Quadro RTX 6000 9

© 2021 Cadence Design Systems, Inc. All rights reserved.


鋪銅效率增強 • 鋪銅 o

全鋪銅效率增強

o

平均效率提升~21%

• FAST鋪銅模式 o

Fast 鋪銅模式首見於 17.42 版 –

‘Fast’ 模式取代 ‘Rough’模式

大幅提升動態銅編輯效率 (slide, add connect, move, etc.)

避銅結果與SMOOTH鋪銅相當類似,保留了連接性 和整體外觀

o

平均效率提升~48%

• SMOOTH鋪銅模式

10

o

提升了 etch edit 相關過程的效率

o

平均效率提升~19%

© 2021 Cadence Design Systems, Inc. All rights reserved.


鋪銅品質增強

Voiding 品質增強 • Crosshatch Shape Fill improvement

• Fillet void quality improvement

Pre-QIR3 Result

11

© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result


鋪銅品質增強

Voiding 品質增強 • Trim void improvement o

• Trim void improvement

Reduction in void spikes at min aperture failures

o

Reduction in acute angles

Pre-QIR3 Result

12

Prior QIR3 Result

© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result

QIR3 Result


鋪銅品質增強

Voiding 品質增強 • Trim void improvement o

• Trim void improvement

Reduction in min width failures

o

Aperture=3.0 Actual =2.6

Pre-QIR3 Result

13

© 2021 Cadence Design Systems, Inc. All rights reserved.

Aperture=3.0 Actual =5.4

QIR3 Result

Reduction in min width/thin protrusion failures


DRC改進 14

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Fillet DRC Control • 在 Design➔Spacing 設定 “Enable Line based check for fillets” 選項可將Fillet圖形為Trace的型態 (非 Pad) o

可決定DRC fillets 為 via/pin-to-object spacings 或是 line-to-object spacings

o

默認情況下,fillets 從它們附加到的連接對象繼承spacing constraints (pin or via)

o

15

Pin/Via Pad的延伸在fillet 周圍保持一致的距離

新的 spacing option 可切換 DRC 檢查 fillet與 trace 間距的行為

不適用於17.2 相容模式環境

© 2021 Cadence Design Systems, Inc. All rights reserved.

Fillet as Pad

Fillet as Trace


Return Path DRC Check New Adjacent Void Spacing (High Speed Option) • ‘Return Path DRC’ is designed to ensure proper signal to reference plane adherence and detection of signals crossing voids​ (loss of reference) o

o

Routing/Segment Over Void –

Ability to set length of trace to ignore reference loss less than a specified value (Ignore Length)

Ability to set length of trace to ignore that loses reference due to the Antipad of the Via on the reference plane (Max Pad Gap)

Max Return Path Stitching Via Distance –

o

Ability to specify the distance from the signal net via within which the reference net stitching via must be found

Min Adjacent Void Spacing (New) –

Ability to specify minimum distance of signal net to adjacent void

Available in 17.2 Compatibility Mode •

16

Adjacent Void Spacing rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4

© 2021 Cadence Design Systems, Inc. All rights reserved.


DRC Browser Updates • Navigation Improvements o

Navigation tree contain RMB menu to expand/ collapse all from any given node

• Waive DRC by group select o

LMB Hold and Drag to select, then RMB>Waive

https://youtu.be/7nGpTvVGcgw

• New Constraint Domain view option

17

o

View constraint by Constraint Set view (default)

o

View DRCs by Domain type

o

View selection in DRC Browser Options form

© 2021 Cadence Design Systems, Inc. All rights reserved.

https://youtu.be/5ppm1U_mCNg


模組管理增強 18

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置件後直接替換原模組 Placement Edit App Mode option to select a module and replace it with a different variant Replace module for multiple instances; Replace into current location Module: DDR_TERM.mdd

Module: DDR_TERM_SHAPE.mdd

https://youtu.be/B7WSMnnw93Q 19

© 2021 Cadence Design Systems, Inc. All rights reserved.


Scribble功能 20

© 2021 Cadence Design Systems, Inc. All rights reserved.


Multi-Pin Scribble Support in Add Connect

先手拉大致 走向

確認後自動生 成實際走線

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Multi-Pin Scribble Support in Add Connect https://youtu.be/HhGHKLhXwPs

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© 2021 Cadence Design Systems, Inc. All rights reserved.


佈線效率提升 23

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Parameterized High Speed Structures Differential Pair w/Return Path Enhancements • New prototype to generate High Speed Structures based on parameters first released in 17.42 o

o o

Create high-speed via transitions with return path vias, route keepouts, and pad entry/exit traces from a variety of available patterns Accessible thru Route>Unsupported Prototypes>Create Structure Available in 17.2 Compatibility Mode

• Differential Pair Signal Vias o

New canvas selection of pre-existing via transitions seed Padstack, Spacing/Pitch

• New Route Keepout Void Shapes added to Structure Generator for more customized high speed structures in 17.43 o o o

Available keepout shapes: rectangle, oval, rings, goggles, owl Ability to define different keepout shapes and dimensions per layer Ability to define allowed objects (i.e. via, trace, etc) in keepout by layer

Oval 24

Rings

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Rectangle

Goggles

Owl


Align Vias Update User Pick Reference • New ability to select ‘User Pick’ as reference for alignment of vias o

Click anywhere in canvas or use RMB>Snap Pick to

o

Available in 17.2 Compatibility Mode

https://youtu.be/w1U1Uv56tFc 25

© 2021 Cadence Design Systems, Inc. All rights reserved.


Component Lead功能 26

© 2021 Cadence Design Systems, Inc. All rights reserved.


DFA Component Lead Definition​ Assigning Lead Definitions • Component Lead Editor​ o

Library or Design Level Definition Entry

o

Specify Lead type​ –

o

BGA, Gull Wing, Flat …​

Lead contact area definition​

• Enables lead to hole/pad checks​ o

Thru Pin Lead to Hole Size​

o

SMD Lead to pad (Toe, heel, side)​

Component lead contact area geometry

27

© 2021 Cadence Design Systems, Inc. All rights reserved.


Component Lead Display • Display Lead Contact Geometry o

Color form - enable Package Geometry Component Lead Display

o

Lead Geometry now contained within Pin Pad display

https://youtu.be/T-aT5Gaqw1k

28

© 2021 Cadence Design Systems, Inc. All rights reserved.


DFM功能改進 29

© 2021 Cadence Design Systems, Inc. All rights reserved.


DesignTrue™ DFM Enhancements

Cu defined pad

SM defined pad

Soldermask Via and SMD Pad (Venture ↑ ) • Via Soldermask Pad to SMD Soldermask Pad Overlap Check o

Allow Via-in-pad Via mask to SMD mask Overlap –

o

Allows the mask of a via contained within a SMD pin to overlap beyond the SMD pin mask boundary • Via origin must be contained within the SMD pin pad boundary

Allow Same net Via mask to SMD mask Overlap –

o

Allow Via-In-Pad Via Mask To SMD Mask Overlap = OFF/NO

Allows the mask pad of a via outside the boundary of an SMD pin to overlap the SMD mask pad • Via origin outside of SMD pin pad boundary

Allow Via-In-Pad Via Mask To SMD Mask Overlap = ON/YES

Available in 17.2 Compatibility Mode –

Rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4

Allow Same Net Via Mask To SMD Mask Overlap = OFF/NO

30

© 2021 Cadence Design Systems, Inc. All rights reserved.

Allow Same Net Via Mask To SMD Mask Overlap = ON/YES


DesignTrue DFM Lead Check • Lead Type Based Rules o

Board and Library level check

o

Through hole lead to hole size

o

SMD Pin to pad/pastemask

o

BGA Pin to Pad –

Metal defined

Mask defined

• Minimum and Maximum Values o

TH Lead to hole

o

SMD Toe, heel, side.

• Multiple SMD and BGA Lead Type Rules o

31

Gullwing, Flat lead, J-Lead, etc.

© 2021 Cadence Design Systems, Inc. All rights reserved.

(Venture ↑ )


3D 顯示功能強化 32

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3D 顯示功能強化 • 等距視圖現在包括頂視圖或底視圖的選擇

• Realistic Plating Thickness

• 數字鍵盤 “1” 鍵或是功能表 View➔Camera

Pre-QIR3 Result

QIR3 Result

• Increased Model Realism o

3D Canvas and JPEG/PNG Export

Isometric View - Top

Pre-QIR3 Result Isometric View - Bottom

33

© 2021 Cadence Design Systems, Inc. All rights reserved.

QIR3 Result


Symphony Team Design 功能增強 34

© 2021 Cadence Design Systems, Inc. All rights reserved.


Symphony Team Design 是什麼? o

o

o

一個可以多個使用者同時編輯同一個brd 檔的環境 與 design-partitioning solution 差異很大,必須將檔案 切成多個部分並給多個使用者在各自的電腦上編輯, 最後在整合成一個檔案。 Symphony Team Design 需要 PA3160 license

Symphony Team Design Option VS

Design Partitioning 35

© 2021 Cadence Design Systems, Inc. All rights reserved.


支援新的Structures • 在Symphony 中可以創建Structures o

可以經由圖形視窗選擇目標創建structure或是使用參數設定視窗生成 structure

o

在Symphony 中可以Place Structures

o

可以從library中放置或即時創建Structures添加到Server端的database以 供其他client端使用 –

Structures➔Place, copy/paste

• 在Symphony 中可以 Export 所有的 Structures

• 拉線指令 Add Connect 支援動態加 structure • 按滑鼠右鍵選擇 Unlock 可以編輯 structure

Route>Structures now Available 36

© 2021 Cadence Design Systems, Inc. All rights reserved.

Create

Place


佈局優化/分享連結 • In-session Component Placement o

圖形化多用戶鎖定,以防止元件放置期間發生衝突

• Share Button o o

37

簡單生成Symphony Server的分享連結 按下 Share button, 複製連結給他的 clients

© 2021 Cadence Design Systems, Inc. All rights reserved.


Allegro 新產品架構 38

© 2021 Cadence Design Systems, Inc. All rights reserved.


新產品架構 Collaboration via Pulse

ALG100:Artist • Rogue teams

ALG200: Designer • Main Stream Design

• Enterprise Control

• Teams that do not need/want to be part of the main stream design flow

• Teams that are integrated into the design flow of the organization.

• Test boards

• Data link to enterprise

• Multi-discipline access

• Bring up boards

• Collaboration with outside disciplines

• GPU performance

• Isolated R&D • Flexibility to be elevated to higher capable tiers when required

• Day to day design

• Proficient in implementation of tools….

功能完整性 39

ALG300: Venture

© 2021 Cadence Design Systems, Inc. All rights reserved.

• Structured flows • Partition design collaboration

• Comprehensive solution for DFM and High Speed


Allegro Back-End Tiering ALG300 Allegro PCB Venture

• • • • •

Complete DesignTrue DFM rule set and DRCs RAVEL Developer Miniaturization and Highspeed options All AI Flowplanning GPU Acceleration

Options

ALG200 Allegro PCB Designer II

• • • • • • •

DE-HDL Allegro Constraint Complier RAVEL Checker DFA based placement Electrical – Dynamic Diff pair phase control Visions – Coupling Layer Based Dynamic Shape control

• • • • • • • • • •

Schematics (Capture, System Capture) PSpice Basics Core place and route Rigid, Flex, Rigid-Flex Physical, Spacing constraints Electrical – Matched group, max length, static phase for Diff pairs Core DFM/DT rules (BASE+FLEX) Visions – Route, Impedance Full Specctra Auto Router Tool Box Features (Coil Design, Post Process, Polar Grid, Custom Variables)

ALG100 Allegro PCB Artist

40

© 2021 Cadence Design Systems, Inc. All rights reserved.

Manufacturing

Symphony

Analog / RF

Productivity Tool Box


http://pcb.maojet.com.tw

T E L : +886-3-271-1599 Mail : sales@pcb.maojet.com.tw

41

Profile for KairosGlobal

Allegro SPB 17.4 QIR3 新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: sales@pcb.maojet.com.tw Web: https://pcb.maojet.com.tw...

Allegro SPB 17.4 QIR3 新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: sales@pcb.maojet.com.tw Web: https://pcb.maojet.com.tw...

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