Page 1


➢ Allegro PCB Designer 17.4 Base ➢ QIR1 ( Hotfix 007 ) ➢ QIR2 ( Hotfix 013 )

➢ QIR3 ( Hotfix 019 )

Allegro PCB Designer 17.4 Base Allegro PCB 17.4 在基礎結構上的改變 New Start Page 中文與日文介面支援計畫 支援Board降轉 17.2 版本

優化複製貼上功能 Collaboration and Team Design 強化

In-Design Analysis Productivity improvements 3D Interactive Canvas 改進

Allegro PCB 17.4 在基礎結構上的改變 Allegro PCB 17.4 在基礎結構上的改變 •

New and improved user interface infrastructure (QT) (no more mainwin)

Enables internationalization in GUI

Updating database for future functionality and performance

Extracta Licensing •

Used to be unlicensed in the past

With 2019 release, it will check for existence of licenses of our products

Designed for no impact to our customers

Designed to prevent usage by unauthorized third parties

New Start Page

中文與日文介面支援計畫 在未來補釘程式將可支援 • 日文功能選單 • 日文訊息描述 • 日文功能視窗 正在進行中的計畫 • 中文版本

支援Board降轉 17.2 版本

.brd V16.6

.brd v17.2


Allegro PCB Editor 17.4-2019

Uprev from v16.6 and v17.2

.brd v17.2

Allegro PCB Editor 17.4-2019

New – Compatibility mode

.brd v17.4

.brd v17.4

Allegro PCB Editor 17.4-2019

Downrev With limitations

.brd v17.2

Downrev to v17.2

➢ Leverage new functionality, improve productivity Will not be able to access new objects and new functionality associated with new objects introduced in 17.4 ➢ Go to manufacturing using 17.2 flow

優化複製貼上功能 Enhanced Copy/Paste • 允許同時黏貼到多數的元件上 • 原始複製的物件會存放在一個暫存區, 以便於黏貼使用 • 配合“Find by Query”功能,對查詢到的目 標物件一起進行黏貼作業


Collaboration and Team Design 強化 (1)

Symphony Team Design

In-Design Analysis


Collaboration and Team Design 強化 (2) • 可鎖定一個完成的區塊,進行模擬檢查 – 使用者可以在使用 Symphony Session 時,進行模擬檢查。 – Impedance, Coupling, Crosstalk, Return Path and Reflection Analysis

• 在同一個環境下針對要修改的部分進行修改以及模擬檢查 • 提升團隊的效益 – 在當前的設計上即時進行模擬檢查


Collaboration and Team Design 強化 (3)

 Allegro Physical Viewer 可在symphony


 Review work done by PCB Designers  Highlight/de-highlight elements

 Pan, zoom, Ratsnest off / on  Find, show elements  Measure  Add Comments and mark-ups (on mark up



In-Design Analysis (1) 1 Embedded Sigrity Technology

Allegro canvas In-Design Analysis

No models No Simulations

PCB Designer

2 PCB Design

Sigrity Analysis Engines

Allegro canvas Analysis results

PCB Designer Analysis results overlaid on Allegro canvas

SI / PI Engineer


In-Design Analysis (2) • 內含 Sigrity technology 消除與 SI/PI 工程師之間的重複過程 – 分辨不符規格的Nets A

Impedance Analysis and Vision

Analysis data on Allegro canvas

Cross-probe, zoom into problem areas Sliders on scale allow for filtering Included in Allegro PCB Designer


Coupling Analysis and Vision

Analysis data on Allegro canvas

View victim and aggressor nets on canvas Included in Allegro PCB Designer


Return Path DRC

Return path violations on Allegro canvas

Signal not next to required Ground Plane Included with PCB HS Option


In-Design Analysis (3) Crosstalk Analysis

Allegro canvas

Reflection Analysis

Allegro canvas

IR Drop Analysis

Allegro canvas

Analysis results viewing with Allegro PCB High Speed Option 15

Productivity improvements (1) DesignTrue DFM improvements – 17.4-2019 Eliminate unnecessary iterations with manufacturers



Mask defined annular ring checks for pins/components

Solder mask check for partially covered vias

• Additional rules for all areas based on customer & manufacturer feedback (17.4) • Remove duplicate / redundant DFM rules from core Allegro PCB Editor

• Continue to add new DesignTrue DFM partners • Users – Get manufacturing rules electronically • CM/Fab Vendors – eliminate unnecessary TQs 16

Productivity improvements (2) Ability to define notes on objects in the design – 17.4-2019 Data transferred to IPC-2581 via SPEC construct • Eliminate electronic paper instruction for PCB Manufacturing • Reduce unnecessary iterations with your manufacturing partners Notes attached to Design, Nets, Components, Shapes, Lines easily Note for compliance to a specification

Manual insertion required for this component


Productivity improvements (3) Electronically interpretable notes on objects/designs Ensure build intent is communicated reliably


Productivity improvements (4) New use model for Via Arrays

• •

Shield RF and High Speed traces for crosstalk and EMI Add / Update / Delete Via Arrays – – – – – –

Single Side of Object Both Sides of Objects Centered on Objects Centered Between Objects Surrounding Selected Objects Various Matrices

50x Performance Improvement on Preview


Productivity improvements (5) Hybrid Arc sliding Improved user control over sliding

Enhanced Arc Support Off – Robust – Predictable results – Non-destructive sliding

• Enhanced Arc Support On – Extended range of motion – Can generate any angle arc – Arc support for bubble (hug and shove)


Productivity improvements (6) Via Structure Update • Single Creation GUI • Newly Added • Description • Procedures • Visuals • Graphic Examples • Create Any Structure without Changing Commands

• New FBQ support for creating Structures

Included with PCB High Speed Option


3D Interactive Canvas 改進 (1) Accurately model height of a component / product 3D Model


Pastemask Pad PCB 3D Model

• Accurately model in 3D and check for collision with enclosures • Important for products that – Have small form factors such as hand held devices – Fit into small spaces


3D Interactive Canvas 改進 (2) 3D Canvas – Symbol Representation Using DFA_Bound Shapes • Symbol representation in 3D can use DFA_Bound as a choice – In addition to existing Place_Bound shape choice – Some customers create DFA_Bound shapes at MMC (Maximum Material Condition)


3D Interactive Canvas 改進 (3) 3D Canvas – Mechanical Symbol transparency •


Pre - V17.4



3D Interactive Canvas 改進 (4) 3D Canvas – Usability Improvements Associated with Cutting Plane • Quicker access to cutting plane command – RMB invocation – Also provides access to options pane – Used to be in preference controls

• Performance improvements



QIR1 ( Hotfix 007 )

排版功能強化 新增版本管理功能

新增 Allegro constraint compiler功能 Interactive 3D Canvas 優化


排版功能強化 • Simplifies panel documentation process • Boards can be stepped individually or by

• • • • • •

array Boards can be rotated and/or mirrored individually Automatic update Automatic notification if boards have been modified Based on proven mdd-Technology (Design Reuse, Place Replicate) Supports standard panels as well as family panels Configuration stored in database


排版功能強化 Family panels  Contain more than one board layout  Simply link the board databases  Make your placement


新增版本管理功能  版本管理控制  Little to no training – it just works


 Easily go back in time  Safely explore different design paths

 Provides value to individuals & teams  Embedded mode (default) enables version control

of the PCB design on the user’s own machine  Connect to a centralized Pulse server to store design versions in a collaborative environment  File > Commit will save the database to project directory but will also backup to Pulse  Users can rollback to a previous version 30

Allegro Constraint Compiler (1) Allegro Constraint Compiler - Included with PCB HS Option Faster creation, reuse of constraints while reducing risk Misc Constraints Internal Design Guides

Table Driven Constraints (csv)

IC Vendor Design Guides Mapping Data

Allegro Constraint Compiler (ACC)

Allegro Constraint Manager

Allegro Design Authoring Allegro PCB Designer


• • •

Flexible Table based constraints that are design independent Consistent process for creation, updates and reuse Significantly reduce human efforts for mapping data, reduces risk of errors being introduced


Allegro Constraint Compiler (2) Allegro Constraint Compiler Benefits •




更能維持Constraint Rules使用上的一致性


Allegro Constraint Compiler (3) Example: Design independent DDR4 interface definition Constraint Manager Objects created • 16 Net Groups with 8 Nets and 16 Diff Pairs – Diff Pair defined as the Target net in each match group – Propagation Delay applied to All Pin Pairs created

• • •

16 Net Classes for each groups of Nets 136 Net Class to Net Class relationships driving Spacing Constraints ACC creates the required match groups based on relative prop delay constraints

➢ Tremendous time saver! ➢ Days down to minutes

➢ Correct by construction 33

Interactive 3D Canvas 優化 (1) • 3D Canvas Launch Improvement o

As compared to V17.4 ISR1 with All Layers and All Objects On launching 3D Canvas Type 1 Small Designs 2 Medium Designs

3 Large Designs






7.67 s

2.40 s



78.02 s

19.61 s



471.02 s

230.38 s




• 3D Canvas Memory Usage Decline Type 1 Small Designs

2 Medium Designs 3 Large Designs




424.95 Mb

425.69 Mb



1071.62 Mb

755.91 Mb



8604.89 Mb

5259.72 Mb

39% 34

Interactive 3D Canvas 優化 (2) • 3D Object Filtering o o

o o

Select Layers and Objects to display All Layers or Outer Layers All Objects or specific objects Improves loading of large designs by only loading necessary objects

• New Nets Pane o


Augmented Net Information for names, properties, types Visualize entire net or any object(s) of that net

• Zero Spacing Collision Detection Consistency with 2D o


Supports components adjacent to each other with “0” clearance Eliminates unnecessary collision errors

Example: J1 & J3 Place_Bound side edges are on exact same plane


Interactive 3D Canvas 優化 (3) New highlight modes – Dim & Vanish

Existing Select Mode

New Vanish Mode

New Dim Mode 36

Interactive 3D Canvas 優化 (4) Allegro PCB - Sigrity/Clarity Integration • Export 3D folded view to Sigrity / Clarity to allow for accurate product level simulation / analysis o o

Crosstalk EMI simulation

• Output includes net information o o o

Net name Type Properties

Clarity analysis with 3D information


QIR2 ( Hotfix 013 ) GPU 加速鋪銅圖形顯示 3D Canvas 功能更新

DesignTrue DFM Check 強化 支援 EDMD (IDX) 4.0 支援 IPC-2581 Revision C 動態鋪銅增加 Fast Mode

支援 3D Cross Probing Spacing checks in Z-direction 39

GPU 加速鋪銅圖形顯示  Using NVIDIA GPU to render graphics in

Allegro  Gain performance  Augment the quality of display

 Panning/Zooming/Quality performance


Old graphic engine

GPU engine*

Zoom fit

16 sec

1 sec

Show All Layer

3 sec

0.01 sec

Show/Hide single layer

2 sec

0.01 sec


1 sec

0.01 sec

Zooming in/out

1 sec

0.01 sec


Old Graphics

New GPU *Using Quadro RTX 6000


3D Canvas 功能更新 (1) 3D Canvas - 3D Mapper • 3D Mapper now part of 3D Canvas o


Replaces existing Allegro (2D) menu Setup > STEP Package Mapper Simplified use model & GUI

• Map 3D models to footprints or devices • Map 3D mechanical models to board designs • Additional support for mapping native CAD models (Parasolid, Siemens NX, CREO, Solidworks)

• Improved accuracy of collision detection and distance measurement o

Due to higher resolution & detailed models 41

3D Canvas 功能更新 (2) 3D Canvas - 3D Mapper GUIs  Existing 2D STEP Package

Mapper GUI  New 3D Mapper GUI for Symbol Editor  New 3D Mapper GUI for Board designs


3D Canvas 功能更新 (3) 3D Mapper – Auto Function 影片連結

• Most models can be mapped using single-click Auto function • Designed for standard pkg symbols o



DesignTrue DFM Check強化 (1) • On-Line DFM On/Off Switch o

Disables DFM checks during exploration editing (placement, other what ifs)


Enables/disables on-line DFM checks


Each individual mode remains unchanged

• Global Manufacturing Tolerance o

Copper and Mask Spacing/Width Tolerance


DFM Checks Ignore violations within tolerance


Reduce number DRC for acceptable violations: –

Rule: .5000 mm

Actual: .4999 mm


DesignTrue DFM Check強化 (2) • DFM Rule Value aggregation o

Aggregates rules values from Multiple DFM Constraint


Generates Aggregated Technology file for DFM Rule CSets import into designs

Aggregated CSet Aggregate Group

• Based on Most Conservative Value o

Max values for spacing, widths


Min numerical value for ratios


Max Value for Angles

• Policy File to define Preferred Values o

General values type (min, max. etc.)


Specific DFM rule value

• Manual Override allowed • Grouping o

Automated – Requires strict naming format


Manual group selection


支援 EDMD (IDX) 4.0 (1) Bend Sequence 2

 Rigid Flex Support  Bend sequence ordering

 Geometry Use Identification

Bend Sequence 1

 Defined intended use of geometry as attribute not

property  Board outline  Cutout  Via

 Primary Pin Identification  Tags primary pin for component ➢

Pin 1, polarity, etc.

 Time Stamp  Initial file creation time stamp

 Modification time stamp  UTC Standard


支援 EDMD (IDX) 4.0 (2) • IDX Baseline Import o

PCB Editor will define database as IDX 4.0 versioning on imported IDX 4.0 baseline –

No settings required

• IDX Baseline Export o


IDX Version 3.0 current default value Set IDX Version 4.0 in User Preferences to create initial baseline in PCB Editor – All exports will be version 4.0 – Sets the database to version 4.0


支援 IPC-2581 Revision C • Rigid Flex Support o

Bend Detail –


Bend angle, radius, direction, sequence, Bend area

Stack-up Profiles –

Boundaries of different materials in different areas

• New Drill Feature Support o



Square Drill

• Net Short o

Identifies shorted nets net names


Identifies location and objects at a specific point

• Enhanced Impedance Support o

Impedance Spec


Impedance for Nets 48

動態鋪銅增加 Fast Mode  New Dynamic fill Fast mode improves dynamic

shape performance  Eliminate delays or lag as dynamic shape update  Drastically improve performance during active etch

editing  Fast mode replaces existing Rough mode

 Reasonably similar results to Smooth shapes

reducing need to update shapes to Smooth  Compatible with Symphony Team Design •


Sample Board o

231 Meg, 15x19 inches


32 Layers, 11K Parts, 54K Pins


966 Shapes (all positive layers)

Slide #1 Slide #2 Route #1 Route #2



10 sec

36 sec


2 sec

22 sec


4 sec

65 sec


4 sec

43 sec



支援 3D Cross Probing


Spacing checks in Z-direction • Productivity Toolbox feature now licensed to Allegro PCB Designer

• 可以任意指定以Net或是Netclass為檢查的對象 • Spacing value 可以手動設定或是由DRC直接 產生 (Constraint Manager) • 提供層別厚度的計算(包含計算或不包含計算)

• 檢查圖形發生重疊的地方


QIR3 ( Hotfix 019 ) 支援簡體中文/日文介面 增進鋪銅的效率與品質 DRC改進 模組管理增強 Scribble 功能改進

佈線效率提升 新增 Component Lead 功能 DFM 功能優化

3D 顯示功能強化 Symphony Team Design 功能增強

Allegro 新產品架構


支援簡體中文/日文介面 (1) Allegro PCB Editor 中文界面


支援簡體中文/日文介面 (2) Allegro System Capture 中文界面 工 具 選 單

設 置

分 析 結 果

報 錯 和 題 示 55

Allegro System Capture 中文界面

工 具 選 單

設 置

分 析 結 果

報 錯 和 題 示


© 2021 Cadence Design Systems, Inc. All rights reserved.

支援簡體中文/日文介面 (3) Allegro 日本語化した画面のイメージ


增進鋪銅的效率與品質 (1) GPU 加速鋪銅圖形顯示 •


GPU to render graphics in Allegro® PCB Designer o



Pre-QIR2,原先只有兩個選項: OpenGL and nonOpenGL,在QIR3後新增第三種選項:GPU。 適用於Windows and Linux 適用於17.2 相容模式

Comparing Performance


Old graphic engine

GPU engine*

Zoom fit

16 sec

1 sec

Show All Layer

3 sec

0.01 sec

Show/Hide single layer

2 sec

0.01 sec


1 sec

0.01 sec

Zooming in/out

1 sec

0.01 sec

*Using NVIDIA Quadro® RTX 6000

Augmented Quality of Display

• 使用GPU的優點 o


• Setup ➔ User Preferences 勾選 ‘disable_gpu’ 以關閉GPU功能

Old Graphics



增進鋪銅的效率與品質 (2) 影片連結

*使用 Nvidia Quadro RTX 6000 59

增進鋪銅的效率與品質 (3) 鋪銅效率增強 • 鋪銅 o




• FAST鋪銅模式 o

Fast 鋪銅模式首見於 17.42 版 –

‘Fast’ 模式取代 ‘Rough’模式

大幅提升動態銅編輯效率 (slide, add connect, move, etc.)


和整體外觀 o


• SMOOTH鋪銅模式 o

提升了 etch edit 相關過程的效率


平均效率提升~19% 60

增進鋪銅的效率與品質 (4) 鋪銅品質增強

‒ Voiding 品質增強 • Crosshatch Shape Fill improvement

• Fillet void quality improvement

Pre-QIR3 Result

QIR3 Result


增進鋪銅的效率與品質 (5) 鋪銅品質增強

‒ Voiding 品質增強 • Trim void improvement o

• Trim void improvement

Reduction in void spikes at min aperture failures


Reduction in acute angles

Pre-QIR3 Result

QIR3 Result

62 Prior QIR3 Result

QIR3 Result

增進鋪銅的效率與品質 (6) 鋪銅品質增強

‒ Voiding 品質增強 • Trim void improvement

• Trim void improvement o

Reduction in min width failures


Reduction in min width/thin protrusion failures

Aperture=3.0 Actual =2.6

Pre-QIR3 Result

Aperture=3.0 Actual =5.4

QIR3 Result


DRC改進 (1) Fillet DRC Control • 在 Design➔Spacing 設定 “Enable Line based check for fillets” 選項可將Fillet圖形為Trace的型態 (非 Pad) o

可決定DRC fillets 為 via/pin-to-object spacings 或是 line-to-object spacings


默認情況下,fillets 從它們附加到的連接對象繼承spacing constraints (pin or via)


Pin/Via Pad的延伸在fillet 周圍保持一致的距離

新的 spacing option 可切換 DRC 檢查 fillet與 trace 間距的行為

不適用於17.2 相容模式環境

Fillet as Pad

Fillet as Trace


DRC改進 (2) Return Path DRC Check ‒ New Adjacent Void Spacing (High Speed Option) • ‘Return Path DRC’ is designed to ensure proper signal to reference plane adherence and detection of signals crossing voids​ (loss of reference) o


Routing/Segment Over Void –

Ability to set length of trace to ignore reference loss less than a specified value (Ignore Length)

Ability to set length of trace to ignore that loses reference due to the Antipad of the Via on the reference plane (Max Pad Gap)

Max Return Path Stitching Via Distance –


Ability to specify the distance from the signal net via within which the reference net stitching via must be found

Min Adjacent Void Spacing (New) –

Ability to specify minimum distance of signal net to adjacent void

Available in 17.2 Compatibility Mode •

Adjacent Void Spacing rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4


DRC改進 (3) DRC Browser Updates 影片連結


• Navigation Improvements o

Navigation tree contain RMB menu to expand/ collapse all from any given node

• Waive DRC by group select o

LMB Hold and Drag to select, then RMB>Waive

• New Constraint Domain view option o

View constraint by Constraint Set view (default)


View DRCs by Domain type


View selection in DRC Browser Options form 66

模組管理增強 置件後直接替換原模組 Placement Edit App Mode option to select a module and replace it with a different variant Replace module for multiple instances; Replace into current location


Module: DDR_TERM.mdd

Module: DDR_TERM_SHAPE.mdd


Scribble 功能改進 (1) Multi-Pin Scribble Support in Add Connect

先手拉大致 走向

確認後自動生 成實際走線 68

Scribble 功能改進 (2) Multi-Pin Scribble Support in Add Connect 影片連結


佈線效率提升 (1) Parameterized High Speed Structures

‒ Differential Pair w/Return Path Enhancements • New prototype to generate High Speed Structures based on parameters first released in 17.42 o



Create high-speed via transitions with return path vias, route keepouts, and pad entry/exit traces from a variety of available patterns Accessible thru Route>Unsupported Prototypes>Create Structure Available in 17.2 Compatibility Mode

• Differential Pair Signal Vias o

New canvas selection of pre-existing via transitions seed Padstack, Spacing/Pitch

• New Route Keepout Void Shapes added to Structure Generator for more customized high speed structures in 17.43 o o o

Available keepout shapes: rectangle, oval, rings, goggles, owl Ability to define different keepout shapes and dimensions per layer Ability to define allowed objects (i.e. via, trace, etc) in keepout by layer







佈線效率提升 (2) Align Vias Update

‒ User Pick Reference


• New ability to select ‘User Pick’ as reference for alignment of vias o

Click anywhere in canvas or use RMB>Snap Pick to


Available in 17.2 Compatibility Mode


新增 Component Lead 功能 (1) DFA Component Lead Definition​ ‒ Assigning Lead Definitions • Component Lead Editor​ o

Library or Design Level Definition Entry


Specify Lead type​ –


BGA, Gull Wing, Flat …​

Lead contact area definition​

• Enables lead to hole/pad checks​ o

Thru Pin Lead to Hole Size​


SMD Lead to pad (Toe, heel, side)​

Component lead contact area geometry 72

新增 Component Lead 功能 (2) Component Lead Display • Display Lead Contact Geometry o

Color form - enable Package Geometry Component Lead Display


Lead Geometry now contained within Pin Pad display



DFM 功能優化 (1) DesignTrue™ DFM Enhancements

Cu defined pad

SM defined pad

‒ Soldermask Via and SMD Pad (Venture ↑ ) • Via Soldermask Pad to SMD Soldermask Pad Overlap Check o

Allow Via-in-pad Via mask to SMD mask Overlap –


Allows the mask of a via contained within a SMD pin to overlap beyond the SMD pin mask boundary • Via origin must be contained within the SMD pin pad boundary

Allow Same net Via mask to SMD mask Overlap –


Allow Via-In-Pad Via Mask To SMD Mask Overlap = OFF/NO

Allows the mask pad of a via outside the boundary of an SMD pin to overlap the SMD mask pad • Via origin outside of SMD pin pad boundary

Allow Via-In-Pad Via Mask To SMD Mask Overlap = ON/YES

Available in 17.2 Compatibility Mode –

Rule/violation will not be in 17.2 but remain in database and recognized when re-opened in 17.4 Allow Same Net Via Mask To SMD Mask Overlap = OFF/NO

Allow Same Net Via Mask To SMD Mask Overlap = ON/YES


DFM 功能優化 (2) DesignTrue DFM Lead Check

(Venture ↑ )

• Lead Type Based Rules o

Board and Library level check


Through hole lead to hole size


SMD Pin to pad/pastemask


BGA Pin to Pad –

Metal defined

Mask defined

• Minimum and Maximum Values o

TH Lead to hole


SMD Toe, heel, side.

• Multiple SMD and BGA Lead Type Rules o

Gullwing, Flat lead, J-Lead, etc. 75

3D 顯示功能強化 3D 顯示功能強化 • 等距視圖現在包括頂視圖或底視圖的選擇

• Realistic Plating Thickness

• 數字鍵盤 “1” 鍵或是功能表 View➔Camera

Pre-QIR3 Result

QIR3 Result

• Increased Model Realism o

3D Canvas and JPEG/PNG Export

Isometric View - Top

Pre-QIR3 Result Isometric View - Bottom

QIR3 Result 76

Symphony Team Design 功能增強 (1) Symphony Team Design 是什麼? o

一個可以多個使用者同時編輯同一個brd 檔的環境


與 design-partitioning solution 差異很大,必須將檔案 切成多個部分並給多個使用者在各自的電腦上編輯,最 後在整合成一個檔案。


Symphony Team Design Option VS

Symphony Team Design 需要 PA3160 license

Design Partitioning 77

Symphony Team Design 功能增強 (2) 支援新的Structures • 在Symphony 中可以創建Structures o



可以經由圖形視窗選擇目標創建structure或是使用參數設定視窗生成 structure 在Symphony 中可以Place Structures 可以從library中放置或即時創建Structures添加到Server端的database 以供其他client端使用 – Structures➔Place, copy/paste

• 在Symphony 中可以 Export 所有的 Structures

• 拉線指令 Add Connect 支援動態加 structure


• 按滑鼠右鍵選擇 Unlock 可以編輯 structure

Route>Structures now Available



Symphony Team Design 功能增強 (3) 佈局優化/分享連結 • In-session Component Placement o


• Share Button o o

簡單生成Symphony Server的分享連結 按下 Share button, 複製連結給他的 clients


Allegro 新產品架構 (1) Collaboration via Pulse

ALG100:Artist • Rogue teams

ALG200: Designer • Main Stream Design

ALG300: Venture • Enterprise Control

• Teams that do not need/want to be part of the main stream design flow

• Teams that are integrated into the design flow of the organization.

• Test boards

• Data link to enterprise

• Multi-discipline access

• Bring up boards

• Collaboration with outside disciplines

• GPU performance

• Isolated R&D • Flexibility to be elevated to higher capable tiers when required

• Day to day design

• Structured flows • Partition design collaboration

• Comprehensive solution for DFM and High Speed

• Proficient in implementation of tools….

功能完整性 80

Allegro 新產品架構 (2) Allegro Back-End Tiering ALG300 Allegro PCB Venture

Complete DesignTrue DFM rule set and DRCs RAVEL Developer Miniaturization and Highspeed options All AI Flowplanning GPU Acceleration

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DE-HDL Allegro Constraint Complier RAVEL Checker DFA based placement Electrical – Dynamic Diff pair phase control Visions – Coupling Layer Based Dynamic Shape control

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Schematics (Capture, System Capture) PSpice Basics Core place and route Rigid, Flex, Rigid-Flex Physical, Spacing constraints Electrical – Matched group, max length, static phase for Diff pairs Core DFM/DT rules (BASE+FLEX) Visions – Route, Impedance Full Specctra Auto Router Tool Box Features (Coil Design, Post Process, Polar Grid, Custom Variables)

ALG200 Allegro PCB Designer II



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Symphony Analog / RF Productivity Tool Box

ALG100 Allegro PCB Artist


T E L : +886-3-271-1599 Mail :


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Allegro PCB Designer 17.4 版新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: Web:

Allegro PCB Designer 17.4 版新功能  

茂積股份有限公司 / PCB事業部 Maojet Technology Corp. / PCB Division TEL: +886-3-2711599 Email: Web:


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