International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 05 Issue: 06 | June-2018
p-ISSN: 2395-0072
www.irjet.net
Fig -3: Complete QSYS design for the transfer of data through DMA controller. We have successfully transferred our data through DMA between the memories as shown in the figure 4 the console is showing the read-data that is transferred in the DDR3 SDRAM. The main objective is to find the time taken in the transfer of the data between the On-chip memory and the DDR3 SDRAM.
Fig -4: Interval timer core block diagram. For the calculation, the time of the transfer we are using the interval timer in our design. There are following steps used in this design: 1. Adding timer in the system integration tool of our later design. Initialization of the parameters for the interval timer. 2. Generation of the design and then integrating the QSYS design with the System design tool project. 3. Simulation and compilation of the final design. 3. Programming the design on the programmer. 4. Initializing the timer before the DMA controller control port command in embedded design suite processor. 5. Reading the counter snapshot before and after the transfer. This Timer works in countdown mode already.
Š 2018, IRJET
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