IOSR Journal of Electronics and Communication Engineering (IOSRJECE) ISSN : 2278-2834 Volume 1, Issue 4 (May-June 2012), PP 51-57 www.iosrjournals.org
Low power CMOS 1-Bit Full adder cell based on Voltage scaling Dayadi.Lakshmaiah1, Dr. M. V. Subramanyam2, Dr.K.Satya Prasad3 1
Asso.professor of ECE Department (HOD), Anurag college of Engg, Hyderabad, India. Principal and Professor of ECE Department, Santhi Ram Engineering College, Nandyala, India. 3 Professor of ECE Department and Rector, JNTU Kakinada, Kakinada, India.
ABSTRACET: Operating an Integrated circuit at the prescribed Voltage scaling (constant field scaling) is preferable for reliable circuit operation under temperature fluctuations. In this work we proposed to design 1 – bit full adder by “changing the threshold voltage and W/L ratio” under temperature variation insensitive conditions. We measured power consumption, leakage current, noise margin, layout area, etc parameters. The results are compared with the previous work and shown that Power is saved 92%, 1% of leakage current and 15% of noise margin. We have performed simulations using 90 Nanometer (nm) Micro wind 3 CMOS layout CAD Tool for design. Key words: voltage scaling, threshold voltage, W/L ratio, Temperature variation, noise margin, leakage current (Ion+Ioff).
Power dissipation has become a prime constraint in high performance applications, especially in portable and battery ASIC systems. So it is necessary to reduce power consumption. Scaling the threshold voltage can limit this performance loss to some extent but results in increased leakages . The advantage of GDI technique two-transistor implementation of complex logic functions and in-cell swing restoration under certain operating conditions, are unique within existing low-power design techniques . The leakage power is expected to reach more than 50% of total power in sub 100nm technology generation . The power reduction must be achieved without trading-off performance which makes it harder to reduce leakage during normal (runtime) operation . Power gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground (called virtual ground) . This device is turned off in the sleep mode to cut-off the leakage path. It has been shown that this technique provides a substantial reduction in leakage at a minimal impact on performance , , , . Process and environment parameter variations are posing greater challenges in the design of reliable integrated circuits in scaled CMOS technologies. The accuracy of estimating the variations relates to the manufacturing cost of an integrated circuit. Results in a conservative design with increased design effort, thereby delaying the time-to-market and degrading performance. Alternatively, an underestimation of variations compromises reliability and functionality, thereby degrading yield. Increasing within-die parameter fluctuations and the complexity in estimating the variations requires new design methodologies for suppressing the effects of process and environment parameter fluctuations in future technology generations. Because of the imbalanced utilization and diversity of circuitry at different sections of an Integrated circuit, temperature can vary significantly from one die area to another . Furthermore, environmental temperature fluctuations can cause significant variations in die temperature. For example, electronic systems mounted on the automobile engines operate at a temperature range from 27°C to 107°C . Temperature variations affect the device characteristics of MOSFETs thereby varying the performance of integrated circuits. Propagation delay of a circuit is a function of the drain current produced by active transistors. Performance of an Integrated circuit under temperature fluctuations is determined by a set of device parameters. Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET . Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current.There exists a bias voltage for which device parameter variations counter balance each other’s effect on MOSFET current when the temperature fluctuates , , , .
2.1. Technology Scaling 2.1.1. Introduction to scaling:Scaling is a discipline of science applicable to many areas such as mechanics, electronics (ICs) and optics (micro optics) as the dimensions of an object are linearly scaled up or down.A scaling factor (S) reduces device dimensions Successive generations of technology have used a scaling S = √2, doubling the number of www.iosrjournals.org
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Low power cmos 1-Bit Full adder cell Based on voltage scaling transistors per unit area. It produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm and 30nm. 2.1.2. Introduction to MOSFET scaling: - The lateral Geometric dimensions of the Device and inter connects are reduced. This reduction in size referred to as scaling of the geometric dimensions of the integrated ckts, Minimum future size of the MOSFET (gate length, inter connect line width) on IC is shown in the figures 1 &Fig2 with K=S. MOSFET Polysilicon Gate
n+ L p-type body
SiO2 Thickness = tox
Copyright Agrawal & Srivaths, 2007
Low-Power Design and Test, Lecture 2
Figure.2 (K=S) Definition: - the scaling parameter S is pre-factor by which dimensions are reduced, it is S < 1 Gate length L =S *L 2.1 Gate width W =S*W 2.2 ID, sat= (ἐox µ w/dox L)*1/2(VD² sat) 2.3 = (ἐox µ w/2dox L)(Vgs-Vth)² Gm=dID/d vgs = (ἐox µ w/dox L)*(Vgs-Vth) 2.4 The gradual channel approximation short gate length and smaller gate thickness results in higher trance conductance. 2.2. VOLTAGE SCALING:There are two types of voltage scaling 1. Constant voltage scaling or fixed voltage scaling. 2. Constant field scaling or variable voltage scaling. 2.2.1. Constant voltage scaling:The lateral dimensions of MOSFET are scaled in the constant voltage scaling which is purely geometrical process. L and W are reduced by the scaling factor S because the drain – source voltage is remain unchanged, the lateral-field increases. It increases approximately by the factor S since Eα (VDS/L) -2.5 E=electric filed, L=length, VDS=drain –source voltage This will lead eventually to very high electric fields in the channel so that dielectric breakdown (Avalanche Break down) will be accrued. 2.2.2. Constant field scaling:Constant field scaling the lateral dimensions (L, W), the perpendicular dimension (dox) and the voltages (VDS.Vth, VGS) of the MOSFET are scaled. Thus constant field scaling is not purely geometrical www.iosrjournals.org
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Low power cmos 1-Bit Full adder cell Based on voltage scaling process.If constant field scaling is performed L, W, VDS, VGS, tox ,and Vth are varied by the scaling factor S . Electric field in the channel and oxide are Independent of the factor S with (S < 1) . Relation between L, W, VDD, Vth, tox, NA and S shown in the below table.1. E channel α (VDS /L) -2.6 And E ox α (Vth /doc) - 2.7 Constant Electric Field Scaling Device Parameter
Gate oxide thickness, tox
Supply voltage, VDD
Threshold voltages, Vtn, Vtp
Substrate doping, NA Copyright Agrawal & Srivaths, 2007
Low-Power Design and Test, Lecture 2
Table.1: Relation b/n L,w,Tox,vth,VDD.
2.3. Factors Influencing MOSFET Drain Current under Temperature Fluctuations:Device parameters that are affected by temperature fluctuations, causing variations in drain current produced by a MOSFET, are identified in this section. BSIM4 MOSFET current equations are used for an accurate characterization of drain current in deeply scaled nanometer devices. The drain current of a MOSFET is 0r AbulkVdseff Vdseff Vgsteff Ids0= Weff µeff (1) Vdse TOX (2Vgsteff+4.v (1 ff ) Leff sat E t) + satLeff Leff where Ids, Ids0,Vdseff, Vgsteff , Abulk, μeff ,Weff and Leff are the drain current with short-channel effects, TOXE is gate oxide thickness, drain current of a long channel device, effective drain-to-source voltage, effective gate overdrive (VGS-Vt), parameter to model ,the Bulk charge effect, effective carrier mobility, effective channel width and effective channel length, respectively. Threshold voltage, carrier mobility are Vth VTHO K1(s
Vbs s ) K 2.Vbs Vt SCE VtNULD VtDIBL U0
1+(UA+UC.Vbseff)( Vgsteff+2(VTH0-Vfb-s) )
TOXE where Vth,VTHO,K1,K2,Vbs,∆VtSCE,∆VtNULD, ∆VtDIBL, μef,, UO, UA, UC, VTHO, Vfb, Φs, TOXE, &EU are the threshold voltage,TOXE is gate oxide thickness,Uo is low field mobility, UA is coefficient of 1st order mobility degradation due to vertical field, Uc is coefficient of 1st order mobility degradation due to body bias effect, long channel threshold voltage at vbs=0, first order body bias coefficient, second order body bias co-efficient, bulk source voltage, short channel effect on vt,non-uniform lateral doping effect, drain induced barrier lowering effect of short channel on vt,effective mobility, low field mobility, co-efficient of first order mobility degradation due to vertical field, co-efficient of mobility degradation due to body bias effect, long channel threshold voltage at vbs=0v,flatbandvoltage,surface potential, oxide thickness, and coefficient.
PERFORMANCE ANALYSIS AND SIMULATION RSULTS:-
The proposed work shown the in below figures 3&4 (FA.1, FA.2). Fig.3 shows the full adder circuit with Voltage scaling method. Here the value of W/L ratio is changed differently for pmos and nmos MOSFETS .This Proposed work1 has saved 90 % of power shown in the figure .4 . Different MOSFETs are www.iosrjournals.org
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Low power cmos 1-Bit Full adder cell Based on voltage scaling high threshold voltage are taken P1, P2, P3, P4, P6, P7. This Proposed work2 has saved 92 % of power. Shown in figures 5 - 11 simulation results and leakage power reports at different temperatures.
Figure .3 FA.1 (proposed work 1) w/L Ratio changes
Figure .4 FA.2 (proposed work 2) Threshold voltages changes.
Refe r pape r .11 61.2
(1.16 5mA +40n A)
(3.91 5mA +134 nA)
(1.10 mA+ 40nA )
(0.87 mA+ 5320 nA)
(2.93 1mA +178 72nA ) 1045
Power ÂľW Leakage current (Ion+Ioff )
Table.2: Comparison of previous work and proposed work
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Low power cmos 1-Bit Full adder cell Based on voltage scaling
Figure.5 FA.1 power report at 27 o C.
Figure.6 FA.1 power report at 107 o C.
Figure.7. FA.1 Leakage current at 27 o C.
Figure.8. FA.1 Leakage current at 107 o C.
Figure.9 FA.2 power report at 27 o C. www.iosrjournals.org
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Low power cmos 1-Bit Full adder cell Based on voltage scaling
Figure.10. FA.2 power report at 107 o C.
Figure.11. FA.2 Leakage current at 27 o C.
Figure.11 FA.2 Leakage current at 107 o C.
The results are compared with the previous work and we shown that Power is saved 92%, 1% of leakage current and 15% of noise margin. We have performed simulations using 90 Nanometer (nm) Micro wind 3 CMOS layout CAD Tool for design. Further power can be saved by using reduction of parasitic capacitance and by using various parameters.
ACKNOWLEDGMENT I Express my Deep sense of gratitude and thanks Chairmen sir Dr.Rajeshswar Reddy sir, Director Prof Dr. Kishan Rao sir, Academic coordinator prof Anupama madam, principal vasudevan sir of Anurarg college of Engg HYD ,for giving me this opportunity to carry out my Research work at highly esteemed Organization.
REFERENCES    
S. Goel, M. A. Elgamel and M. A. Bayoumi, ―DesignnMethodologies Transl. on Circuits and Systems—I: Regular Papers, vol. 53, No. 4, April 2006. P. M. Lee, C. H. Hsu and Y. H. Hung, ―Novel 10-T full addersrealized by GDI structure‖, Proc. on Intl. Symp. on Integrated Circuits (ISIC2007), pp.115-118. Jun Cheol Park and Vincent J. Mooney‖ Sleepy Stack Leakage Reduction‖ IEEE transactions on very large scale integration (vlsi) systems, vol.14, no.1. november 2006. Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J.Nowka,‖Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating,‖IEEE Transactions on VLSI Systems, Vol.15, No.11,
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Low power cmos 1-Bit Full adder cell Based on voltage scaling 
        
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Author Profile Dayadi.Lakshmaiah is currently working as an (HOD) Associate professor of Electronics & Communications Anurag Engg College, Hyderabad, AndraPradesh (State), India. He Received B.Tech Degree in ECE From National Institute of Technology, Warangal (RECW) and M.Tech (DSCE) Degree From JNTUA Anantapur Andhra Pradesh He has published 5 International Journals..Now He is Pursuing PhD in Low Power VLSI at JNTUK, Kakinada. India. Dr.M.V.Subramanyam Professor of ECE, currently working as Principal of Santhiram Engineering College Nandyal, Andhra Pradesh, India. He has 22 years of Experience in Teaching. He authored 4 text books, STLD, Computer Networks, Basic Electronics and Microprocessor& Microcontroller Interfacing and Application. He published more than 48 Technical papers in various National and International Journals and Conferences’, He has an Editorial Member for the 4 International journal and 3 National Journals. “His Area of interest is Adhoc Wireless Networks, Cellular and Mobile Communications. He has Received B.Tech & M.Tech in ECE from JNTU, Hyderabad, PhD (Adhoc wireless Networks) Degree from JNTUH, Hyderabad, Andhra Pradesh, India. He has completed 5 research projects sponsored by the IE(I), India and currently one research project in hand which is funded by AICTE, New Delhi. Dr. K. Sathaya Prasad Professor of ECE is currently working as Rector of JNTUK, Kakinada. He has more than 32 years of experience in teaching and 25 years of R & D. He is an expert in Digital Signal Processing. He has Guided to 10Ph.D’s and guiding 10Ph.D scholars. He authored Electronic Devices and Circuits text book. He held different positions in his career like Head of the Department, vice principal, and principal for JNTU Engineering College (JNTUK). He published more than 60 technical papers in National and International Journals and conferences. He also received best Teacher Award from Govt of Andhra Pradesh in 2010. He is Received B.Tech Degree in ECE from JNTUA Anantapur, M.E (Communication Systems) Degree from University of Madras, and Ph.D (signal Processing) Degree from the Indian Institute of Technology Madras, India.
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