This paper presents a systematic approach to the complex problem of high confidence performance
assurance of high performance architectures based on methods used over several generations of industrial
microprocessors. A taxonomy is presented for performance assurance through three key stages of a product
life cycle-high level performance, RTL performance, and silicon performance. The proposed taxonomy
includes two components-independent performance assurance space for each stage and a correlation
performance assurance space between stages. It provides a detailed insight into the performance assurance
space in terms of coverage provided taking into account capabilities and limitations of tools and
methodologies used at each stage. An application of the taxonomy to cases described in the literature and
to high performance Intel architectures is shown. The proposed work should be of interest to manufacturers
of high performance microprocessor/chipset architectures and has not been discussed in the literature.