ISSN: 2250â€“3676

PUNNAIAH.S* et al. [IJESAT] INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY

Volume-2, Special Issue-1, 123 â€“ 127

OPTIMAL POWER CALCULATION FOR THE CRYPTOGRAPHY AES ALGORITHM USING CLOCK GATING TECHNIQUE Punnaiah.S1, Venkata Ganesh.G2, Naresh kumar Reddy.Beechu3 1

Research Scholar, ECE Department, K.L.University, A.P, India, punnaiah.sp@gmail.com Assitant Professor, ECE Department, K.L.University, A.P, India, ganesh.gorla@yahoo.com 3 Research Scholar, ECM Department, K.L.University, A.P, India, naresh.klu@gmail.com

2

Abstract Advanced Encryption Standard (AES). The AES is a Federal Information Processing Standard (FIPS). The AES algorithm is a symmetric block cipher that can encrypt, (encipher), and decrypt, (decipher), information. Encryption converts data to an unintelligible form called cipher-text. Decryption of the cipher-text converts the data back into its original form, which is called plaintext. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. Many algorithms were originally presented by researchers from twelve different nations. The Rijndael algorithm was chosen in this paper since it had the best overall scores in security, performance, efficiency, implementation ability and flexibility. In this paper low power clock gating technique is used to reduce power of AES core. Results show that dynamic power can be minimized as overall design is considered when compared to design without clock gating technique.

Index Terms:AES, clock-gating, Low-power, information security, Rijndael algorithm -----------------------------------------------------------------------***----------------------------------------------------------------------1. INTRODUCTION All electronic hardware devices handling Crypto algorithms are really meant for information security. Crypto-cores execute cryptographic algorithms for providing services such as privacy, confidentiality, integrity, and authentication. Although cryptography is used to provide security, weaknesses such as weak crypto algorithms, poor design or physical failure of the hardware platform that implements the crypto algorithm can render the product insecure and place highly sensitive information at risk. Consequently, appropriate validation and testing of the cryptoalgorithms and corresponding crypto-core are essential to provide security assuranceUnited States National Institute for Standards and Technology (NIST) organized contest for selecting encryption standards. The Data Encryption Standard (DES) [6] was adopted as national standard in 1976, and the Advanced Encryption Standard (AES) [7] has been selected in October 2000. Since the hardware implementation of DES is not expensive, it is still used in many applications in the form of Triple DES for security improvement [8]. Gating the clock at the last few levels of the clock buffers is therefore aneffective

way to reduce active power. Since a clock gated latch keep sits current data value stable, clock gating prevents signal transitions of invalid data from propagating down the pipeline thereby reducing switching power in the combinational logic between latches.

2. CLOCK-GATING Clock-gating has been introduced as the primary means of dynamic power management in recent high- end in recent commercial microprocessor. Lower power consumption is mandatory for mobile and handheld applications for longer battery life and even networking or storage devices for low carbon footprint requirements. Clock power consumes 60-70 percent of total chip power and is expected to significantlyIncrease in the next generation of designs at 45nm and below. This is due to the fact that power is directly proportional to voltage and the frequency of the clock as shown in the following equation. Power = Capacitance * (Voltage) 2 * (Frequency) Hence, reducing clock power is very important. Clock gating is a key power reduction technique used by many designers and is typically implemented by gate-level power synthesis

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PUNNAIAH.S* et al. [IJESAT] INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY tools. Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock signal on registers whose outputs do not affect circuit outputs. We consider and evaluate FPGA clock network architectures with built-in clock gating capability and describe a flexible placement algorithm that can operate with various gating granularities (various sizes of device regions containing clock loads that can be gated together). Results show that depending on the clock gating architecture and the fraction of time clock signals are enabled, clock power can be reduced by over 50%, and results suggest that a fine granularity gating architecture yields significant power benefits.[12] In this paper, we will discuss the use of clock gating techniques with design examples for achieving lower power and also highlight the impact of clock gating on different areas of the design process like meta-stability with clock domain crossings and testability. The paper also details the do's and don'ts of clock gating to avoid chip failures and unnecessary power dissipation.

Volume-2, Special Issue-1, 123 â€“ 127

most suitable (see Advanced Encryption Standard process for more details). It became effective as a Federal government standard on May 26, 2002 after approval by the Secretary of Commerce. It is available in many different encryption packages. Figure 1: encryption processes

Plain text

ADD Round key (Data Roundkey)

KEY

Round = 1 Byte Sub (Data)

ShiftRow(Data) Shift Row(Data) Mix column(Data)

3. AES (RIJNDAEL) ALGORITHM The Rijndael algorithm is a symmetric block cipher that can process data blocks of 128 bits through the use of cipher keys with lengths of 128, 192, and 256 bits. The Rijndael algorithm was also designed to handle additional block sizes and key lengths. The hardware implementation of the Rijndael algorithm can provide either high performance or low cost for specific applications[8]. At backbone communication channels or heavily loaded servers it is not possible to lose processing speed, which drops the efficiency of the overall system while running cryptography algorithms in software. On the other side, a low cost and small design can be used in smart card applications, which allows a wide range of equipment to operate securely.

)nd

ADD Round Key (Data,Key)

round = round + 1

Key Schedule

Round < (No. Of rounds)

Byte Sub(Data)

)Shift Row(Data)

A. AES (Rijndael) Encryption

)

ADDRoundKey(Data)

The Encryption process of Advanced Encryption Standard algorithm is presented below, in figure 1. Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. It has been adopted by the U.S. government and is now used worldwide. It supersedes DES, The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. In the United States of America, AES was announced by National Institute of Standards and Technology (NIST) as U.S. FIPS PUB 197 (FIPS 197) on November 26, 2001 after a five-year standardization process in which fifteen competing designs were presented and evaluated before it was selected as the

The basic stepsCipher involved Text in Encryption are 1.

Byte substitution for S-box values

2.

Shift row transformation for shifting the rows in the matrix.

3.

Mixing columns transformation based on Galois Field multiplication.

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PUNNAIAH.S* et al. [IJESAT] INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY 4.

Adding key to mixed columns transformation to the round key

B.AES (Rijndael) Decryption

consists no memories for 128 bit data operations which is suitable for ASIC implementations

4. CURRENT RESULTS

Cipher Text ADDRoundkey (Data,Inv

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Last round key

Round) inv_roundkey) Round =

1 InvShift_Row( Data) Invbyte_sub( Data) ShiftRow(Data)

Figure 3: shows the simulation results of the 128 encrypt and decrypt data, i.e. to give 128 bit cipher and 128 bit key then produce inverse of cipher. After to give the inverse of cipher then produce plain test or cipher using the ISE simulator. Figure 4: shows the experimental results of AES core and comparison of AES core without clock gating and with clock gating using the cadence RTL compiler.

A .Simulation results:

ADDRoundkey(Data,inv_roundke y)

InvMixcolumn(Dat a) round = round +

Key Schedule

1 Round < (no. Of

rounds) InvShift_Row(Da ta) InvByte_Sub(Da ta) ADDRoundKey( Data)

Key

Plain Text2 : decryption processes Figure

Figure 3: simulation results of 128 bit plain data and inverse plain data.

B .Experimental results:

In the decryption algorithm, the quite reverse operations will be done on the input cipher text. The corresponding inverse operations are 1). Inverse byte substitution 2). Inverse shift row transformation 3). Inverse ADD round key to shift row transformation 4). Inverse Mixing column operations. The hardware implemented for AES (Rijndael) algorithms is valid for key size of 128bits only, because of complexity involved in implementing generic design[13].This design

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PUNNAIAH.S* et al. [IJESAT] INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY

Type of AES

Encryp tion

Decryp tion

AES core

Without clock gating

Leakag e power (nW)

Dynamic power (nW)

96684 36938. 691

2791150 45.702

42536. 146

7258154 1.923

966847 9474.8 37

3516965 87.625

Cmos Technology K.;10.1109/EIT.2009.

With clock gating

Total power( nW)

leakage power(n W)

Dynamic power(n W)

279151 984.39 4

96659 37582.52 8

2742282 09.827

726240 78.069

42506.59 5

7244594 8.626

351776 062.46 3

9665980 089.123

3466741 58.453

Total power(n W)

2742657 92.355

7248845 5.221

3467542 47.576

Volume-2, Special Issue-1, 123 – 127 Feng

Ge;

Jain,

P.;

Choi,

[3] Low Power AES Design Using Parallel ArchitectureHyun Suk Choi; Joong Hyun Choi;10.1109/ICHIT.2008. [4] Hardware-efficient encryption encoder and decoder unitAdams, O.; Shengli Fu; Varanasi, M.; Computer. Sci. & Eng., Univ. of North Texas, Denton, TX16-19 Nov. 2008. [5] Design and Implementation of Low_ Area and Low PowerAESEncryptionHardWareCore.Hamalainen.P,Alho.THa nnikainen10.1109/DSD.2007 [6] Data Encryption Standard, Federal InformationProcessing Standard (FIPS), Publication 46, National Bureau of Standards, U.S Department Of Commerce, Washington D.C, January 1977. [7] Joan Daemen, Vincent Rijmen,"The Design of Rijndael: AES – TheAdvanced Encryption Standard." Springer, 2002. ISBN 3-540-42580-2.

Figure 4: experimental results of AES core

5. CONCLUSION In this paper the performance of cryptography is depends on the AES algorithem, applied the clock gating technique to reduce the power up to 30%,without clock gating technique high power consumed . This paper implemented high efficient and optimal power will be calculated using the cadence RTL compiler. The simulation result of this paper is verified using ISE simulator.

AKNOWLEDGEMENT We thanks to our principal Prof K. Raja Shekar Rao For providing necessary facilities to wards carrying out this work. We acknowledge the diligent efforts of Our head of the department Dr. Habibulla Khan in assisting us towards implementatios of this idea

REFERENCE [1] High Throughput Cost -Effective and Low Power AES Chip Design Yunping Liang; Ye Li; Chengmin Zhang10.1109/CISP.2010. [2] Ultra Low Power and High Speed Design and Implementation of AESandShia Hardware Cores in 65nm

[8] National Inst. Of Standards and Technology, “Federal Information Processing Standard Publication 197, the Advanced Encryption Standard (AES),” Nov. 2001. [9] Ashwini M. Deshpande, Mangesh S. Deshpande and Devendra N. Kayatanavar, FPGA Implementation of AES Encryption and Decryption, Control, Automation, Communication and Energy Conservation, 2009. [10] M.R.M. Rizk, Senior Member, IEEE and M. Morsy, optimized area and optimized speed hardware implementions of AES on FPGA, Design and Test Workshop, 2007. [11] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin and Hung-Yun Tai, The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation, Data, Privacy, and ECommerce, 2007. [12]Huda,S.;Mallick,M.;Anderson,J.H.; Dept.ofECE, Univ. of Toronto, Toronto, ON, Canada“ Field Programmable Logic and Applications, 2009. FPL 2009”. [13]Panato,A.;Barcelos,M.;Reis,R.; Inst. de Informatica,Univ. Fed. do Rio Grande do Sul, Porto Alegre,Brazil Design, Automation and Test in Europe Conference and Exhibition, 2003. [14]Jong-Yeon Park; Okyeon Yi; Ji-Sun Choi; Dept. of Math., Kookmin Univ., Seoul, South Korea “ Information and Communication Technology Convergence” (ICTC), 2010

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PUNNAIAH.S* et al. [IJESAT] INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY

Volume-2, Special Issue-1, 123 – 127

BIOGRAPHIES Punnaiah. Sangati He received B.Tech from JNTU, Kakinada in 2010 and M.Tech pursuing in K L University. His interest focuses on VLSI.

Venkata Ganesh.G He received B.Tech from JNTU, Hyderabad M.Tech from Andhra university in 2007 and 2009 respectively. He is working as Assistant Professor in K L University. His interest focuses on nanoelctronics.

Naresh Kumar Reddy. Beechu He received B.Tech at K.S.R.M.C.E from S.V.UNIVERSITY..MTech pursuing in K.L.UNIVERSITY. He published 6 international journals.

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