This paper presents optimized layout of SR flip flop using NAND gates on 90nm technology. The proposed SR flip flop has been designed using different technology namely fully-automatic design and semi-custom design. In the first approach layout has been generated using fully automatic technique with the help of SR flip flop schematic. In second approach layout has been generated manually by using one finger. In the last approach semicustom layout is further optimized by using two fingers. The area and power consumption of all the designs has been compared and analyzed. It can be observed from the simulated results that SR flip flop with two fingers and SR flip flop with one finger using semicustom technique consumes (62.92% , 91.20%) and (40.04%, 80.40%) less (area, power) as compare to the SR flip flop using fully automatic technique respectively.