ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global Interconnects with Current Mode Signaling Technique Rajib Kar, K.Ramakrishna Reddy, Ashis K. Mal, A.K.Bhattacharjee Department of Electronics & Communication Engg., NIT Durgapur-713209, India Email: {rajibkarece, ramu023}@gmail.com the global interconnects can be reduced by reducing voltage swings on the line. However, in a voltage mode scenario, this means that the signals need to be amplified back, which consumes power and leads to a tradeoff between the circuit power loss and the interconnect power loss [6]. In a current mode situation, the swings can be independently controlled leading to extremely low power consumption in the wire and reduced wire delays. The power analysis of current mode signaling for RC interconnects was presented in [1]. However, the analysis is carried out by considering DC node voltages in dynamic power calculations. In order to model the dynamic power dissipation of current mode signaling, an efficient and accurate as well as generic model is being developed based on modified nodal analysis (MNA) approach. In this work, total analysis is carried out in S-domain in order to estimate dynamic power dissipation accurately at any operating frequency. To the best of our knowledge, there are no such generic closed form expressions available which can estimate the dynamic power dissipation at varying frequency. We have made the following contributions in this literature: A novel and efficient as well as an accurate model is being proposed for the estimation of the dynamic power for global on-chip VLSI RC interconnects. Our proposal is different from [1] in the sense that [1] only can estimate the dynamic power for dc node voltages. On the contrary, using our model, the dynamic power can be accurately estimated at any given frequency. The paper is organized as follows: In section 2, the basic theory regarding the dynamic power dissipation and the modified nodal analysis is being discussed. Section 3 describes the model to calculate the node voltage and the dynamic power for any given frequency. Section 4 shows the dynamic power model for a typical case, i.e. at dc node voltage. Section 5 discusses the results and the comparison to some established methods. And finally section 6 concludes the paper.

Abstractâ€” As the VLSI process technology is shrinking to the nanometer regime, power consumption of on-chip VLSI interconnects has become a crucial and an important issue. There are several methodologies proposed to estimate the onchip power consumption using Voltage Mode Signaling technique (VMS). But the major drawback of VMS is that it increases the power consumption of on-chip interconnects compared to current mode signaling (CMS). A closed form formula is, thus, necessary for current mode signaling to accurately estimate the power dissipation in the distributed line. In this paper, we derived an explicit dynamic power formula in S-domain based on Modified Nodal Analysis (MNA) formulation. The usefulness of our approach is that dynamic power consumption of an interconnect line can be estimated accurately and efficiently at any operating frequency. By substituting s=0 in the vector of node voltages in our model results similar solution as that of Bashirullah et. al. Comparison of simulation results with other established models justifies the accuracy of our approach. Index Termsâ€” Current mode signaling, On-chip Interconnect, MNA Analysis, Dynamic Power.

I. INTRODUCTION The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performance while the dynamic power dissipation of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. Signaling across long global on-chip interconnects is rapidly becoming a performance limiter due to reverse interconnect scaling trends. Traditionally, voltage mode repeaters along the interconnect have been used to reduce the delays in signal transmission. However, there is a limit in the performance improvement that can be obtained with repeaters in deep submicron designs in terms of power and delay [5], [7]. Current mode signaling has been explored as an alternative choice for data transmission over interconnects in [1], [4], and [8]. Power consumption on Corresponding author: RAJIB KAR Email: rajibkarece@gmail.com

27 ÂŠ 2010 ACEEE DOI: 01.IJEPE.01.03.90

ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

A. Dynamic Power Model We can not accurately model the dynamic power dissipation of current mode circuits by the following well known equation:

II. BASIC THEORY Long global interconnects can be modeled by distributed RC transmission lines as long as the overall line resistance dominates the response (i.e. R>>jwL). These RC interconnect lines can be driven either by voltage-mode or current-mode signals. For Current mode signaling, interconnect terminates at a finite resistance in addition to a capacitive load, as shown in fig. 1.

Pd=Vdd2 Ct f

(A)

Since it assumes that all the capacitive components of a distributed RC line are charged to Vdd. As illustrated in fig. 2, the voltage at any point of a resistively terminated line will be less than Vdd, resulting in smaller dynamic power dissipation components. In order to accurately model this effect, we find voltage at each node of an N-segment distributed RC line by using modified nodal analysis. B.

Figure 1.

Modified Nodal Analysis Approach The distributed RC network shown in figure 1 , can be conveniently expressed in terms of state equations by using Modified Nodal Analysis representation (MNA) [2-3]. The generalized output equation can be expressed in the Laplace domain as: (1) [G + sC ] ⋅ [X(s )] = b(s ) Where G and C are the nodal conductance and capacitance matrices, respectively. X is vector of node voltages and b(s) is the input source excitation.

Generalized distributed RC model

A generalized model for a driven distributed RC line is shown in Fig. 1. The diver is modeled as a voltage source with output resistance RS. For the sake of generality the output of the line is terminated with a resistor RL, and load capacitance CL. For voltage-mode signaling, the termination resistance RL is infinite and the output voltage is seen across CL. In current mode signaling (CMS), the terminating resistance RL is finite. Power dissipation in current mode circuits are classified into three components: static, dynamic and short circuit power dissipation components. Static power dissipation component arises from the constant current path from Vdd to ground via the resistive termination RL as shown in fig. 2. The dynamic power is dissipated when the capacitive components are charged through the PMOS device and discharged via the NMOS device. The third source of power dissipation arises from the finite input signal edge rates that result in short-circuit current. Generally, careful control of input edge rates can minimize the cross-over current component to within 20% of the total dynamic power dissipation [9].

⎡Gs1 + Gu ⎢ −G u ⎢ ⎢ 0 [G ] = ⎢⎢ ... ⎢ ... ⎢ ⎢ ... ⎢ 0 ⎣

− Gu 2Gu

0 − Gu

... 0

... ...

− Gu ... 0

2Gu ... − Gu

− Gu ... 2Gu

0 ... − Gu

... ...

0 0

− Gu 0

− Gu

2Gu

⎤ ⎥ ⎥ ... ⎥ ⎥ ... ⎥ 0 ⎥ ⎥ − Gu ⎥ GL + Gu ⎥⎦ 0 0

(2)

Gu is the segment conductance of the distributed transmission line and GL is the load conductance. Gs1=1/(Rs+Ru); where Rs is the source resistance The capacitance matrix of the distributed RC line is: ⎡Cu ⎢0 ⎢ ⎢0 [C ] = ⎢⎢ ... ⎢ ... ⎢ ⎢ ... ⎢0 ⎣

0u

0

...

...

Cu 0u

0 Cu

0 0

... 0

...

...

...

...

0

0

Cu

0

...

0

0

Cu

...

0

0

0

⎤ ⎥ ⎥ ⎥ ⎥ ... ⎥ 0 ⎥ ⎥ 0 ⎥ Cu + CL ⎥⎦ 0

0 ...

(3)

Where Cu is the segment capacitance of the distributed transmission line and CL is the load capacitance. III. POWER DISSIPATION FOR AC NODE VOLTAGES

Figure 2. Power dissipation in interconnect line for current mode signaling

In order to determine dynamic power dissipation of the distributed line, node voltages are required. The node voltage vector X(s) can be determined by using (1). 28

© 2010 ACEEE DOI: 01.IJEPE.01.03.90

ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

A general closed form expression for ith node voltage of X(s) is given by,

(4) [ X ( s )] = [G + sC ]−1 b( s ) A general closed form expression for ith node voltage of X(s) is given by:

vi =

( A +1)A ⎡ ⎤ ⎢ AGu .GL + 2 Gu sCu ⎥ (5) 1 vi = (vdd .Gs1 ) ⎢ ⎥ D ⎢+ G2 + A.G sC + ( A +1)( A −1)A sC G ⎥ u u L u L 6 ⎣⎢ ⎦⎥ Where A = N-i (6) D = X+Y

X . = mG s1 G L G u + G s1 G + mG u G s1 sC L +G G L 2 u

2 u

⎡ mN ⎤ 2 2 ⎢ 2 Gs1Gu sCL + NGu sCu + Gu sCL ⎥ Y =⎢ ⎥ ⎢+ mN G G sC + nC G sC G ⎥ u L u N −3 s1 u L ⎣⎢ 2 ⎦⎥

N

i =1

i =1

Pdyn = ∑ Pi = ∑ v C i f ⋅ act

A = N-I

(16)

(8)

Where,

2

2 ⎡ R N (N + 1)(2 N + 1) ⎛ Ru ⎞ ⎤ ⎜ ⎟ ⎥ Q = ⎢ N + N (N + 1) u + ⎜ ⎟ RL 6 ⎝ RL ⎠ ⎥⎦ ⎣⎢

(9)

final (17)

(18)

As N approaches infinity in the above equation, (18) results a closed form expression for total dynamic power dissipation for current mode circuits. It is given as, 2 (19) Pdyn = (α ⋅ vdd ) f ⋅ act ⋅ K And k and α are defined as, ⎡ ⎛ R 1⎛ R K = ⎢C L + C t ⎜1 + t + ⎜⎜ t ⎜ RL 3 ⎝ RL ⎢ ⎝ ⎣ RL α= R L + R s + Rt

⎞ ⎟⎟ ⎠

2

⎞⎤ ⎟⎥ ⎟⎥ ⎠⎦

(20) (21)

Where, Rt =N Ru

(22)

and Ct = N Cu

(23)

The expression (19) is much similar to the established model [1]. For a given frequency, (11) gives better result when compared to (19), since its node voltages depends upon the operating frequency. Note that as RL approaches, infinity (i.e. voltage-mode), (19) reduces to the more familiar dynamic power dissipation formulation of voltage-mode circuit. The static power dissipation component of an interconnect line for current-mode signaling can be expressed as: Vdd2 (24) p stst = Rs + R L + Rt

On substituting s=0 in (4), the DC node voltages are obtained. It can be written as, (12) −1

Ginv is the inverse matrix ( G ) which can be expressed as:

Equation (24) signifies that the static power dissipation component dominates for low interconnect resistance line (i.e Rt < 500 Ω), indicating that current mode signaling should be used for long global interconnects to minimize the total power dissipation

(13)

V. SIMULATION RESULTS In order to verify the accuracy of the proposed power model, it is compared with the well excepted model proposed in [1]. The results are based on (11), (19) and other established model [1] for 0.18-µm process with

Where k and i are row and column of an inverse matrix −1

( G ). 29 © 2010 ACEEE DOI: 01.IJEPE.01.03.90

(15)

Pdyn = (α ⋅ v dd ) f ⋅ act ⋅ (C u ⋅ Q + C L )

IV. POWER DISSIPATION OF DC NODE VOLTAGES

⎧ [Gu + ( N − k )GL ]⋅ [Gu + (i − 1)Gs1 ] ⎪ G [G G + ( N − 1)G G + G G ] ∈ i ≤ k L s1 L u ⎪ u u s1 ⎪ Ginv (k , i ) = ⎨ ⎪ ⎪ [Gu + ( N − i )GL ]⋅ [Gu + (k − 1)Gs1 ] ⎪ G [G G + ( N − 1)G G + G G ] ∈ i > k L s1 L u ⎩ u u s1

D. = mG s1G L Gu + G s1G u2 +G u2G L

(7)

Evaluating the summation in closed-form gives total dynamic power dissipation for current-mode circuits. The usefulness of our approach is that power consumption of an interconnect line can be estimated accurately at any operating frequency.

[X(s )] = [G ]⋅−1 b(s )

(14)

By substituting these node voltages in (11) gives expression for total dynamic power dissipation is,

(11)

2 i

]

Where

Here m = N-1; where N is number of nodes in distributed line In (8), higher order terms are not considered since product of s and C (Cu or CL) for higher powers is almost zero. The dynamic power at each node can be written as (10) Pi = vi2 C i f ⋅ act Where Ci is the capacitance at each node and act is the switching activity factor. Hence, the total dynamic power dissipation can be expressed as, N

[

1 (vdd.Gs1 ) AGu .GL + Gu2 D

ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

interconnect resistance (Rt) and capacitance (Ct) varied from 50Ω-1000Ω resistance and 100fF-2pF, respectively. Other pertinent parameters are defined as follows:

dissipate more dynamic power when compared to current mode circuits. Comparison of dynamic power dissipation expression (for s=0) and Bsh model for typical values of RL is shown in table 1. From table 1, we find that our model is much similar to the Bsh model for current mode signaling at dc node voltages i.e. at s=0. We can easily extend our result to voltage mode (By substituting RL = ∞ and RS = 0 ). If we do so, we will get the similar expression as that of [1].

f clock

=2GHz, Vdd =l.8V, Wp/Wn=3, activity factor act=0.5, Rs=50 Ω, CL =50pf and RL =100 Ω.

-3

3.5

x 10

our work for s=0 our work Bsh model

3

VI.

power(w)

2.5

A closed form expression for the dynamic power dissipation of a driven distributed RC line is derived in Laplace domain for current mode signaling. The expression is modeled in such a way that power dissipation in distributed line is estimated accurately at any operating frequency. For a typical case, the closed form power dissipation expression, on substituting s=0 in our model, is also presented. The derived expression along with this analysis can serve as a convenient tool for dynamic power estimation without much computation during design.

2

1.5

1

0.5

0

0

0.5

Figure 3.

1

1.5

2

2.5 RC(sec)

3

3.5

4

4.5

5 -9

x 10

Dynamic power dissipation for different values of RC with RL=100 Ω

TABLE I.

Fig. 3 illustrates the dynamic power dissipation dependency on interconnect RC delay (i.e Rt.Ct) for current mode drivers. Above figure signifies that our proposed model is having higher accuracy than the Bsh model [1] at 2GHz frequency. The reason that our approach is showing lesser power dissipation because of the fact that we are dealing with the ac node voltage in the power dissipation calculation. For dc node voltage (i.e. s=0) the magnitude of the dynamic power dissipation will be higher compared to that of the ac nodes.

1

power(mW)

Bsh

1 1.5 2 2.5 3

1.5 1.9 2.2 2.4 2.6

RC(ns) RL=100 RL=200 RL=500 RL=1000 RL=inf(VM)

1 1.5 2 2.5 3

0.8

DYNAMIC POWER DISSIPATION (MW) FOR CMS WITH R L =100 Ω, CL=50PF

RC(ns)

TABLE II.

1.4

1.2

CONCLUSION

Our work for s=0 1.5 1.9 2.2 2.4 2.6

Our work 0.68 0.81 0.91 1.0 1.1

DYNAMIC POWER DISSIPATION (MW) FOR CMS WITH R L=150 Ω, CL=50PF Bsh 1.6 2.0 2.3 2.5 2.7

Our work for s=0 1.6 2.0 2.3 2.5 2.7

Our work 0.71 0.85 0.93 1.0 1.1

0.6

TABLE III. 0.4

0.2

0

0

0.2

0.4

0.6

0.8

1 RC(ns)

1.2

1.4

1.6

1.8

2

Figure 4: dynamic power dissipation for different values of RL

Fig. 4 illustrates the dynamic power dissipation dependency on load resistance RL. In figure 4, as load resistance increases, the dynamic power dissipation increases indicating that voltage mode circuits (i.e. RL = ∞ ) 30 © 2010 ACEEE DOI: 01.IJEPE.01.03.90

DYNAMIC POWER DISSIPATION (MW) FOR CMS WITH R L =200 Ω, CL =50PF

RC(ns)

Bsh

1 1.5 2 2.5 3

1.7 2.1 2.4 2.6 2.8

Our work for s=0 1.7 2.1 2.4 2.6 2.8

Our work 0.73 0.85 0.96 1.1 1.1

ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

[6] C. Svensson, “Optimum Voltage Swing on On-Chip and OffChip Interconnect,” IEEE Journal of Solid State Circuits and Systems, 29, No.6:663-670, June 1994. [7] D. Sylvester and K. Kuetzer, “Getting to the Bottom of Deep Submicron II: The Global Wiring Paradigm,” Proceedings Of international Symposium on Physical Design, Pages 193200 April 1999. [8] Venkatraman and W. Burleson, “Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations,” Proceedings of Sixth International Symposium on Quality Electronic Design, pages 522– 527, March 2005 [9] M. K. Gowan, L.L. Biro, D.B. Jackson, “Power considerations in the design of the Alpha 21264 microprocessor,” Proc. Design Automation Conference, pp 726-731,1998.

REFERENCES [1] R. Bashirullah, W. Liu, and R. Cavin, “Delay and power model for current-mode signaling in deep submicron global interconnects,” Proceedings of IEEE Custom Integrated Circuits Conference, May 2002, pp. 513 -516. [2] M. Celik, L. Pileggi, A. Odabasioglu, IC Interconnect Analysis, Kluwer Academic Publishers, 2002. [3] C.W. Ho, A.E. Ruehli, P.A. Brennan, “The modified nodal Approach to network analysis,” IEEE Trans. Circuits and Systems, Vol. CAS-22, pp. 504- 509, June 1975. [4] I Dhaou, M. Ismail, and H. Tenhunen. Current mode ,Low Power ,On –Chip Signaling in Deep Sub-micron CMOS Technology, IEEE Transactions on Circuits and Systems ,50,No.3:397-406,March 2001 [5] D. Liu and C. Svensson. Power Consumption Estimation in CMOS VLSI Chips, IEEE Journal of Solid State Circuits and Systems, 29, No.6:663-670, June 1994.

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An Explicit Approach for Dynamic PowerEvaluation for Deep submicron GlobalInterconnects

As the VLSI process technology is shrinking to the nanometer regime, power consumption of on-chip VLSI interconnects has become a crucial an...

An Explicit Approach for Dynamic PowerEvaluation for Deep submicron GlobalInterconnects

Published on Jan 19, 2013

As the VLSI process technology is shrinking to the nanometer regime, power consumption of on-chip VLSI interconnects has become a crucial an...

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