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Short Paper Proc. of Int. Conf. on Research Methodologies in Electronic Devices and Circuits 2012

Optimized Parasitic Resistance Performance of MultiFin Device Y. Manish1, Kondekar P. N., Jawar Singh, and Apurba Chakrborty Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India 1 manish1010204@iiitdmj.ac.in II. EXPREMENTAL DEVICE STRUCTURE

Abstract—Multi-Fin device with reduced parasitic series resistance has been designed and characterized by using 3-D TCAD simulator. Space between fins is utilized by lateral extension of silicon region. This leads to increased crosssectional area of the device. We found significant current density in the extended region. Drive current performance improved to 20% without degrading the sub-threshold current & Drain induced barrier lowering (DIBL) effects. Also, width of device is reduced by using single insulated metal gate stack.

The 3D device structure shown in the Fig.1 (a) & (b) is designed using DEVEDIT. The structure shown in Fig.1 (b) had common gate between the two fin regions. Also, extension source/drain region laterally extended to increase the crosssectional area of device. Since the common gate stack was used total width of device was also optimized in comparison to previous device. Width of fin is 12 nm to provide the optimum gate control. Source/drain was highly doped with arsenic impurities. In the region extended laterally lightly ntype doped profile was used [7]. Ohmic contact with appropriate work function was employed to satisfy the metal contact properties.

Index Terms—Multi-Fin, Parasitic series resistance, Subthreshold current, DIBL

I. INTRODUCTION The FinFET device leading as a most promising structure for further scaling the CMOS technology [1]. Device with multi gate structure have an advantage of better control on the channel leads to reduced short channel effects. As, shrinking with the physical dimensions, increased parasitic resistance is the prominent challenge to semiconductor device. Because increased parasitic resistance leads to reduced drive current. Thus, Multi-Fin device is most suitable for replacement to Single fin device due to their better drive current capability but compromising to dimensional constraints of the device. Further, impediment to decrease the width is the poor performance of parasitic resistance. The regions that contribute to parasitic resistance are channel region, extended fin region, extended source/drain regions & contacts. The literature related to FinFET device is flooded with enormous approaches to reduce the parasitic resistance. Such as, ion implantation of tellurium in n-FinFET [2] and aluminum in p-FinFET [3] source/drain contact region is used to reduce the contact resistance. Material like SiC, SiGe are used over silicon source/drain region as stressing [4] element to enhance the mobility of the carriers, also the various design such as body connected STI-FinFET [5] and extension source/drain region[6] are present in the literature. All these innovative designs and research concepts lead to reduced parasitic resistance of the device. In this paper, by lateral extension of silicon material in the valley of extended fin regions of Multi-Fin structure, area of cross-section for the conduction of current is increased. Since, the area of cross section is inversely proportional to resistance, hence parasitic resistance of the device reduced.

© 2012 ACEEE DOI: 02.EDC.2012.01. 3

Fig.1 (a)

Fig.1 (b) Fig.1(a). Without lateral extension (conventional). lateral extension

(b) With

The optimized device parameters involves in designing the structure are shown below in Table-I. 115


Short Paper Proc. of Int. Conf. on Research Methodologies in Electronic Devices and Circuits 2012 T ABLE I.

Device simulation was done by using Atlas simulator. While the simulation, energy balanced transport model [8] were used to couple the carrier density to carrier temperature. It is the advantage for accuracy over only poison’s equation and continuity equation for the carrier used in the drift diffusion transport model. Lombardi CVT & Shottkey reduction hall (SRH) models were added to include mobility variations with transverse electric field and recombination behaviour of the carrier respectively. III. RESULTS AND DISCUSSION Propose device structure was extensively optimized with the prospects of characteristics as well as dimension. In this section device characteristics & contour plots related to device performance were analysed using tony plot tool. In Fig.2 contour plot for total current density were shown. It was observed that the current density is increase in laterally extended region. Since, extended area between the fins is analogous to increase in width of conventional MOSFET. Similar to increase width in MOSFET, extended region have inverse relation with resistance. The relation observed is responsible for increase in drain current by á time to conventional multi fin device, where á =1.2. Advantage of increased current acquired in the proposed device would be responsible factor for high gain in the device.

conventional Multi-Fin device. Due to gate control acquired form the two parallel sides of thin fin it was observed that in the region between the gates vertical field were dominating the horizontal field. Since it was a primary advantage of FinFET device to acquire optimum control on channel, this advantage is retained in the proposed device. Better gate control is directly responsible for its advantages in digital circuit such as efficient noise margin, switching properties etc.

Fig.3. Equipotential lines between the gates showing the input control

Fig.4 shows the output characteristic comparison of the proposed device with conventional multi fin devices. Device simulation was performed on different gate voltages (Vg) with the entire gate on same voltage. It was observed from the simulated results that saturation as well as linear current increased by 20% at all gate voltage compared. Current increased in the proposed device shows inverse relation of resistance with laterally extended fin region. Further reason behind such performance is low parasitic resistance of the device. Fig.5 shows sub-threshold current in the proposed device was remained similar even with improved drive current. Since sub-threshold current is proportion to depletion capacitance & though increase in laterally extended region, increased depletion region is negligible.

Fig.2. Total current density plot showing high density in laterally extended region

Also, from potential contour plot shown in Fig.3, it can be seen that widths of fin between the gates were same to the 116 © 2012 ACEEE DOI: 02.EDC.2012.01.3

Fig.4. Showing the comparison of drive current between the two devices


Short Paper Proc. of Int. Conf. on Research Methodologies in Electronic Devices and Circuits 2012 In the proposed design, by using lateral source/drain extension, parasitic resistance of device was optimized. It was experimentally verified by using TCAD tool that the 20% improvement in the saturation current was observed. In spite of such improvement short channel effect of the device was well controlled. Contour plots shown were validating the current flow in lateral extension part & also, the optimum potential control of gate over the channel. ACKNOWLEDGMENT Authors would like to thank Discipline Co-ordinator, electronics & communication engineering department and Silvaco, Inc. for providing the simulation facility in IIITDM Jabalpur. REFERENCES Fig.5. Input current plot with logarithmic drain current axis showing comparison of off current

[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H.Takeuchi, K. Asano,C. Kuo, E. Anderson, Tsu-Jae King, J. Bokor, C. Hu, “FinFET—A self-Aligned double-Gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000. [2] Shao-Ming Koh, Eugene Yu-Jin Kong, Bin Liu, Chee.Mang Ng, G.S. Samudra, Yee-Chia Yeo “Contact resistance reduction for strained n-FinFETs with silicon–carbon source/ drain and platinum-based silicide contacts featuring tellurium implantation and segregation,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3852-3862, Nov. 2011. [3] Sinha M., Lee, Rinus T. P, Eng Fong Chor, Yee-Chia Yeo “Contact resistance reduction technology using aluminum implant and segregation of strained p-FinFETs with silicongermanium source/drain,” IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1279-1286, Jun. 2010. [4] T. Y. Liow, K.-M. Tan , D. Weeks , R. T. P. Lee , M. Zhu , K.M. Hoe, C.-H. Tung , M. Bauer , J. Spear , S. G. Thomas , G. S. Samudra , N. Balasubramanian and Y.-C.Yeo “Strained nchannel FinFETs featuring in situ doped silicon-carbon sourcr and drain stressors with high carbon content”, IEEE Trans. Electron Devices,  vol. 55,  no. 9,  pp.2475 -2483, Aug. 2008. [5] Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, “A new STItype FinFET device structure for high performance applications,” in symp. Next Generation Electronics 2010, pp. 25-27. [6] J. Kedzierski, M. Ieong, E. Nowak, Thomas S. K, Y. Zhang, Ronnen Roy, D. Boyd, David Fried, and H.-S. Philip Wong, “Extension and source/drain design for high-performance FinFET devices” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, Apr. 2003. [7] V. Ramanjaneula, S. Baisya, R. H. Laskar , “Optimization consideration of undoped raised source/drain FinFET with effective SCE control “ in Conf. 2nd ICMME 2010, pp. v150-v1-153. [8] User manual, Atlas. Silvaco, inc. Oct. 2011.

Fig. 6 shows the comparison of variation in threshold voltage of both devices when biased at 0.2 V & 1.2 V. It was observed that threshold voltage variation in the proposed structure was 0.021V & it was similar to previous structure. Similarly as it is analysed from the threshold variation that drain induced barrier lowering is 21mV/V & similar for both the structure.

Fig.6.Threshold voltage variation with drain biasing at 0.2V and 1.2V

CONCLUSIONS Parasitic resistance of the FinFET device are increasing as width of fin is scaling down. Since channel in the devices shrinking, transverse electric field was dominating the perpendicular electric field. So, scaling down the width of fin became stringent need to acquire optimum control over the gates in multi-gate device.

© 2012 ACEEE DOI: 02.EDC.2012.01. 3

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