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Full Paper Proc. of Int. Conf. on Advances in Electrical & Electronics 2012

TCAD Linearity Performance Evaluation of Gate Workfunction Engineering in Surrounding Gate Silicon Nanowire MOSFET Nishant Aggarwal1, Ishan Gupta2, Kshitij Sikka2, and Rishu Chaujar2 1

Microelectronics Research Laboratory, Applied Physics Department, Delhi Technological University, Delhi, India Email: 2 Microelectronics Research Laboratory, Applied Physics Department, Delhi Technological University, Delhi, India Email:,, vided Dual Material Gate (DMG) with work function Φm1=5.5eV & Φm2=4.7eV. The oxide permittivity, εOX=3.9, substrate doping, NA=6×1019 cm-3, source/drain doping, ND+=1×1020 cm-3. The gate/channel length (Lg) and gate oxide thickness (tox) used for comparison are 30nm and 2nm respectively.

Abstract: In this paper a comparative study of device linearity metrics for conventional MOSFET, conventional Surrounding Gate-Silicon Nanowire (SG-SNW) MOSFET and Surrounding Gate Electrode Workfunction Engineered-Silicon Nanowire (SGEWE-SNW) MOSFET has been done using TCAD simulations. SGEWE-SNW  MOSFET  possesses  better  device linearity in comparison to its counterparts. This is because SGEWE-SNW  MOSFET  integrates  the  potential benefits of SNW MOSFETs with Dual Material Gate (DMG) architecture for enhancing the digital, switching and RF performance. The effect of variation in gate/channel length (Lg) and workfunction (Φm2) in SGEWE-SNW MOSFET on linearity performance characteristics has further been explored.

III. EQUATIONS The realization of a highly efficient linearized amplifier has emerged as a paramount issue in the RFIC design and wireless communication systems. Distortion and Linearity are key issues in the design of many types of circuits. The Volterra series has long been used to analyze distortion in analog circuit. The Volterra series is a Taylor series that simplifies to a power series when the system is memoryless. It describes a signal as a summation of the linear behaviour, the second order behaviour, the third order behaviour, and so on. Taylor series are usually used for weakly nonlinear circuit analysis because it is simple. However, it is not applicable to highly nonlinear applications such as power amplifiers. Unlike numerical simulations which give no information about the source of the distortion, closed form expressions for distortion components in terms of circuit parameters can be found using Volterra series. Unfortunately, the method of presenting the Volterra series analysis is complex and often intimidating to the uninitiated. Consequently, the Volterra series is often under-utilized by circuit designers. Circuit designers prefer to work with linear models of circuits but more accurate models which take into account the nonlinearities in a circuit are often required. Many practical circuits can be assumed to behave in a weakly nonlinear way, and under this condition, closed form expressions for the nonlinearity can be obtained using the Taylor series. In this paper, the basic of linearity analysis is presented by employing Taylor-series expansion and the expansion coefficients are extracted from the ATLAS device simulator [7]. The drain current in Taylor expansions [8] can be expressed as follows: IDS(VGS,VDS) = IO + GM.VGS + GD.VDS + GM2.V2 + GMD.VGS.VDS + GD2.V2 + GM3.V3 + GM2D.V2 .VDS + GMD2.VGS.V2 + GD3.V3 + (1) …………… Assuming that the drain is shorted at a signal frequency, all output-conductance terms (g d, g d2, g d3, ...) and cross

Index Terms — TCAD, Linearity, SGEWE-SNW MOSFET, DIBL.

I. INTRODUCTION The search for high performance ICs has led to scaling of MOSFETs down to sub-50nm regime and SNW MOSFETs offer a promising solution for realizing CMOS technology [1, 2]. Linearity behaviour of MOSFETs is imperative for lownoise applications. In the nanometre regime, SNW MOSFET is a propitious contender for CMOS applications [3-5]. RF-distortion and linearity has been determined by metrics gm1, gm3, VIP3, 1-dB compression point, IIP3 [6]. gm1 represents transconductance, gm3 is the third order derivative of drainsource current (I ds) with respect to gate bias (Vgs) and represents third order harmonic; V IP3 represents the extrapolated input voltage at which first and third-order harmonic voltages are equal; 1-dB compression point is the input signal level that causes the small-signal gain to drop by 1 dB; IIP3 represents the extrapolated input power at which first and third-order harmonic powers are equal. For high linearity and low distortion operation, gm1, V IP3, 1-dB compression point, IIP3 should be as high as possible and gm3 should be low. II. DEVICE STRUCTIRE Conventional MOSFET and SG-SNW MOSFET structures consisted of a metal gate with work function Φm=5.5eV while SGEWE-SNW MOSFET structure consisted of a equally di© 2012 ACEEE DOI: 02.AETAEE.2012.3. 29


Full Paper Proc. of Int. Conf. on Advances in Electrical & Electronics 2012 harmonics are cancelled out. The third order harmonic, which is represented by ‘gm3’, thus, determines a lower limit on the distortion and therefore, the amplitude of gm3 should be minimized. Thus, reducing gm3 and increasing the transconductance (gm1) acts as a viable solution to improve device linearity. Value of gm3 particularly determines a lower limit on distortion and, therefore, amplitude of gm3 should be minimized. At the same time, VIP3, IIP3 and P1dB should be as high as possible. SGEWE-SNW MOSFET provides superior values of gm1, gm3, VIP3, 1-dB compression point, IIP3 in comparison to SGSNW MOSFET as can be observed from Fig4, Fig5, Fig6, Fig7, Fig8 respectively. This is due to increase in carrier transport efficiency and gate control over the channel because of decrease in Drain Induced Barrier Lowering (DIBL) [11]. This in turn is a consequence of workfunction difference introduced by the DMG architecture [12]. On evaluating the effect of Lg variation on linearity of SGEWE-SNW MOSFET it is observed from Fig4 that gm1 decreases as Lg gradually increases. This is because as Lg increases, threshold voltage increases. This weakens gate control over the channel, thereby degrading g m1 and increasing gm3. It can be seen from Fig7 that 1-dB compression point is higher for Lg=30nm as compared to Lg=35nm. VIP3, IIP3 values are greater while gm3 is lesser for Lg=30nm (Fig6, Fig8 and Fig5). On considering the screening metal workfunction variations, it is observed that according to gm1, VIP3, 1-dB compression point, and IIP3 (Fig4, Fig6, Fig7 and Fig8) SGEWE-SNW MOSFET with Φm2=4.7eV (workfunction difference of 0.8eV) has better linearity as compared to Φ m2=4.9eV, 5.1eV. Thus, decreasing the workfunction difference below 0.8eV degrades the device linearity performance.

modulation terms (gmd, gm2d, gmd2, ...) are vanished and only transconductance terms (gm, gm2, gm3, ...) remain. The transconductance coefficients gmn (gm1 and gm3 have been used in this paper) and device linearity analysis metrics VIP2, VIP3 and IIP3 are defined as : (2) Thus,




(6) (7) RS = 50 Ω for most RF applications. To compare the linearity and intermodulation distortion performance of SNW MOSFETs, all devices were optimized at a threshold voltage (Vth) of 0.15 V, which thus accounts for a meaningful comparison. IV. LINEARITY ANALYSIS The conventional MOSFET structure having above stated specifications possesses threshold voltage which is an order higher as compared to SG-SNW MOSFET and SGEWE-SNW MOSFET as can be seen from Fig2, thus conventional MOSFET can be omitted and hence its linearity performance evaluation metrics need not be calculated for drawing out a meaningful comparison. This omission was further supported by the obtained ON current (ION) values (Fig3). Also, SG-SNW MOSFET and SGEWE-SNW MOSFET have better gate control owing to their surrounding gate architecture. This demonstrates poor short channel performance of conventional MOSFETs. SGEWE-SNW MOSFET Lg variations used are 30nm, 35nm and the linearity metrics have also been computed for screening metal workfunction (Φm2) variations viz. 4.7ev, 4.9ev, 5.1ev (gradually decreasing workfunction difference of the two metals). The comparison has been done by optimizing all devices at Vgate=0.15V and incorporating Hydrodynamic, Bohm Quantum Potential (BQP) models for accounting the quantum effects significant at nanoscale dimensions [9, 10].   Second order nonlinearity results in second order intermodulation and linearity and third order nonlinearity results in third order intermodulation and linearity. In MOS circuits, harmonic distortion is present due to the nonlinearity exhibited by higher-order derivatives of IDS-VGS characteristics. In the circuits using balanced topologies, even-order © 2012 ACEEE DOI: 02.AETAEE.2012.3. 29

Fig1. Simulated SGEWE-SNW MOSFET Device structure

V. CONCLUSION The work presents a vital module of technological design process to build a distortion resistant device design, exhibiting enhanced analog performance for the use in ULSI technology. Intensive 3-D simulations have been performed 60

Full Paper Proc. of Int. Conf. on Advances in Electrical & Electronics 2012 to scrutinize the role of gate electrode workfunction engineering in Surrounding Gate Silicon Nanowire MOSFETs. A comparison of the figures of merit for analog and large signal performance of gate length variations (30 nm, 35 nm), it was found that the performance enhancement in SNW MOSFETs is through enhanced gate control that improves the device efficiency and speed to power dissipation performance .i.e. linearity decreases as gate/channel length increases. At the same time, the performance enhancement can be achieved by increasing the workfunction difference between the controlling gate metal (M1) and screening gate metal (M2). The work therefore presents SNW MOSFET design as a promising contender and opens up the door to single-chip solutions for low-power telecommunication applications. It can thus, be inferred from linearity performance evaluation metrics that in sub-50nm regime, SGEWE-SNW MOSFET possesses superior linearity (which decreases with increase in Lg and decrease in workfunction difference) as compared to conventional MOSFET and SNW MOSFET thus proving their efficacy for high performance ULSI applications.

Fig4. Simulated gm1 characteristics for SNW MOSFET and Lg, Φm2 variations of DMG SNW MOSFET, devices optimized at V th=0.15V

Fig5. Simulated gm3 characteristics for SNW MOSFET and Lg, Φm2 variations of DMG SNW MOSFET, devices optimized at V th=0.15V

Fig2. Vth for SMG SNW MOSFET, DMG SNW MOSFET and Conventional MOSFET

Fig6. Simulated VIP3 characteristics for SNW MOSFET and Lg, Φm2 variations of DMG SNW MOSFET, devices optimized at V th=0.15V


© 2012 ACEEE DOI: 02.AETAEE.2012.3. 29


Full Paper Proc. of Int. Conf. on Advances in Electrical & Electronics 2012 [2] Nishant Aggarwal, Kshitij Sikka, Ishan Gupta, Rishu Chaujar, “Linearity evaluation of Silicon Nanowire Surrounding Gate MOSFET for high performance ULSI applications” in Techconnect World Summit and Innovation Showcase 2012, Nanotech 2012 Vol.2 pp. 570-573, 18-21 June 2012. [3] Fatemeh karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour, “A Comparison Study of Electrical Characteristics in Conventional Multiple-gate Silicon Nanowire Transistors”, World Academy of Science, Engineering and Technology, issue 69, pp. 463-466, September 2010. [4] Rajni Gautam, Manoj Saxena , R.S. Gupta , Mridula Gupta, “Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis”, Microelectronics Reliability, Volume 52, Issue 6, June 2012, Pages 989–994. [5] Y. Cui, Z. Zhong, D. Wang, W.U. Wang, C.M. Lieber, “High performance silicon nanowire field effect transistors”, Nano Letters, Volume 3, Issue 2, 1 February 2003, Pages 149-152. [6] Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta, “Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design” in Superlattices and Microstructures, Volume 44, Issue 2, August 2008, pp. 143152. [7] ATLAS User’s Manual, Silvaco. [8] S.Kang, B.choi, B.Kim, “Linearity of CMOS for RF application”, IEEE Tansactions on Microwave Theory and Techniques, Volume 51, Issue 3, pp. 972-977, March 2003.and Techniques, Volume 51, Issue 3, pp. 972-977, March 2003. [9] Vijay Sai Patnaik, Ankit Gheedia and M. Jagadesh Kumar”, 3D Simulation of Nanowire FETs using Quantum Models” in Simulation Standard, Vol. 18, No.3, pp.6-12, July-Sept 2008. [10] G. Iannaccone, G. Curatola, G. Fiori, “Effective Bohm Quantum Potential for device simulators based on drift diffusion and energy transport” in Simulation of Semiconductor Processes and Devices 2004, vol. 2004, pp. 275-278, Sept. 2004. [11] Wang Zhou, Lining Zhang, Yiwen Xu, Lin Chen and Frank He, ‘Simulation study on a new dual-material nanowire MOS surrounding-gate transistor”, Journal of Nanoscience and Nanotechnology, Volume 11, Issue 12, 2011, Pages 1100611010 [12] Wei Long, Haijiang Ou, Jen-Min Kuo, and Ken K. Chin, “DualMaterial Gate (DMG) Field Effect Transistor” in IEEE Tansactions on Electron Devices, Volume 46, Issue 5, pp. 865-870, May 1999.

Fig7. Simulated 1-dB compression points,for SNW MOSFET and Lg, Φm2 variations of DMG SNW MOSFET, devices optimized at Vth=0.15V

Fig8. Simulated IIP3 characteristics for SNW MOSFET and Lg, Φm2 variations of DMG SNW MOSFET, devices optimized at V th=0.15V

REFERENCES [1] Toshiro Hiramoto,” From Bulk toward FDSOI and Silicon Nanowire Transistors: Challenges and Opportunities” in Ultimate Integration on Silicon (ULIS), 2011 12th International Conference, pp. 1-2, 14-16 March 2011.

© 2012 ACEEE DOI: 02.AETAEE.2012.3. 29


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