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Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

Analysis and Minimization Technique for Leakage Reduction in Two Input NOR gate 1Vaibahav

Neema ,2Sanjiv Tokekar

1Lecturer 2Professor

Department of Electronics & Telecommunication IET Devi Ahilya University, Indore vaneema.iet, 1 2sanjivtokekar{}

Abstract :-Leakage current in CMOS circuit technology is a major concern for technology node below to the 100nm as it drains the battery even when a circuit is completely idle. this paper proposed a novel approach to minimize leakage current in CMOS circuit during the off state (or Standby Mode , Sleep Mode).In this paper we first present a novel leakage reduction technique over Two Input NOR gate and then compare it with well established leakage reduction technique. Our proposed leakage reduction technique control leakage current for all possible input vector applied to Two Input NOR gate.

achieve high levels of performance (speed) and utilize less area. However, they require two operation phases: precharging and evaluation. They cannot be scaled easily due to their low noise immunity, and require keeper circuits to restore logic levels. On the other hand, fully Complementary Metal Oxide Semiconductor (CMOS) styles are usually robust, dissipate low power, have fully restored logic levels, and are easily scalable. II. APPLICATION aREA

Experiment conducted using TANNER EDA tool for 90 nm Predictive Technology Model file with 1V supply voltage. Result shows that successfully 90 % of static power reduction is obtain with small delay penalty using proposed technique.

Cell phones and pocket PCs have burst-mode type integrated circuits, which for the majority of the time are in an idle state. For such circuits, it is acceptable to have leakage during the active mode. However, during the idle state it is extremely wasteful to have leakage, as power is unnecessarily consumed with no useful work being done. Given the present advances in power management techniques [6], leakage loss is a major concern in deepsubmicron technologies, as it drains the battery, even when a circuit is completely idle. Power dissipation of highperformance processors and servers is predicted to increase linearly over the next decade. The 2006 International Technology Roadmap for Semiconductors [7] projects power dissipation to reach 198 Watts in the year 2008 and reach 300 Watts by the year 2018. Multi-core integrated processors deliver significantly greater compute power through concurrency, offer greater system density and run at lower clock speeds, thereby reducing thermal dissipation and power consumption to an extent. Leakage power will contribute towards the majority of the total power consumption for such servers fabricated with deepsubmicron technologies. Figure 1 shows subthreshold leakage power trends [2] in accordance with Moore’s law. Clearly, with deep-submicron processes, chips will leak excessive amounts of power. By the year 2020, leakage is expected to increase 32 times per device [6]. This is a major challenge in scaling down designs, and it motivates the need for efficient leakage control mechanisms to minimize power overheads in circuits designed with deepsubmicron technologies.

Index Terms: Stand by Mode, Idle Mode, deep submicron

I. INTRODUCTION: There is a growing need for high-performance and lowpower systems, especially for portable and batterypowered applications. Battery-powered electronic systems form the backbone of the growing market of mobile handheld devices used all over the world today. In order to maximize battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (cell phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements [1]. With miniaturization and the growing trend towards wireless communication, power dissipation has become a very critical design metric. The longer the battery lasts, the better. Therefore current reduction is main concern for this type of applications. A number of such methods have been proposed to address this problem [2]–[3]. However, with continued process scaling, lower supply voltages necessitate reduction of threshold voltages to meet performance goals and result in a dramatic increase in subthreshold leakage current. Minimizing power consumption is currently an extremely challenging area of research, especially with on-chip devices doubling every two years [4] [5]. Design styles [5] play a key role in determining the power dissipation, performance and supply/threshold scalability of a circuit. Dynamic circuits 160 © 2010 ACEEE DOI: 02.AEE.2010.01.136

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

However, there is a delay penalty to be incurred as a result of stacking.The sleepy stack approach combines the sleep and stack approaches [10]. The sleepy stack technique divides existing transistors into two half size transistors like the stack approach. Then sleep transistors are added in parallel to one of the divided transistors. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while saving state. Each sleep transistor, placed in parallel to the one of the stacked transistors, reduces resistance of the path, so delay is decreased during active mode. However, area penalty is a significant matter for this approach since every transistor is replaced by three transistors and since additional wires are added for S and S’, which are sleep signals.

Figure 1: Projected Subthreshold Leakage ( Static ) Power (W)


In sleepy keeper approach[11], all that is needed addition of NMOS connected to VDD and the PMOS connected to GND to be able to maintain proper logic state in sleep transistor approach. Sleepy keeper approach increases dynamic power consumption over the sleepy stack approach. LECTOR is based on the observation made in [12], that “a state with more than one transistor OFF in a path from supply voltage to ground is far less leaky than a state with only one transistor OFF in any supply to ground path.” In this method, author introduces two leakage control transistors (LCTs) in each CMOS gate such that one of the LCTs is near its cutoff region of operation. LECTOR yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes.

Various researchers proposed a lot of interesting literature about techniques to minimize leakage power. Summarizing below are various methods presently used for leakage power control: Mutoh in [8] introduced the concept of Multi- Threshold CMOS (MTCMOS) which has emerged as a very popular technique for standby mode leakage power reduction. In this technique, a highthreshold voltage transistor is inserted in series with the power supply and the existing design and ground. During Active mode of operation, the high threshold Vth transistors are turned on, thereby facilitating normal operation of the circuit as there exists a direct path from the output to ground and Vdd. During Standby mode, these transistors are turned off creating a virtual power supply and ground rail and cutting off the circuit from supply. Since the high Vth transistors operating in standby mode forces the circuit to go to”sleep”, they are also known as sleep transistors.

The goal of our proposed new approach is to achieve the benefit of the sleepy transistor approach without making output float. Finally In this work, we develop a new technique for leakage control in CMOS circuits. The proposed technique avoids the problems associated with the techniques discussed above.

A variation of MTCMOS technique is the Dual technique, which uses transistors with two different threshold voltages. Low-threshold transistors are used for the gates on the critical path and high-threshold transistors are used for those not in the critical path [9]. In both MTCMOS and Dual methods, additional mask layers for each value of threshold voltage are required for fabricating the transistors selectively according to their assigned threshold voltage values. This makes the fabrication process complex.

IV. VSECUR BASED NOR GATE The basic idea behind our approach for reduction of leakage power in sleep transistor technique, which cutoff circuit form power supply VDD in sleep or idle mode. This is based on observation made [] that, if for a transistor source and drain potential are same then transistor is less leaky. In our method we introduce two high threshold (one PMOS and one NMOS) transistors. PMOS high threshold transistor Cutoff Vout node with power supply in sleep mode of operation and high threshold NMOS transistor gives non floating output in sleep mode.

In [9] , the authors show that “stacking” of two off devices significantly reduces subthreshold leakage compared to a single off device. These stacks are series-connected devices between supply and ground. (Eg : PMOS stack in NOR or NMOS stack in NAND gates). Stacking can also be achieved by forcing a non-stack transistor of width ‘W’ to a series-stack of two transistors, each of width ‘W/ 2 ’.

Figure 2 shown Two Input NOR gate implemented using VSECURE approach. where both dirk lined PMOS and 161

© 2010 ACEEE DOI: 02.AEE.2010.01.136

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

NMOS are representing high threshold transistors connect with Sleep Signal. Two series PMOS representing Pull Up Network and two parallel NMOS representing Pull Down Network of 2 Input NOR Gate. V1 and V2 are the intermediate node voltages.

because both PMOS is in ON state and if input vector 01, 10 or 11 is applied then both or one of the PMOS is in OFF state and voltage at node V2 is in mV range. Since sleep signal high is applied then for all input combination high threshold PMOS transistor operates in OFF state , which will cutoff node Vout from V2 hence leakage current flows through high threshold PMOS and its minimum. Due to high sleep signal, high threshold NMOS transistor is in ON state and provide always output Zero in sleep mode, hence output node is not floating.

Figure 2 : Two Input NOR using VSECURE technique

Active Mode : in this mode of operation Sleep signal low is applied to the circuit , hence PMOS sleep transistor is in ON state( figure 3 Shown in Green color) and sleep NMOS is in OFF state ( figure 3 shown in RED color). For input A and B four different combinations are possible (00, 01, 10 and 11). In active mode of operation circuit behave normally.

Figure 4 : Sleep mode of VSECURE NOR gate

V. EXPERIMENTAL METHODOLOGY AND RESULTS In order to compare the results of our new approach with prior leakage reduction approaches, namely, stack, sleep, sleepy stack, Sleep Keeper and LECTOR approaches. In addition, we consider a base case and the newly proposed VSECURE approach. Schematics are designed for all considered techniques using TANNER EDA tool and Netlists of test circuits for different techniques are extracted from the schematics. The netlists are modified to fit into all silicon technologies targeted using the PTM 90nm. We use TSPICE simulation to estimate delay and power consumption. The 1V supply voltage used for 90nm technology. Figures 5, 6 and 7 show the experimental results. Since the following several comparisons are focused on 90nm technology, Table 1 lists the numerical result values for 90nm technology, which are also shown in Figure 5, 6 and 7.

Figure 3: Active mode of VSECURE NOR gate.

Sleep mode : in this mode of operation Sleep signal high is applied , hence sleep PMOS is in OFF state (Figure 3 Shown in RED color) and Sleep NMOS is in ON State ( Figure 3 Shown in Green color) .Because Sleep POMS is in OFF state voltage at node V2 will depends on applied input vector, for input 00 node V2 voltage equals to Vdd 162 Š 2010 ACEEE DOI: 02.AEE.2010.01.136

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

for complex logic circuits, because the portion of increased area for the required additional transistors will be smaller for complex logic circuits than for simple logic circuits (e.g., for an inverter). For our future work, we plan to investigate contribution of gate leakage current in static power.

Avg Static Power Dissipation 8.00E-10 7.00E-10 6.00E-10 5.00E-10 4.00E-10 3.00E-10 2.00E-10 1.00E-10 S ta ck tra Tr an ns si is st to or r (D ua S le l ep V T S H ) ta ck S Tr le an ep si K s to ep r er (D ua lV TH )

References 1)

K. S. Yeo and K. Roy, Low-Voltage, Low-Power VLSI Subsystems. New York, USA: McGraw-Hill, 2005, p. 293. 2) V. De and S. Borkar, “Technology and design challenges for low power and high performance,” in Proc. Int. Symp. Low Power Electronics and Design, 1999, pp. 163–168. 3) K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley, 2000, ch. 5, pp. 214– 219. 4) Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998. 5) Piguet, C. Low-Power Electronics Design. CRC Press, 2005. 6) Roy, K., And Prasad, S. Low-Power CMOS VLSI Circuit Design. Wiley- Interscience, New York, USA, 2000, p. 376. 7) International Technology Roadmap for Semiconductors (ITRS-06). Design 2006Update.pdf. 8) S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu,and J. Yamada, “1-v power supply highspeed digital circuit technology with multithresholdvoltage cmos,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847–854, August 1995. 9) .Q. Wang and S. Vrudhula, “Static power optimization of deep sub-micron CMOS circuits for dual Vt technology,” in Proc. ICCAD, Apr.1998, pp. 490–496. 10) J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power,” Proceeding of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158, September 2004. 11) Se Hun Kim , Vincent J. Mooney III, "Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design" 12) Narender Hanchate,Nagarajan Ranganathan, "LECTOR: A Technique for Leakage eduction in CMOS Circuits" 2004 IEEE , Digital Object Identifier 10.1109/TVLSI.2003.821547


S le ep


S ta ck



as e

tra ns is to r

S le ep

B as e

C TO R V C E LA R IT R E (w V SE ith C hi U gh R E N M O S V TH )


Figure 5 : Static Power result (W) Dynamic Power Dissipation 3.50E-07 3.00E-07 2.50E-07 2.00E-07 1.50E-07 1.00E-07

V S E hi C gh U R N E M O S V TH (w ith


S ta ck S le ep


S ta ck Tr tra an ns si st is to or r (D ua S lV le ep TH ) S ta ck S Tr le an ep si K s to ep r er (D ua lV TH )

tra ns is to r

C as e B as e

S le ep


5.00E-08 0.00E+00

Figure 6 : Dynamic Power result (W) Propagation Delay 3.00E-11 2.50E-11 2.00E-11 1.50E-11 1.00E-11 5.00E-12

St ac k Sl ee p

LE C TO R VC VS E LA EC R U IT R E VS (w EC ith U hi R gh E N M O S V TH )

St ac k Tr tra an ns si is st to or r (D ua Sl lV ee p TH St ) ac k Sl Tr ee an p si Ke st o pe r r( D ua lV TH )

tra ns is to r

Ba se

Sl ee p

C as e


Figure 7 : Propagation Delay (Sec)

VI. CONCLUSION We have presented an efficient method for reducing leakage power in VLSI design as compared to established methods. The VSECURE technique results in ultra low static and dynamic power consumption without floating output state. Furthermore, the proposed methods is applicable to single and multiple threshold voltages. With application of dual Vth, VSECURE found to be more efficient approach to reduce leakage current with the negligible increase in delay while simultaneously providing non –floating output login in sleep mode In terms of area, the VSECURE approach is expected to be more attractive

163 © 2010 ACEEE DOI: 02.AEE.2010.01.136

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

Avg Static Power Dissipation

Dynamic Power Dissipation

Propagation Delay


PDP(Dynamic )

Base Case






Sleep transistor






Stack transistor






Sleep Stack Transistor (Dual VTH)






Sleep Stack Transistor






Sleep Keper (Dual VTH)
























VSECURE ( with high NMOS VTH)






Table 1 Static Power Dissipation, Dynamic Power Dissipation, Propagation, Power Delay product (Static & Dynamic) for 90nm.

164 Š 2010 ACEEE DOI: 02.AEE.2010.01.136