Page 1


APEX Center ­ Overview  Like the art of mountaineering, Semiconductor Technology is a very    

practically oriented science with very high peaks that few can scale Working professionals in industry are at different levels of height in terms of expertise High-end expertise is to be found only in very small pockets within the industry and academia across the globe Due to fast pace of innovation, Industry and Academia need to come closely together for pursuing Applied Research At BITS-RIT APEX Center, we will attempt to bring together top experts from industry and academia to help the working professionals attain global heights in professional excellence Applied research will be a key focus through close collaboration with industry and top academic institutions

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Goals

Applied Research Education

 PhD Program for working professional & full time students

 Short Courses to meet specific industry needs

 Projects sponsored by Indian & US semiconductor Industry

 Structural Master’s degree program

 Active research collaboration between RIT & BITS faculty  Exchange of researchers between RIT & BITS

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Program for Professional Excellence  A world-class education, training, and hands-on program offered in

   

Bangalore  To upgrade skills of VLSI professionals and managers to the world-class level  Offered by the best faculty members and industry professionals from India and across the world  OLAB extension will be set up at the center in Bangalore with state-of-the-art EDA tools  Offered to professionals from Center Affiliates companies The program will consist of multiple courses and access to OLAB Each course will be a complete unit in itself with appropriate credits awarded from BITS - Pilani Accumulation of enough credits and completion of a thesis will entitle for a master’s degree from BITS Will be taught by some of the best faculty and Industry professionals from India and abroad

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


BITS­RIT Collaboration  BITS will take ownership in setting up the center, the labs, the equipment       

and the management responsibilities for the center. All investments towards this will come from BITS BITS will also drive the Professional Excellence Program with involvement from faculty from RIT as well as from across the world Award of degrees / certificates for Professional Excellence programs will be managed by BITS RIT will play the lead role in Applied Research, particularly in the area of RF, Analog and Mixed Signal Design with involvement from BITS faculty and others in Industry Prof. P. R. Mukund, Director RAMLAB at RIT will be visiting Bangalore often to supervise the research programs. At least one or more research associates from RAMLAB of RIT will be located in Bangalore to carry on with the applied research work. PhD degrees may be awarded by RIT and BITS jointly or separately depending on the nature of association of the lead researchers BITS and RIT will jointly promote the center

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Course Structure  Each course will normally be about 20-30 people and will

have a tuition fee of about INR 10K – 30K per course per student (including access to OLAB as well)  These courses will be offered as 

intensive courses (10 to 30 hours of teaching over a period of one, two or three weeks), or over a semester

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Corporate Sponsors  Each interested company will become a Corporate Sponsor for the

Center with an annual fee of INR 75K – INR 200K based on their employee strength  Corporate Sponsors will also be able to provide input on courses offered and choice of faculty members  Corporate Sponsors will ensure that the Center remains world class and dynamic  Annual Corporate Sponsorship Fee  Employee Strength < 50 : INR 75K  Employee Strength 50-100 : INR 125K  Employee Strength > 100 : INR 200K

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Corporate Sponsorship Benefits  

 

Professionals from Sponsor Companies will be given preference in enrollment in these courses Representatives from sponsor Companies will be invited to be a member of the Technical Advisory Board to guide the Center to meet their specific needs and the needs of Indian Semiconductor Industry. Professionals from their companies would be able to enroll for an M. Eng. Degree from BITS and credit these courses towards their degree program. Resources of the center will be extended for research and development including supervision for Ph.D. programs. Corporate Sponsor will be able to directly benefit from this activity.

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Suggested List of Courses VLSI Technology and Systems Foundation Courses

Hours

Lab

Introduction to VLSI Technology

18

No

Fundamentals of ASIC design

30

Yes

Digital Design using Verilog

30

Yes

Design for Test

30

Yes

FPGA Design with Xilinx

30

Yes

Integrated Circuit Packaging

15

No

Principles of Logic Synthesis

30

Yes

Custom Layout of Integrated Circuits

30

Yes

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Suggested List of Courses â&#x20AC;Ś VLSI Technology and Systems Advanced Courses

Hours

Lab

Phase-Locked Loop Systems and Clock Gen Circuits

15

Yes

Signal Integrity Analysis for Integrated Circuit Interfacing

15

Yes

Advanced ASIC Physical Design

30

Yes

Advanced Static Timing Analysis

15

Yes

Circuit Modeling and Simulation

15

No

Advanced HDL Coding Techniques

15

Yes

RF Design

30

Yes

Low Power Design Techniques

15

No

Design of System Level Test Benches

15

Yes

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Suggested List of Courses â&#x20AC;Ś VLSI Technology and Systems Programming

Hours

Lab

30

Yes

Real-Time Programming and Embedded Systems Design

30

Yes

Embedded and Real-Time Linux

30

Yes

Practical Digital Signal Processing

30

Yes

Perl Scripting for Electronic Design Automation Embedded Systems, DSP and misc. hardware engineering

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Other Possible Courses …  In addition to the courses on VLSI, the scope

may be expanded to offer additional practice oriented courses relevant for Industry  Few Practitioner’s Courses identified    

Software Testing Technical Writing Embedded SW development Bio-Technology

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Value Proposition for Professionals  Never before opportunity to enrich knowledge and    

expertise where it matters Learn from best in class experts from all over the world, right here Opportunity for people not having a Masters degree to earn one through part-time route Opportunity for pursuing research through PhD enrollments, while working A stronger alternative to distance learning options available from US based universities

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Value Proposition for Industry  Move up the value chain through skills and

expertise gained  Possible avenue for better employee retention  Compelling cost structure to try new ideas  Excellent design infrastructure  Instant access to university expertise on fundamental knowledge

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Value Proposition for Faculty  Chance to contribute to India’s success –

especially for NRI industry professionals & professors coming from overseas  Chance for strategic relationship with Indian University system  Joint research programs with BITS and working professionals from industry in India  Better understanding of the emerging markets  Opportunity for fulfilling the passion for teaching  World class remuneration Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


Value Proposition for Academia  Through continuous interaction and help from the top experts

participating in BITS-RIT APEX programs, academic curriculums at the University will be constantly enhanced to keep pace with the latest  Some of the courses offered at BITS-RIT APEX center will be beamed remotely to the university campuses through video conferencing with an option for the students at the campus to enroll against credits. BITS may consider extending such facilities to other interested universities as well at a future date  Plan to fund fundamental and applied research at the university with the resources generated at the BITS-RIT APEX center  Chance to contribute to growth of India’s semiconductor industry by facilitating high end talent generation and applied research programs Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB


BITS - Pilani

   OLAB (Oysters Lab)  VLSI DESIGN LABORATORY Integrated efforts of BITS, BITS Alumni and Industry Professionals

Birla Institute of Technology & Science Pilani, Rajasthan


OLAB at BITS, Pilani

RAMLAB


OLAB - Industry Sponsors

Open Silicon

Mentor Graphics CADENCE SUN Microsystems

WIPRO


OLAB FACILITIES


 A powerful centralized compute server

farm for EDA tools in Layer 1 Sun Fire v250, NAS 3300 & SDLT320  Sun Ray software  EDA tools & user files  Automatic tape back-up


 Number of powerful SUNSPARC workstations

as compute servers in layer 2 : • 20 Ultra 2 Enterprise server-class workstations • Computing share through Sun Grid Engine  40 SUN THIN Clients as nodes in layer 3.  Connected with 1.0 Gbps network connectivity


 Tool Suite from MAGMA

(About 15 sets of licenses of back-end design tools for mixed signal and a complete package for RTL to GDS flow)  Tool Suite From CADENCE  Foundry access for fabrication of parts  FPGA design infrastructure for prototyping


OLAB ACTIVITIES •   Students of M.E. Microelectronics for conducting      laboratory sessions •   Students of First Degree Programme for courses        in the area of  VLSI Design •  To Facilitate Research activities •  To conduct short term courses for Industry       Professionals •  To support entrepreneurs in Technology        Development •  To undertake Industry Sponsored Projects


A Sample list Dissertation projects ­Design of CISC Microprocessor ( M68010 compatible) ­Design of Application Specific Instruction set Processor  for text to speech conversion ­Design of A/D and D/A converters ­Design of switched capacitor circuits ­Design of a CAD tool for synthesis of OPAMPs


Currently a Project on ZigBee enabled wireless sensor network is taken up with joint efforts of faculty, students and BITS Alumni.


Master/Controller module

Sensor/Slave module Processor

Host I/F

Processor & Peripherals

Analog interface Circuits (ADC/DAC)

RF Circuitry (Wireless transceivers)

RF Circuitry (Wireless transceivers)

Sensors interface Circuits

Processors and wireless transceivers are the same for both the master and slave modules.

Sensor/Slave module Processor RF Circuitry (Wireless transceivers)

Sensors interface Circuits

WIRELESS MESHED SENSOR NETWORK ARCHITECTURE


OLAB will support a full chip design capability at BITS through state-of-the-art EDA tools


RF/Analog/Mixed Signal Lab (RAMLAB)

RF/Analog/Mixed signal Laboratory (RAMLAB)  Dept. of Electrical Engineering Building 9, 3rd Floor, Room 3271 Rochester Institute of Technology Rochester, NY 14623


RAMLAB ­ Overview Semiconductor Research Corporation RAMLAB specializes in developing cutting edge design  solutions for RF, analog and mixed signal circuits  People:

Technology Used:

Research Faculty Graduate Students

0.25 um TSMC CMOS 0.25 um IBM CMOS

Distinguished Researcher

National Science Foundation Harris Corporation

Equipment: Unix Workstations with Cadence Suite ATE with probe station, spectrum  analyzer & Network Analyzer for RF  Characterization Industry Liaisons Ph.D. Students Anand Gopalan Sripriya Bandi Tejasvi Das

Intel Corporation

Sharmila Sridharan Mark Pude Jeff Lillie

Eastman Kodak Company Kawasaki LSI LSI Logic

RAMLAB


RAMLAB ­ Current Projects  Chip­Package Co­Design Of RF­Mixed signal 

Microsystems

 Built in Self Test Strategies for RF/Mixed Signal Systems

 High­speed circuit design and Characterization

 Mixed­Signal IC Design beyond 10 GHz

RAMLAB


Collaboration with Harris Corporation

Work with Harris Corporation VDD

Tunable Wideband LNA Design

R1 LD M3 R2 LG

M2 M1 LS

LNA Schematic

RF Front end circuitry is designed to be either only  narrowband or wideband. For military applications wherein frequency hopping is  popular for secure communications, the above  mentioned circuitry is not suitable. Objective: design tunable RF LNA with very wide  frequency range and very fine selectivity Simulation Results

Simulation results summary

Noise Figure v/s frequency LNA was fabricated on a 10mm^2 Chip  using IBM’s 0.25um CMOS RF 6­metal  layer process

Input return loss S11 v/s frequency

RAMLAB


Chip­Package Co­Design

Chip-Package Co-Design of RF Microsystems Research Objectives “To analyze different functional blocks in a RF microsystem, in the 2-5GHz range for Chip-Package Co-Design, and develop a software package that performs early analysis of various functional blocks”

 Convert intricate analysis into a set of simple design rules that can be used by the designer  Make trade-off analysis simpler  Make intricate problems opaque to the designer  First Time Right  Lower time to market

Accomplishments Circuit Components Designed and  Fabricated using IBM’s 0.25um CMOS • Low Noise Amplifier   • Single Balanced Mixer • Low Phase Noise VCO

Integrated Passive Design

Early Design Software Developed for Chip­ Package Co­Design – ‘DREAM’

• Embedded Inductor on Si Substrates

• Suited for ‘Early Design’

• Developed Inductor Library for Embedded Process

• Applications are diverse including RF,  Mixed Signal, Digital and Power  Distribution

Development of Design Rules& Methodologies • Design constraints of ESD protection circuitry • Vertically Integrated Designs Developed

G. Nayak, P.R. Mukund, “Chip-Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using embedded passives in a silicon package”, 17th International Conference on VLSI Design and 3rd International Conference on Embedded Systems, Mumbai, India, January 2004

RAMLAB


DREAM: Digital-RF Early Analysis Methodology Digital Pin  Placement Mixed Signal Analysis

A/D and  Op­Amp Analysis

Design MRF ethodologies Modules

Passive Characterization

Horizontal Floor Planning

Digital Modules

RF Design Digital Logic Vertical MEMS Integration Quality Factor

Novel Design Techniques

RF

Inductor Library 40

Phase Noise Analysis for VCO &  Sideband Analysis for Mixer

L1 off chip L2 off chip L1 on chip L2 on chip

35 30

Power Distribution

25 20 15 10 5 Frequency(GHz) 0 0

2

4

6

Inductor Libraries for RF Design

2D and 3D Analysis for  Power Distribution Analysis

Early Design Software – ‘DREAM ’

8

Inductor Modeling  and Characterization Vertically Integrated Designs (Si on Si)

RAMLAB


Application Specific Reduced Order Modeling Technique Change in S11 due to package

Pin Functionality, RF Circuit

Package RLC Models

Proposed SiP Design Methodology

Krylov’s Sub Space Models

Application Specific Reduced Order Models

S-parameters comparison with and without package parasitics

RFIC Design Model Reduction for power pin

Equivalent circuit model for ground pin

Lw

Original curve Order: 27

Model Reduction for signal pin S11

Order = 5 Original curve Order = 27

Rg Lg

SiP Design Methodology

Order: 7

Cg

Order = 6

Order: 6 Order: 5

G. Nayak, C. Washburn, P.R. Mukund, “System in a Package Design of a RF Front End System using Application Specific Reduced Order Models ”,Accepted at the 18th International Conference on VLSI Design and 4th International Conference on Embedded Systems, Calcutta, India, January 2005

RAMLAB


Built-In-Self Test (BiST) for RF systems Semiconductor Research Corporation

RAMLAB


Motivation – RF Testing Challenges  Probes

Si Die RF Design

Very act of probing can affect  circuit performance Access to RF core difficult RF Testing Passives

Factors affecting RF Circuit reliability  Process Variations  Tolerances of Package Parasitics  Quality of Passives: soft  faults

CHI P Bond Wire

CHIPCARRIER

RAMLAB


Current sensor for GHz applications Requirements of a sensor •High Bandwidth •Low Sensitivity to process variations •High Dynamic Range •High Sensitivity

Stage 1: Sensing Resistor (Rs) + Source Follower Stage 2: Inverting Amplifier Stage 3: Current Amplifying Cell

DESIGN FEATURES •Sensing Resistor – 7 Ω •Feedback structure •Reduction in number of Gain •Addition of bypass capacitor

RAMLAB

Stages


BiST for LNA, Mixer, VCO

0.15

1.35

0.14

1.34

0.13

1.33

BiST output

1.9GHz LNA and BIST circuit fabricated in IBM  0.25 micron

BiST Output

 Low real estate and power overheads!!  Similar techniques can be used to  quantify   Output Match (S22), Gain (S21), and  Linearity (1dB compression) of LNA  Entire self­test can be carried out in less  than 20μs.

0.12 0.11 0.1 0.09

1.32 1.31 1.3 1.29

0.08

1.28

1.775

1.975

2.16

-22

-16 S11 magnitude

S11 frequency

RAMLAB

-13


Self­Calibrating RF circuits Inability to probe RFICs directly

1

2

Limitations of existing RFIC testing

Probes

Si Die RF Design

3

010010101000 010101001000 111001000011 000010101000 010101011111

RF Testing

High Cost $$

Limitations of Co­Design

 Wide tolerance ranges of package parasitics 

Time Intensive

Use of DSPs

Can detect but not correct faults

 Dependence of E.S.D. protection on                             

                                      

   environmental conditions   Package portability   Design time and cost

Hence, a circuit topology that dynamically self­corrects its performance in the presence of process faults  and package parasitics is desired!

RAMLAB


Self­Calibration: Methodology Sense Amplifier

Start with nominal  RF ckt

Sense current with  minimally intrusive  element

Peak Detector

Amplify sensed  current

Down­convert signal  to baseband

Map signal to  performance metric

RF CIRCUIT Dynamically modify  design parameters in RF  circuit

Generate baseband/digital  signal to modify design  parameters

NO

Baseband Signal  Processing

Figure 3.  Proposed  Methodology  for  self­correction  of  input match.

Performance metric ok?

YES 3 End Calibration  process

 Self­correction on­the­fly

 Robust ­> Two­tonal approach

 Non­intrusive current sensing

 Cuts down design cycle cost and time

 Baseband processing

 Low overheads 

RAMLAB


Self­Calibration: Results S11 curves before and after  calibration.  (a)

when a parasitic  inductance of 1nH is  added. 

(b) when CGS of the  LNA transistor is  reduced by 10%. S11 curves before and after calibration for the weakest  corner: Ideal S11=1.824 GHz Parasitic inductance shifted it to 1.728 GHz  After calibration the input match aligned itself at 1.817  GHz

RAMLAB


LSI Logic: High­speed circuit design and  Characterization

 Collaborative effort with LSI for device characterization in high-speed circuits.  Current empirical models require that every device size used in design has to be fabricated and the data curve-fitted.  Model scalability with respect to both device size and technology is required.  0.18um, 0.13um, 90nm & 65nm foundry and data access from LSI

RAMLAB


Kawasaki: Mixed­Signal IC Design beyond 10  GHz  3­year project begins May 2005  

 Switching noise dependencies on logic activity and packaging  High speed clock distribution in a large chip  Simultaneous switching outputs and containment strategies  Analog and digital isolation in a SoC design   Circuit techniques to monitor core noise 

RAMLAB


Thank You

Birla Institute of Technology & Science Pilani, Rajasthan

RAMLAB

Bits  

Bits bla bla bla

Read more
Read more
Similar to
Popular now
Just for you