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HCTL Open International Journal of Technology Innovations and Research (IJTIR) is an international, open-access, peer-reviewed journal devoted to various disciplines of Science and Technology published (bi-monthly) by HCTL Open Publishing, India. Published by:

HCTL Open International Journal of Technology Innovations and Research (IJTIR) Volume 1, January 2013

HCTL Open Publishing, India. C/O Raj Gaurav Mishra (Managing Editor), B-144, Palace Orchard, Phase IV, Kolar Road, Bhopal – 462042, MP INDIA Web: http://www.hctl.org/IJTIR.html Email: editor_ijtir@hctl.org Phone: +91 810 955 9626

Edited by: Raj Gaurav Mishra For HCTL Open Publishing


HCTL Open International Journal of Technology Innovations and Research (IJTIR) An International, Open-Access, Peer-Reviewed, Online Journal Devoted to Various Disciplines of Science and Technology. Volume 1, January 2013

Edited by Raj Gaurav Mishra Editor-in-chief for HCTL Open International Journal of Technology Innovations and Research (IJTIR)

31 January 2013

HCTL Open Publishing


Volume 1 January 2013 HCTL Open International Journal of Technology Innovations and Research (IJTIR) e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Raj Gaurav Mishra

Publisher:


HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Title Information HCTL Open International Journal of Technology Innovations and Research (IJTIR) Volume 1, January 2013 Date of Online Publishing: 31-January-2013

Copyright Information c HCTL Open Publishing, India. This volume is an open-access document, distributed under the terms and conditions of the Creative Commons Attribution 3.0 Unported License (http://creativecommons.org/licenses/by/3.0/).

Publisher Published by: HCTL Open Publishing, Bhopal, MP, India Email: director@hctl.org Website: http://www.hctl.org/IJTIR.html

Bibliographic Information ISSN (Online): 2321-1814 ISBN-13 (Print): 978-1-62776-012-6 ISBN-10 (Print): 1-62776-012-6 e-Version (Online) available at: www.hctl.org/ijtir/vol1/Volume1_January2013.pdf

Important Links HCTL Open Digital Library / Archives: http://elibrary.hctl.org Running Call for Papers: http://cfp.hctl.org Author’s Guidelines & Publication Process: http://www.hctl.org/authors_guidelines_IJTIR.html Online Manuscript Submission System: http://www.hctl.org/submit_manuscript_IJTIR.html Other Information: http://www.hctl.org/IJTIR.html

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

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HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Editorial Board Members Publication Heads Nirmala Mishra Hybrid Computing Technology Labs, India Raj Gaurav Mishra Hybrid Computing Technology Labs, India

Editor-in-Chief Raj Gaurav Mishra Hybrid Computing Technology Labs, India

Associate Editors Charu Agrawal Assistant Prof., Galgotia University, Greator Noida, India Manish Kumar Jaiswal Researcher, City University of Hongkong, Hongkong Sanchita Sengupta Researcher, Delft Institute of Technology, Delft, Netherlands Surajit Paul Researcher, IUCAA, University of Pune, Pune, MH, India Abhay Vidhyarthi Assistant Prof., ITM-University, Gwalior, MP, India Amit Shrivastava Assistant Prof., NRI-ITM, Gwalior, MP, India Anand Srivastava Researcher, Indian Institute of Technology - Mandi, HP, India Devendra Bhavsar Assistant Prof., J.K. Lakshmipath University, Jaipur, Rajasthan, India Gajendra Sharma Researcher, Indian Institute of Information Technology Allahabad, UP, India Gaurav Mishra Assistant Prof., SRMS, Bareily, UP, India Ismathullakhan Shafiq Researcher, City University of Hongkong, Hongkong Jayant Supale Assistant Prof., SKN SITS, Mumbai-Pune Express Highway, Lonavala, MH, India Krishnakant Agrawal Researcher, Indian Institute of Information Technology Allahabad, UP, India Manisha Rajpoot Reader, Rungta College of Engineering & Technology, Bhillai, CG, India

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

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HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Pawan Mishra Researcher, King Abdulla University of Science & Technology, Saudi Arabia Pawan Verma Researcher, Motilal Nehru National Institute of Technology Allahabad, UP, India Preetam Suman Researcher, Indian Institute of Information Technology Allahabad, UP, India Ravi Bhramaramba Associate Prof., GITAM Institute of Technology, GITAM UNIVERSITY, AP, India Ravindra Meena Assistant Prof., J.K. Lakshmipath University, Jaipur, Rajasthan, India Richa Chauhan Researcher, Hybrid Computing Technology Labs, India Sandeep Bhaskar Assistant Prof., Echelon Institute of Technology, Faridabad, UP, India Shaishav Agrawal Researcher, Indian Institute of Information Technology Allahabad, UP, India Shubhi Shrivastava Researcher, Hybrid Computing Technology Labs, India Vimal Upadhyay Researcher, Indian Institute of Information Technology Allahabad, UP, India Vipin Patait Assistant Prof., ICFAI University, Faculty of Science & Technology, Dehradun, UK, India Vishal Srivastava Assistant Prof., Selaqui Institute of Engineering & Technology, Dehradun, UK, India Zahid Ullah Researcher, City University of Hongkong, Hongkong

Technical Advisors Sr.

Sr.

Amit Bhargawa Consultant (IT & Networking), HCL Technologies, Noida, UP, India Ankit Sharma Consultant (IT & Networking), HCL Technologies, Noida, UP, India Arpit Seth Sr. Consultant, Capgemini, Mumbai, MH, India

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

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HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Chandra Shekhar Bhadauria Consultant (IT Services), Impetus Technologies, Inc., Indore, MP, India Naval Garg Sr. Consultant (IT Services), Tata Consultancy Services, USA Rahul Shrivastava Sr. Consultant (Marketing and Sales), Hybrid Computing Technology Labs, India Ritika Chauhan Sr. Consultant (IT & Marketing), Hybrid Computing Technology Labs, India Rohit Tripathi Sr. Consultant (Technical), Subros - India, Greater Noida, India Rudransh Sharma Sr. Consultant (IT Services), Tata Consultancy Services, Mumbai, MH, India Sagar Ambastha Sr. Consultant (IT Services), Amdocs, Pune, MH, India Vinod Kumar Singh Sr. Consultant (Technical), Reliance Industries Ltd., Mumbai, MH, India Sr.

Authors/Contributors - Volume 1 (January 2013) Raj Gaurav Mishra Hybrid Computing Technology Labs, India Amit Shrivastava Assistant Prof., NRI-ITM, Gwalior, MP, India Preetam Suman Researcher, Indian Institute of Information Technology Allahabad, UP, India Amrit Suman Assistant Prof., Laxmi Narayan College of Technology, Bhopal, MP, India Vimal Upadhyay Researcher, Indian Institute of Information Technology Allahabad, UP, India Krishnakant Agrawal Researcher, Indian Institute of Information Technology Allahabad, UP, India Mukesh Chand M.D.U. Rohtak, Haryana, India Devesh Mishra M.Tech. Student, Indian Institute of Information Technology Allahabad, UP, India

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

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HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Editorial and Forewords We are very happy to publish the first volume of HCTL Open International Journal of Technology Innovations and Research (IJTIR). HCTL Open International Journal of Technology Innovations and Research (IJTIR) is an international, open-access, peer-reviewed journal devoted to various disciplines of Science and Technology published by HCTL Open Publishing, India. This issue contains three research articles. Achieving such a high quality of papers would have never been possible without the huge work that was undertaken by the Journal’s Production and Promotion Team, Editorial Board Members, Technical Advisory Committee Members and External Reviewers. The first research article Implementation of Custom Precision Floating Point Arithmetic on FPGAs have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. In the second research article An Enhanced TCP Corruption Control Mechanism For Wireless Network, an improved mechanism for Transmission Control Protocol (TCP) corruption control and the comparative study of Enhanced TCP (ETCP) with other TCP variants is presented on various parameters like mobility, size of network and the speed. In the third research article Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant, a method of NDT (Non Destructive Testing) for measurement of flow accelerated corrosion or thickness degradation in the pipelines used in oil and nuclear plants by using ultrasonic sensors is presented. We take this opportunity to thank everyone (including Authors of this volume) for their great support and cooperation and we wish for their similar kind of support in future. Raj Gaurav Mishra, Founder and Managing Director for HCTL Open Publishing, India Editor of Volume 1, January 2013 - HCTL Open IJTIR

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

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HCTL Open Int. J. of Technology Innovations and Research (IJTIR) Volume 1, January 2013

Contents S. No.

Title of the Research Article

Page No.

1.

Cover Pages

2.

Bibliographic Information

4

3.

Editorial Board Members

5-7

4.

Editorial and Forewords

8

5.

Implementation of Custom Precision Floating Point Arithmetic on FPGAs.

10 - 26

6.

An Enhanced TCP Corruption Control Mechanism For Wireless Network.

27 - 40

7.

Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant.

41 - 49

HCTL Open Digital Library & Archives Volume 1: e-ISSN: 2321-1814, ISBN (Print): 978-1-62776-012-6

1-3

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Implementation of Custom Precision Floating Point Arithmetic on FPGAs Raj Gaurav Mishra and Amit Kumar Shrivastava rajgmishra@hctl.org and amitshrivastava@hctl.org

Abstract loating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in calculations and their hardware utilization for such calculations. In this paper, we have described and evaluated the performance of custom-precision, pipelined, floating point arithmetic core for the conversion to and from signed binary numbers. Then, we have assessed the practical implications of using these algorithms on the Xilinx Spartan 3E FPGA boards.

F

Raj Gaurav Mishra and Amit Kumar Shrivastava Page 10 Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Keywords Field Programmable Gate Array (FPGA), floating point arithmetic, customprecision floating point, floating point conversion.

Introduction With the advent of sensor technology, it is now possible to measure and monitor a large number of parameters and to carefully use them in a number of fields such as medical, defence, commercial etc. for various applications. Real-time implementation of sensor based application requires a system which can read, store and process the sensor data using micro-controllers or FPGAs as processors. Figure 1 shown below, represents a real-time data acquisition system based on a FPGA processor. Such a system comprises of a single or multiple sensors, signal conditioning unit (filters and amplifiers) and analog to digital converters. The output of the analog to digital converter is generally connected to the input of the processor (FPGA device in our case) for further signal acquisition and processing.

Figure 1: Block diagram of a FPGA processor based real-time sensor data acquisition system.

It is important for FPGA processor to store the real time sensor values to an external memory device for signal processing using custom algorithms. For example, analysing sound/speech in real time requires recording of sound signals using a microphone (sensor) using a high speed FPGA processor and then storing the resultant sensor values into a floating point format to maintain a specific accuracy and resolution. Floating point number system in comparison with binary number system have a better dynamic range and are better in

Page 11 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 handling underflow and overflow situations during mathematical calculations (signal processing). In this way, when a sensor value is stored in floating point format provides a base for accurate signal processing. In this paper, a pipelined implementation and hardware verification of custom precision floating point arithmetic on FPGA have been reported and discussed. Here, we assume that the reader is familiar with FPGA [1], its programming using Verilog HDL [2]-[3] and the single precision, double precision floating point standards [4] defined by IEEE. Comparatively, floating point number systems have a better dynamic range than a fixed point number system; also they are better in handling underflow and overflow situations during mathematical calculations however the speed and complexity issues rises when an implementation on FPGA processors comes into consideration. Research has been done to experiment various optimized implementations of IEEE single precision [7]-[10] and double precision [11]-[15] floating point arithmetic on FPGA. Algorithms for floating point implementation are complex in nature and with the number of bits used in single or double precision made them utilize a large area of the FPGA chip with a considerable processing time. Need of a custom precision floating point system arises when a real-time image or digital signal processing applications are to be implemented on an FPGA processor, where a requirement of high throughput in calculation and a balanced timearea-power implementation of the algorithm becomes an important requirement. In this way, an embedded designer can choose a suitable custom floating-point format depending upon the available FPGA space for the required embedded application. Table 1 shows the basic comparison between the 17-bits custom precision, IEEE standards of single, double and quadruple precision floating point numbers. This paper is organized as section 2 presents the custom precision floating point format in details. In section 3, we have described the algorithm and flowchart for the conversion of 12 bit signed binary number to 17 bits custom precision floating point number, the algorithm and flowchart for the conversion of 17 bits custom precision floating point number to a 12 bit signed binary number, along with their simulation results, synthesis summary and hardware verifications. Section 4 concludes this paper with the scope of future work which can be extended in various ways.

Page 12 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Table 1: Different floating point formats.

Custom Preci- Single sion sion Word Length Mantissa Exponent Sign Bias Range

Preci- Double Preci- Quadruple Presion cision

17 bits

32 bits

64 bits

128 bits

10 bits 6 bits 1 bit 26−1 -1=31 About 4.3x109 =(232 )

23 bits 8 bits 1 bit 28−1 -1=127 About 3.5x1038 =(2128 )

52 bits 112 bits 11 bits 15 bits 1 bit 1 bit 11−1 2 -1=1023 215−1 -1=16383 About About 308 1024 1.8x10 =(2 )1.2x104932 =(216384 )

Custom Precision Floating Point Format Floating-point systems were developed to provide high resolution over a large dynamic range. Floating-point systems can often provide a solution when fixed-point systems, with their limited dynamic range, fail. Floating-point systems, however, bring a speed and complexity penalty. Most microprocessor floating-point systems comply with the published single- or double-precision IEEE floating-point standard; while in FPGA-based systems often employ custom formats. A standard floating-point word consists of a sign-bit S, exponent E, and an unsigned (fractional) normalized mantissa M, arranged as shown in the figure 2.

Figure 2: 17 bits Custom Precision Floating Point format.

The minimum number custom precision floating point number (1,6,10) format can represent is:

Page 13 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 (±0.0000000004656612873077392578125)10 or (±0.0000000000000000000000000000001)2 . Minimum number representation in custom precision floating point format is (00000000000000000)1,6,10 for a positive number and (10000000000000000)1,6,10 for a negative number. The maximum number custom precision floating point number (1,6,10) format can represent is: (±4, 29, 49, 67, 296.00)10 or (±100000000000000000000000000000000)2 . Maximum number representation in custom precision floating point format is (01111110000000000)1,6,10 for a positive number and (11111110000000000)1,6,10 for a negative number.

Figure 3: Method of converting a fixed point decimal number in to a custom precision floating point number (1,6,10) format [5]-[6].

Raj Gaurav Mishra and Amit Kumar Shrivastava Page 14 Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Table 2: Some Examples values of 17-bit Custom Precision Floating-Point Format.

S.No.

17-bit custom precision floating-point format (1,6,10)

Equivalent decimal values

1 2 3 4 5

0 000000 0000000000 1 000000 0000000000 0 011111 0000000000 1 011111 0000000000 0 111111 0000000000

6

1 111111 0000000000

Represents a minimum number (+0) Represents a minimum number (−0) +1.0 −1.0 Represents a maximum number (+∞) Represents a maximum number (−∞)

Floating Point Operations on FPGA Signed Binary to Custom Precision Floating Point Conversion Considering the system defined in the figure 1, an embedded designer can choose 8-bit, 12-bit or 16-bit analog to digital converters to adjust the required resolution of the sensor value for an application. Texas Instruments ADS7828 [16] or any other similar 12-bit ADC is more suitable for the algorithm developed and presented in the following section. Algorithm 1 describes the step-wise approach of programming an FPGA for the conversion of a 12-bit signed binary number in to a 17-bit custom-precision floating point number. The flow diagram of the algorithm 1 is shown in the figure 4. Table 3 shows the synthesis summary of hardware utilization and speed for the algorithm 1 on different FPGA processors. Figure 5 shows the simulation results for the algorithm 1 implemented using verilog HDL on Xilinx ISE Project Navigator Ver. 13.4 and ISE Simulator [17].

Custom Precision Floating Point to Signed Binary Conversion Algorithm 2 defines the step-wise approach of programming an FPGA for the conversion of a 17-bit custom-precision floating point number in to a 12-bit signed binary number. The flow diagram of the algorithm 2 is shown in the

Page 15 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Algorithm 1 Converting a Signed Binary number (12 bits) in to a CustomPrecision (17 bits) Floating Point number (1,6,10) format. Require: 12 bits signed binary number as input. Ensure: 17 bit custom-precision floating point number (1,6,10) format as output. 1: Store the value of input to a temporary register R1 (size 12 bits). 2: Check for the sign-bit: 3: if Sign-bit is equal to 1 (Input is a negative number): then Take 2’s complement of the values stored in R1 register (input value) and store the results to a temporary register R2 (size 12 bits). 4: else if Sign-bit is equal to 0 (Input is a positive number): then Store the value of temporary register R1 to temporary register R2 without any modifications. 5: end if 6: Scan all the bit values of register R2 starting from (MSB − 1) towards LSB and search for first HIGH (1) bit value. 7: Count of the total bits towards right side (towards LSB) from the first HIGH (1) bit found, and store this count to a temporary register R3 (size 4 bits). 8: Store all the bits towards right side (towards LSB) from the first HIGH (1) bit found, to a temporary register R4 (size 10 bits). 9: Calculate the addition of the count stored in temporary register R3 with the value of fixed bias* and store the results to a temporary register R5 (size 6 bits). This forms the exponent value. Calculation of Fixed Bias* = 2E−1 − 1 = 26−1 − 1 = 3110 or 0111112 . (E is the number of bits allocated for exponent in the floating point format). 10: Normalize the value of register R4 (bit shifting towards MSB to fit the values completely in 10 bits format). Store the resultant value to a temporary register R6. This forms the mantissa value. 11: Store the sign bit from the input value (as stored in register R1), value of register R5 (exponent) and value of register R6 (mantissa) in a 17 bits custom (1,6,10) format to a temporary register R7 (size 17 bits). 12: Connect the temporary register R7 to the output. 13: 17 Bit custom-precision floating point number (1,6,10) format.

Page 16 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Table 3: Synthesis Summary for 12 bit Signed Binary Number to 17 bit Custom Precision Floating Point Conversion.

FPGA Pro- Speed cessor Grade

Number of Slices Used

Number of Slice Flip Flops Used

Number of 4 input LUTs Used

Number of bonded IOBs Used

Maximum Frequency

Spartan 3E -5 XC3S500E

71 out of 4656

70 out of 9312

134 out of 9312

30 out of 232

174.304 MHz

Spartan 3E -5 XC3S1200E

71 out of 8672

70 out of 17344

134 out of 17344

30 out of 250

174.304 MHz

Spartan 6 -3 XC6SLX25

77 out of 30064

138 out of 15032

162 out of 486

30 out of 226

212.770 MHz

Virtex 4 -12 XC4VFX100

83 out of 42176

70 out of 84352

157 out of 84352

30 out of 576

338.324 MHz

Virtex 5 -3 XC5VFX100T

70 out of 64000

94 out of 64000

113 out of 339

30 out of 680

394.120 MHz

Virtex 6 -2 XC6VCX130T

69 out of 160000

120 out of 80000

136 out of 408

30 out of 240

433.529 MHz

figure 8. Table 4 shows the synthesis summary of hardware utilization and speed for the algorithm 2 on different FPGA processors. Figure 6 shows the simulation results for the algorithm 2 implemented using verilog HDL on Xilinx ISE Project Navigator Ver. 13.4 and ISE Simulator [17]. Algorithms 1 and 2 have been tested and verified on Digilent NEXYS 2 FPGA board [18] containing Spartan 3E [19] XC3S1200E FPGA processor as shown in figure 7. To verify the correctness of the algorithm different inputs were given through different combinations of on-board switches and output was received through the LEDs connected to the I/O pins of the FPGA processor.

Page 17 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 Algorithm 2 Converting a Custom-Precision (17 bits) Floating Point number (1,6,10) format in to a Signed Binary number (12 bits). Require: 17 bit custom-precision floating point number (1,6,10) format as input. Ensure: 12 bits signed binary number as output. 1: Store the MSB value of input to a temporary register R1 (size 1 bit). This is for the purpose of defining sign bit. 2: Store the 10 bits from the LSB towards MSB to a temporary register R2 (size 11 bits). This is to be used as mantissa for further calculations. 3: Assign the MSB bit of temporary register R2 as HIGH (1) to incorporate the hidden 1 bit. 4: Store the remaining 6 bits from the input to a temporary register R3 (size 6 bits). This is to be used as exponent for further calculations. 5: Calculation of exponent value (in order to normalize the mantissa): Values stored in register R3− Bias* = Value of exponent by which mantissa is to be normalized. Store this value to a temporary register R4 (size 8 bits). Calculation of Fixed Bias* = 2E−1 − 1 = 26−1 − 1 = 3110 or 0111112 . (E is the number of bits allocated for exponent in the floating point format). 6: Normalization of mantissa value to fit in 11 bits: 7: if the value stored in register R3 (exponent value) is equals to 0 (zero). then the value of mantissa will become 0 (zero). 8: end if 9: if the value stored in register R4 (exponent count) is equals to 0. then the value of mantissa is to be bit-shifted 10 times towards left (MSB) for normalization. 10: end if 11: if the value stored in register R4 (exponent value) is equals to 1. then the value of mantissa is to be bit-shifted 9 times towards left (MSB) for normalization. 12: end if 13: if the value stored in register R4 (exponent value) is equals to 2. then the value of mantissa is to be bit-shifted 8 times towards left (MSB) for normalization. 14: end if 15: if the value stored in register R4 (exponent count) is equals to 3. then the value of mantissa is to be bit-shifted 7 times towards left (MSB) for normalization. 16: end if 17: if the value stored in register R4 (exponent value) is equals to 4. then the value of mantissa is to be bit-shifted 6 times towards left (MSB) for normalization. 18: end if Page 18 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

19:

20: 21:

22: 23:

24: 25:

26: 27:

28: 29: 30: 31:

32:

33: 34: 35:

if the value stored in register R4 (exponent value) is equals to 5. then the value of mantissa is to be bit-shifted 5 times towards left (MSB) for normalization. end if if the value stored in register R4 (exponent value) is equals to 6. then the value of mantissa is to be bit-shifted 4 times towards left (MSB) for normalization. end if if the value stored in register R4 (exponent value) is equals to 7. then the value of mantissa is to be bit-shifted 3 times towards left (MSB) for normalization. end if if the value stored in register R4 (exponent value) is equals to 8. then the value of mantissa is to be bit-shifted 2 times towards left (MSB) for normalization. end if if the value stored in register R4 (exponent value) is equals to 9. then the value of mantissa is to be bit-shifted 1 time towards left (MSB) for normalization. end if Store the resultant value of mantissa after suitable bit-shifting (normalization) to a temporary register R5 (size 11 bits). Check for the sign-bit stored in the register R1: if Sign-bit is equal to 1 (Input is a negative number): then Take 2’s complement of the values stored in R5 register (normalized value of mantissa) and store the results to a temporary register R6 (size 12 bits). else if Sign-bit is equal to 0 (Input is a positive number): then Store the value of temporary register R5 to temporary register R6 without any modifications. end if Connect the temporary register R6 to the output. 12 bits signed binary number.

Page 19 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Table 4: Synthesis Summary for 17 bit Custom Precision Floating Point to 12 bit Signed Binary Number Conversion.

FPGA Pro- Speed cessor Grade

Number of Slices Used

Number of Slice Flip Flops Used

Number of 4 input LUTs Used

Number of bonded IOBs Used

Maximum Frequency

Spartan 3E -5 XC3S500E

56 out of 4656

47 out of 9312

100 out of 9312

30 out of 232

199.222 MHz

Spartan 3E -5 XC3S1200E

56 out of 4656

47 out of 9312

100 out of 9312

30 out of 232

199.222 MHz

Spartan 6 -3 XC6SLX25

48 out of 30064

72 out of 15032

90 out of 486

30 out of 226

248.738 MHz

Virtex 4 -12 XC4VFX100

55 out of 42176

47 out of 84352

99 out of 84352

30 out of 576

340.833 MHz

Virtex 5 -3 XC5VFX100T

47 out of 64000

61 out of 64000

80 out of 339

30 out of 680

440.567 MHz

Virtex 6 -2 XC6VCX130T

47 out of 160000

72 out of 80000

90 out of 408

30 out of 240

461.563 MHz

Conclusion and Future work We have successfully implemented and tested the functionality of custom precision floating point numbers on FPGAs. The main objective of this research is to develop and implement a real-time sensor data acquisition system based on FPGA. In order to achieve it, the following activities are planned be carried out in future: Implementation of Multiplication, Addition/Subtraction and Division algorithms on custom precision numbers on FPGAs, Implementation of I 2 C protocol to read serial ADC data on FPGA, Implementation of SD card and display module on FPGA to store and display real-time sensor data. These algorithms would be helpful in handling physical connections, storage and display of incoming sensor data and implementation of some basic digital signal processing techniques.

Page 20 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

References [1] Xilinx documentation on Field Programmable Gate Arrays (FPGA), Available online at: http://www.xilinx.com/training/ fpga/fpga-field-programmable-gate-array.htm (last accessed on 26-Oct-2012. [2] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice-Hall, Inc. Upper Saddle River, NJ, USA, ISBN: 0-13-451675-3. [3] Uwe Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology), ISBN: 978-3-540-72613-5. [4] IEEE Standard for Floating-Point Arithmetic, IEEE Std 754-2008, pp.1-58, Aug. 29 2008. [5] Decimal to Floating Point Conversion, Tutorial from Computer Science group in the Department of Mathematics and Computer Science, Mississippi College, Clinton, Mississippi, USA. Available online at: http: //sandbox.mc.edu/~bennet/cs110/flt/dtof.html (last accessed on 03Oct-2012). [6] Floating Point to Decimal Conversion, Tutorial from Computer Science group in the Department of Mathematics and Computer Science, Mississippi College, Clinton, Mississippi, USA. Available online at: http: //sandbox.mc.edu/~bennet/cs110/flt/ftod.html (last accessed on 03Oct-2012). [7] L. Louca, T. A. Cook, W. H. Johnson, Implementation of IEEE single precision floating point addition and multiplication on FPGAs, FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on, pp.107-116, 17-19 Apr 1996. [8] W. B. Ligon, S. McMillan, G. Monn, K. Schoonover, F. Stivers, K. D. Underwood, A re-evaluation of the practicality of floating-point operations on FPGAs, FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on, pp.206-215, 15-17 Apr 1998. [9] A. Guntoro and M. Glesner, High-performance fpga-based floating-point adder with three inputs, Field Programmable

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

Logic and Applications, 2008. FPL 2008. International Conference on, pp.627-630, 8-10 Sept. 2008. [10] M. Al-Ashrafy, A. Salem, W. Anis, An efficient implementation of floating point multiplier, Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International, pp.1-5, 24-26 April 2011. [11] Diniz, P.C.; Govindu, G., Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit, Field Programmable Logic and Applications, 2006. FPL ’06. International Conference on, pp.1-4, 28-30 Aug. 2006. [12] Shao Jie; Ye Ning; Zhang Xiao-Yan, An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs, Computer Science and Software Engineering, 2008 International Conference on, vol.4, pp.50-53, 12-14 Dec. 2008. [13] Kumar Jaiswal, M.; Chandrachoodan, N., Efficient Implementation of Floating-Point Reciprocator on FPGA, VLSI Design, 2009 22nd International Conference on, pp.267-271, 5-9 Jan. 2009. [14] Ould Bachir, T.; David, J.-P., Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision, Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on, pp.105-108, 2-4 May 2010. [15] Kumar, Y.; Sharma, R.K., Clock-less Design for Reconfigurable Floating Point Multiplier, Computational Intelligence, Modelling and Simulation (CIMSiM), 2011 Third International Conference on, pp.222-226, 20-22 Sept. 2011. [16] Texas Instruments ADS7828 datasheet, Available online at: www.ti. com/lit/ds/symlink/ads7828.pdf (last accessed on 26-Oct-2012). [17] Xilinx ISE Project Navigator Ver. 13.4 and Xilinx ISE Simulator, Available online at: http://www.xilinx.com/products/ design-tools/ise-design-suite/index.htm (last accessed on 26-Oct2012). [18] Digilent NEXYS 2 FPGA board, Available online at: http://www. digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 (last accessed on 26-Oct-2012).

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

[19] Xilinx Spartan3E FPGA Datasheet, Available online at: www.xilinx. com/support/documentation/data_sheets/ds312.pdf (last accessed on 03-Oct-2012). This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 3.0 Unported License (http: //creativecommons.org/licenses/by/3.0/). c 2013 by the Authors. Licensed & Sponsored by HCTL Open, India.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

Figure 4: Flow diagram for conversion of a 12 bit Signed Binary Number in to a 17 bit Custom Precision Floating Point Number - Pipelined approach

Raj Gaurav Mishra and Amit Kumar Shrivastava Page 24 Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

Figure 5: Simulation Results for 12 bit Signed Binary Number to 17 bit Custom Precision Floating Point Conversion

Figure 6: Simulation Results for 17 bit Custom Precision Floating Point to 12 bit Signed Binary Number Conversion

Figure 7: Digilent NEXYS 2 FPGA board hardware setup for algorithm testing and verification

Page 25 Raj Gaurav Mishra and Amit Kumar Shrivastava Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

Figure 8: Flow diagram for conversion of a 17 bit Custom Precision Floating Point Number in to a 12 bit Signed Binary Number - Pipelined approach

Raj Gaurav Mishra and Amit Kumar Shrivastava Page 26 Implementation of Custom Precision Floating Point Arithmetic on FPGAs.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

An Enhanced TCP Corruption Control Mechanism For Wireless Network Preetam Suman and Amrit Suman preetam.suman@ieee.org and amrit.it@gmail.com

Abstract obile Ad Hoc networks are collections of mobile nodes, dynamically forming a temporary network without pre-existing network infrastructure or centralized administration. Transmission control protocol (TCP) provides connection oriented, reliable and end to end mechanism. Comparing to wire networks, there are many different characteristics in wireless environments. In this paper an improved mechanism for TCP corruption control is presented. It considers the influences sending rate to TCP sender’s packet not only by the congestion but also by the corruption. The sending window size calculated after each transmission, based on number of corrupted packet. So, there is less packet drop in transmission. The comparative study of Enhanced TCP (ETCP) with other TCP variants is also presented on various parameters like mobility, size of network and the speed. The improved mechanism is implemented with fewer overheads and is effectively improve reliability with small variances of throughput and delay. Implementation and Simulation is performed in QualNet 4.0 simulator.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Keywords Wireless Network, Congestion Control, Corruption Control, TCP Variants.

Introduction Transmission control protocol (TCP) [1, 2] is the predominant Internet protocol and carries approximately 90% of Internet traffic in today’s heterogeneous wireless and wired networks. TCP is widely used as a connection oriented transport layer protocol that provides reliable packet delivery over unreliable links. TCP does not depend on the underlying network layers and, hence, design of various TCP variants is based on the properties of wired networks. However, TCP congestion control algorithms may not perform efficiently in heterogeneous networks. Wireless networks have higher bit error rates due to weather conditions, obstacles, multipath interferences, mobility of wireless end-devices, signal attenuation and fading, which may lead to packet loss. Various TCP algorithms and techniques have been proposed to improve congestion and reduce the non-congestion related packet loss. TCP Tahoe [11], TCP Reno [13], TCP Reno with Selective Acknowledgement (SACK) [11], TCP NewReno [12], TCP Vegas [15], and TCP FACK [14] are examples of proposed end-to-end solutions. They are all proposed to improve network performance [3]-[9]. The end-to-end techniques are the most promising because they require changes only to the end systems instead to the intermediate nodes. These end-to-end control approaches are used in today’s deployed networks. In Section 2, algorithm of ETCP is described. Description of simulated network is given in Section 3, while simulation scenarios and results are described in Section 4, simulation methodology is described in Section 5 conclusion and future work is explained with Section 6. Corruption Loss Rate - The corruption loss rate defined as the packet loss rate because of corruption. Sending rate is not adjusted when the there is little corruption loss rate, but its required to decrease the sending rate rapidly to improve the reliability when the corruption loss rate becomes higher. Otherwise, there will be more lost packets due to corruption and more packets will be retransmission, responding the poor transmission reliability and more energy consumption of mobile hosts.

Page 28 Preetam Suman and Amrit Suman An Enhanced TCP Corruption Control Mechanism For Wireless Network.


HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 The corruption loss rate define as: P e = m/n

(1)

Where, Pe is the corruption loss rate defined in [10]. If TCP sender sends n packets in which m packets may be discarded due to weak wireless link. The corruption loss rate decides by the bit error rate (BER) of wireless link layer and the length (Length) of data frame: P e = 1 − (1 − BER)Length

(2)

If the corruption loss rate Pe is higher than the certain lower limit Pemin , the sending rate will be decreased. Many factors decide the value of corruption loss rate lower limit Pemin , mainly include: the kind of application; the length of data frame; the bit error rate of data link layer; the bandwidth and the transmission delay of wireless network etc. Normally value of Pemin is 0.4.

Enhance TCP ETCP (Enhanced Transport Control Protocol) is the improved TCP congestion and corruption control mechanism for wireless network. It considers the influences to TCP sender’s packet sending rate not only by the congestion but also by the corruption. It is a good reference to apply the TCP to wireless networks.

Initial Window The initial sending window is calculated by following formula: Iw= min (4 * SMSS , Max (2 * SMSS , 4380 byte))

Slow-Start Algorithm The slow start algorithm is used to start a connection of ETCP and the periods after the value of retransmission timer exceed the RTO (retransmission timeout). In the start of ETCP, the size of cwnd will be initialized to 1. The slow start algorithm describes as below: if (Receive ACKs && cwnd < ssthresh) { cwnd = cwnd++; }

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

The slow start algorithm will be ended in two conditions. First, if the congestion window size reaches the slow start threshold size (ssthresh), the slow start will be ended and then congestion avoidance takes over. Second, if there lose any packet due to congestion or high packet loss rate due to corruption, the slow start also will be ended and then fast recovery takes over.

Congestion Avoidance Algorithm If the congestion window size (cwnd) is less than or equal to the slow start threshold size (ssthresh), DW-TCP is in slow start; otherwise ETCP is performing congestion avoidance. The congestion avoidance algorithm describes as below: if (Receive ACKs || (Receive Explicit Corruption Loss Notification && Corruption Loss Rate P e < Pemin )) { if (cwnd > ssthresh) cwnd = 1+1/cwnd else cwnd++; if (Receive Explicit Corruption Loss Notification) Pe= (m/n); If (Pe < Pemin ) Pemin = Pe; temp=cwnd* Pemin ; cwnd=cwnd temp; }

In the algorithm, cwnd is the congestion window size; n is total number of packets to be send; m is the number of lost packets due to wireless link corruption; Pe denotes the corruption loss rate.

Fast Retransmission and Fast Recovery If the network congestion or heavy corruption, the fast recovery algorithm will be taken. When the network congestion, set ssthresh to one-half the flight size or double of SMSS (maximum segment size) window. if (Congestion || Heavy Corruption) { if (Receive Same ACK 3 Times || Retransmission Timer Overtime) /* Congestion */

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 { Ssthresh = max(flightsize/2 , 2*SMSS); // Flightsize are those data which have no acknowledged. if (Retransmission Timer Overtime) { cwnd = 1; Exit and call slow-start;} else /* Receive Same ACK 3 Time */ cwnd = ssthresh; } else if (Receive Explicit Corruption Loss Notification && Corruption Loss Rate Pe>=Pemin ) { temp=cwnd* Pemin ; cwnd=cwnd+ temp; }; if (Receive Explicit Loss Corruption Notification) Pe= (m/n); If (Pe < Pemin ) Pemin = Pe; temp=cwnd*Pemin ; cwnd=cwnd - temp; }

Computer Simulation In this paper all the simulation work is performed in QualNet [11] wireless network simulator version 4.0. Initially number of nodes are 50, Simulation time was taken 200 seconds and seed as 1. All the scenarios have been designed in 1500m x 1500m area. Mobility model used is Random Way Point (RWP). In this model a mobile node is initially placed in a random location in the simulation area, and then moved in a randomly chosen direction between at a random speed between [SpeedM in , SpeedM ax ]. The movement proceeds for a specific amount of time or distance, and the process is repeated a predetermined number of times. Nodes in network moves with speed of 5 m/s to 30m/s, and with pause time of 5s to 30s. All the simulation work was carried out using TCP variants (Reno, Lite, Tahoe) with DSR routing protocol. Network traffic is provided by using File Transfer Protocol (FTP) application. File Transfer Protocol (FTP) represents the File

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 Transfer Protocol Server and Client.

Simulation Methodology Parameters Simulation Time Node Area Pause Time TCP Protocol Routing Protocol Node Speed (m/sec)

Scenario 1 constant constant constant constant change constant change

Scenario 2 constant constant constant change change constant constant

Scenario 3 constant change constant constant change constant constant

Table 1: Simulation Scenarios

Performance metrics used for this works are as follows: Throughput is the measure of the number of packets successfully transmitted to their final destination per unit time. It is the ratio between the numbers of sent packets vs. received packets. Signal Received with error is the measure of signal received, but they have error. The error may be occurring due to noise or due to heavy traffic. Bytes received are the measure of total packet received by server. The packets may be drop due to heavy traffic. So received packets may be vary according to traffic conditions. Packet loss is the measure of total discarded packet due to corruption or due to packet drop. It can be calculate by subtracting total received packets by server with total sent packet by client.

Results and Analysis Fig 1, 2 & 3 shows signal received with error of different variants with variation in speed of node, pause time and number of node in network. It has to be seen that ETCP has less error signal than other TCP variants. Due to optimal

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6 routing path between sender and receiver. When number of node in network increases than congestion also occurs, due to this reason, signals were distorted.

Figure 1

Figure 2

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 3

Fig 4, 5 & 6 shows Packet loss of different variants of TCP with variation in node speed, pause time and number of node. It has to be seen that ETCP has less packet loss than other TCP variants. It is due to proper sending window size, which is calculated according to number of discarded packets. So, receiver can receive those packets which are sent by sender.

Figure 4

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 5

Figure 6

Fig 7, 8 & 9 shows the readings of total byte received for different TCP variants with variation in speed of node, pause time and number of node in network. It has to be seen that receiver can receive maximum byte at ETCP, but it is sometimes less due to congestion in network. Sometimes nodes can move faster, so nodes cannot get proper signal, due to this reason nodes cannot received packets.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 7

Figure 8

Fig 10, 11 & 12 shows throughput of different TCP variants with variation in node speed, pause time and number of node. Throughput is the ratio of numbers of sent packets with number of received packets. It has to be seen that Throughput of ETCP is better than other TCP variants. Receiver receive maximum packets and there are less packets were discarded, due to this reason throughput is better.

Conclusion An enhanced TCP (ETCP) is proposed with a new calculation for sending window and implemented it in a Mobile Ad-hoc Network in QualNet 4.0. It

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 9

Figure 10

considers the influences sending rate to TCP senderâ&#x20AC;&#x2122;s packet not only by the congestion but also by the corruption. The sending window for ETCP is calculated according to packet corrupted in network. Extensive simulation studies were undertaken to compare its performance with other standards TCP Reno, TCP Lite and TCP Tahoe over Ad-hoc Mobile Network. The simulation results show that the performance of ETCP is better than other than other TCP variants. The performance of TCP variants are analysed on various parameters like mobility, size of network and the speed. The comparison of TCP variants are performed using various performance metrics like signal received with error, total data packet received, total packet drop and throughput.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 11

Figure 12

From results of implementation it has be seen that the performance of ETCP is better in high density node because in this condition sender can get different paths through different nodes. Packets can be corrupted due to congestion in network or heavy traffic, due to this reason packet drop is fewer in less density network. Signals also affected due to improper routing path in network, so maximum signal were distorted when nodes in network are moving with speed of 5m/sec.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

Throughput depends on number of packet received and number of packets loss. It is better in high density network, because receiver can receive maximum packets when number of node in network is 50.

Future Work The performance of ETCP can be measured in different wireless environments especially those with high error rates. It can also be plan to build a flexible and lightweight transport protocol for the wireless side of ETCP which can adapt to changes in the wireless environment and can support planned disconnections. Presentation layer services can also be built on top of ETCP which will allow mobile applications to dynamically choose a format for data transmitted over the wireless medium. Other work includes testing throughput intensive applications such as ftp and mosaic with ETCP.

References [1]

J. Postel, Transmission control protocol, RFC 793, Sept.1981.

[2] A. Gurtov and S. Floyd, Modeling wireless links for transport protocols, ACM SIGCOMM Comput. Commun. Rev., vol. 34, no. 2, pp. 85-96, Apr. 2004. [3] G. Holland and N. Vaidya, Analysis of TCP performance over mobile ad hoc networks in Proc. ACM/IEEE Int. Conf. on Mobile Computing, Seattle, WA, USA, Sept. 1999, pp. 219-230. [4] Y. Shang and M. Hadjitheodosiou, TCP splitting protocol for broadband and aeronautical satellite network in Proc. 23rd IEEE Digital Avionics Syst. Conf., Salt Lake City, UT, Oct. 2004, vol. 2. [5] J. Zhu, S. Roy, and J. H. Kim, Performance modeling of TCP enhancements in terrestrial-satellite hybrid networks IEEE/ACM Trans. Netw., vol. 14, no. 4, pp. 753-766, Aug. 2006. [6] C.-H. Ng, J. Chow, and Lj. Trajkovic, Performance evaluation of the TCP over WLAN 802.11 with the Snoop performance enhancing proxy, OPNETWORK 2002, Washington, DC, Aug. 2002. [7] W. G. Zeng, M. Zhan, Z. Li, and Lj. Trajkovic, Improving TCP performance with periodic disconnections over wireless links, OPNETWORK 2003, Washington, DC, Aug. 2003.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

[8] W. G. Zeng and Lj. Trajkovic, TCP packet control for wireless networks in Proc. IEEE Int. Conf. on Wireless and Mobile Computing, Networking and Communications (WiMob 2005), Montreal, Canada, Aug. 2005, vol. 2, pp. 196-203. [9] M. Omueti and Lj. Trajkovic, M-TCP+: using disconnection feedback to improve performance of TCP in wired/wireless networks in Proc. SPECTS 2007, San Diego, CA, USA, July 2007, pp. 443-450. [10] Xu Chang-Biao, Long Ke-Ping, Yang Shi-Zhong. Corruption-based TCP rate adjustment in wireless networks In: Chinese Journal of Computers, 2002, 25(4): pp.438-444. [11] Scalable Network Technology, QualNet4.0 simulator tutorial and QualNet Forum, http://www.scalable-networks.com/forums/ [12] K.Fall, S.Floyd, Simulation Based Comparison of Tahoe, Reno and SACK TCP, ACM SIGCOMM Computer Communication Review, Volume 26 Issue 3, July 1996. [13] S. Floyd, The NewReno Modification to TCP’s Fast Recovery Algorithm, RFC 3782, April 2004. [14] B. Qureshi, M. Othman, Member, IEEE, and N. A. W. Hamid, Progress in Various TCP Variants, February 2009. [15] M. Mathis and J. Mahdavi, Forward acknowledgment: refining TCP congestion control, in Proceedings of ACM SIGCOMM, pp. 181-191, 1996. [16] Lawrence S. Brakmo, Student Member, IEEE, and Larry L. Peterson, TCP Vegas: End to End Congestion Avoidance on a Global Internet, OCTOBER 1995. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution 3.0 Unported License (http: //creativecommons.org/licenses/by/3.0/).

©2013 by the Authors. Licensed & Sponsored by HCTL Open, India.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant Vimal Upadhyay, Krishna Kant Agrawal, Mukesh Chand and Devesh Mishra vimalupadhyay2002@gmail.com, krishna.agrawal@sify.com, mukeshchand19@gmail.com and deveshbbs@gmail.com

Abstract iping in the oil and nuclear plants are subject to erosion or corrosion inside pipe wall. This corrosion or erosion depends on chemical aggressively of fluids, operational conditions and pipeline materials. In many cases inspection become tough when pipes are mounted several meters above the ground for a human testing personnel. Sometimes, inspection done during shut- down of plant or removal of surrounded armatures. For in service maintenance or inspection of these plants, there is always a desire for optimal solution. The NDT (Non Destructive Testing) developments for measuring flow accelerated corrosion or thickness degradation. Our first task is to deploy and connect ultrasonic sensor for measuring pipe wall thickness in such a design, their values can be evaluated at accessible point.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Keywords Non Destructive Testing (NDT), Flow Accelerated Corrosion (FAC), Ultrasonic Testing (UT), Pipe Inspection Gauge (PIG), Piezoelectric Transducer (PZT), Electromagnetic Acoustic Transducers (EMAT), Strong Static Magnetic Field (SSMF), Liquid Coupled Method (LCM), Wheel Coupled Method (WCM).

Introduction In present scenario there is no single system which measures all pipelines. In present era commonly used tool is PIG (pipe inspection gauge) that moves inside the pipe. Crawler move down to the pipeline independently and stop if major defect assessment. The sensors are mounted on crawler; they are almost small in size, lightweight and required low power consumption. Therefore, the distance between measurement and evaluation can be bridge by cable (in order of 100 meters). Pipe wall thickness degradation due to flow accelerated corrosion gave a birth to leaks and raptures in piping system which cannot be identify at early stage. Ultrasonic examination methods are typically used to monitor pipe conditions in terms of thickness, erosion and corrosion. In this paper we focus on design issues of ultrasonic system for rapid scanning of sample model. Ultrasonic testing is completed with the help of ultrasonic waves (Primary wave) which uses 20 KHz to 200 KHz high frequency sound energy for making accurate measurements of thickness, corrosion and erosion with the help of sensors. Ultrasonic examinations can be conducted to known the properties of material including castings, forgings, geometry, welds, and composites. We collect a considerable amount of information related to turbine, boilers with the help of instrument where human being approach is impossible. In this technique first we generate guided wave with the help of ultrasonic generators than we collect information with the help of receiver (sensor). This gathered information passed from Micro-channel plate detector for resolution and getting more accurate readings. Pipelines are worldwide used for distributing energy to end users. The pipeline deployment is well designed and required in service monitoring for natural degradation to overcome sudden failures. A mostly failure in pipeline occurs due to ageing factor of pipe system for examples leak, corrosion, erosion and raptures etc.

Vimal Upadhyay et al. Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Ultrasonic System for Pipe Wall Measurement In 1980s high frequency sound waves are used for sample object inspection. The basic principle is shown in the figure 1. The working model of hand-held

Figure 1: Pulse echo Ultrasonic System for pipe wall measurement

ultrasonic gauge based on the principle of pulse echo method to determine accurate pipe sample thickness and raptures. Pulses of ultrasonic energy are launched with the help of piezoelectric transducer, angle beam etc. Energy band of ultrasonic testing varies 1-10 MHz. These energy pulses are reflected by inside and outside wall of the sample object. The thickness is measured by calculating reflection time and speed of sound in steel pipe. For industrial perspective thickness measurement accuracy required 0.001â&#x20AC;? (0.025 mm). Especially in case of noisy areas we prefer high frequency transducers for more accurate results. To overcome pipeline surface roughness challenges we use lower frequency transducers (5 MHz) for accurate results. The typical accuracy for in service inspection is 0.020â&#x20AC;? (0.5 mm). Ultrasonic tools require a large number of tiny sensors, in the order of ten per inch diameter. Data processing and storage time directly affect the speed of inspection. In early years (1989) inspection speed of ultrasonic system in the range of 3.0 mph. Now recent state of art in electronics pushes up speed of inspection. Ultrasonic Testing gave an accurate reading in noise free pipes; lamination and inclusions on a pipe reduce accuracy. In ultrasonic testing misses to catch out defects lying behind laminations. Therefore applying ultrasonic gauge system we make a pipe free from debris or deposits.

Vimal Upadhyay et al. Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Ultrasonic Crack Detection System Most common methods which are used to determine cracks in pipeline: 1. Liquid Coupled Method. 2. Wheel Coupled Method. 3. Electromagnetic Acoustic Transducers. These above methods are capable for crack detection but all have some limitations:In case of wheel coupled method numbers of sensors are limited to number of wheels. The number of sensors in liquid coupled methods has many more in comparison to wheeled tool. Two common tools are: 1. Liquid Coupled Angle Beam Tool 2. Wheel Coupled Angle Beam Tool Difficulties in angle beam tools are same as difficulties arise in wall thickness measurement tool. For example: 1. Speed Restriction 2. To differentiate cracks from lamination and inclusion After several attempts to above system EMAT (Electromagnetic Acoustic Transducers) inspection system came in focus for determine cracks in pipe wall thickness. EMAT ultrasonic testing technique operates at lower frequency (200-800 KHz) in comparison to PZT (1-20 MHz). The waves generated by EMAT are bounded by the geometry of sample object. The waves generally generated by EMAT are shown in figure 2. For generating above waves two things are essential: 1. Strong Static Magnetic Field 2. Coil Coils are used for creating localized eddy current in the sample object. Eddy current oscillates at the designed inspection frequency. Wave mode directly depends on pipe wall thickness. If we make a small change in variable cause a different wave mode, which affects result of inspected sample object. The coil near to sample object are generate sufficient amount of energy required to determine cracks even hidden by laminations. For long distance pipe wall

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Figure 2: Waves generated by EMAT

inspection, the coil is covered by thin polymers. Advantages of EMAT in comparison to Liquid Coupled Method and Wheel Coupled Method: 1. No need for liquid coupling media. 2. Bounded waves propagate in sample object. Disadvantages of EMAT in comparison to Liquid Coupled Method and Wheel Coupled Method: 1. Many modes. 2. Different results by different mode. 3. Implementation Challenges.

Simulation Models Ultrasonic testing simulation models use numerous methods and physical equations for predicting results of an experiment. The potential uses of simulation model classified into three categories as shown in Table ??. All above queries except last three are cracked by UTSIM (Measurement model). Last three queries are related to scan coverage modelling, scan coverage problems are sort out by a beam model.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

Table 1: Simulation Model Parameters

Ultrasonic reach the region of sample object?

Properties of the field in region of sample object?

Response from the incident field of sample object?

What is amplitude?

Shape of beam?

Time domain waveform?

Beam passes through concave interface?

Phase curvature?

Flow change?

Beam spread when it Focal point? propagates into material?

–X–

Beam bend?

–X–

–X–

Amplitude loses due –X– to coupling?

–X–

–X–

–X–

–X–

response

Scan Optimization Industrial objective towards scan optimization is to minimize in-service inspection cost for accomplishing a specific task or optimum in service inspection under specified cost. Modelling objective towards scan optimization is to maximum sensitivity for a given scan spacing. In scan optimization we focused on following points: 1. Best location to place a probe. 2. Optimum wedge angle. 3. Optimum transducer coverage.

Scope of Modelling in Ultrasonic Automated scans using longitudinal waves at normal incidence, automated scans for deterministic and repeatable of accurate motion. Contact scans are excluded due to variability in coupling. Two important spacing parameters index and scan spacing are beneficial for chosen a coordinate system for example optimum change in beam width along index direction. Qualities of coordination

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

direction they are orthogonal by nature. Index coordinates direction used for radial cross section of the sample object. Scanning of sample object is modelled in lower dimension.

Figure 3: Scan Direction v/s Index Direction

Result and Conclusion The above system reduce cost of non destructive testing and required time in petrochemical plant, also increase operating safety, minimized processing cost, reduce testing intervals and this system make easy continuous supervision possible. Advantages of above system in comparison to other models are: No need for liquid coupling media and Bounded waves propagate in sample object. Disadvantages of above system in comparison to other models are: Many modes, Different results by different mode, Implementation Challenges, etc.

Acknowledgement We thank to our Honourable Director Sir (IIIT-Allahabad) for allowing us to perform this research work by providing excellent academic facility under his privileged guidance.

References [1] Hideo Nishino, Simple method of generating for circumferential shear horizontal waves in a pipe and their mode identifications, Institute of Science and Technology, Japan 2006.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

[2] W. Harara, Pit-Depth Measurement on Large Diameter Pipes by Tangential Radiography Using a Co-60 Gamma-Ray Source, Russian Journal of Non-destructive Testing, Vol. 40, No. 11, 2004. [3] Calkins, F.T., Smith, R.D., and Flatau, A.B., An Energy-based Hysteresis Model for Magnetostructive Transducers, IEEE Transactions on Magnetics, submitted 10/97. [4] Dapino, M.J., Calkins, F.T., and Flatau, A.B., On Identification and analysis of fundamental issues in Terfenol-D transducer modeling, SPIE 1998, Proceedings on Smart Structures and Integrated Systems, paper no. 23, Vol. 3329, 3/98. [5] Glenn M. Light , Health Monitoring of Piping and Plate Using the Magnetostrictive Sensor (MsS) Guided-Wave Technology, Southwest Research Institute San Antonio, TX 78228, 2010. [6] K.Imano, Possibilities of non-destructive evaluation of a pipe using air-coupled ultrasonic wave in the MHz range, IEICE 2008. [7] http://www.ndt.org, Non Destructive Testing, 14 November 2009. [8] J H BUNGEY, Non Destructive Testing in UK, Seiken Symposium 2000. [9] http://www.wikipedia.com, Non Destructive Testing. [10] A P Ferrerira and P F Castro, NDT for assessing concrete strength, Seiken Symposium 2000. [11] J F Hinslay, Text Book of Non destructive Testing. [12] K Brandes, J Herther and R. Helmerich, Non-destructive testing being essential part of the safety assessment of steel bridges, Seiken Symposium 2000. [13] N.Tamura and K.Takada, Seiken Symposium 2000.

High Evaluation Inspection Vehicle,

[14] K R Maser and I sande, Application of Ground Penetration RADAR technique for evaluation of Air field pavement, Seiken Symposium 2000.

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HCTL Open Int. J. of Technology Innovations and Research HCTL Open IJTIR, Volume 1, January 2013 e-ISSN: 2321-1814 ISBN (Print): 978-1-62776-012-6

References

[15] Y.H.Cha anb J H shu, Differential approach to Ultrasonic Testing of Strength and Homogeneity of concrete, Seiken Symposium 2000. [16] IHI Inspection and Instrument Cooperation Limited, http://www. iic-hq.co.jp [17] http://ndt-ed.org This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution 3.0 Unported License (http: //creativecommons.org/licenses/by/3.0/). c 2013 by the Authors. Licensed & Sponsored by HCTL Open, India.

Vimal Upadhyay et al. Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant.

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Volume 1, January 2013  

HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 1, January 2013, ISSN: 2321-1814, ISBN: 978-1-62776-0...

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