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‫اﻟﺠﻤﻬﻮرﻳﺔ اﻟﻌﺮﺑﻴﺔ اﻟﺴﻮرﻳﺔ‬ ‫وزارة اﻟﺘﻌﻠﻴﻢ اﻟﻌﺎﻟﻲ‬ ‫ﺟﺎﻣﻌﺔ ﺣﻠﺐ – آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻟﻜﻬﺮﺑﺎﺋﻴﺔ واﻻﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻟﺤﻮاﺳﻴﺐ – ﻣﺨﺒﺮ اﻟﺤﺎﺳﺒﺎت‬ ‫إﻋﺪاد اﻟﻤﻬﻨﺪس ‪ :‬أﺳﺎﻣﺔ ﻋﺰﻳﺰ‬

‫ﻣﻠﺨﺺ اﻟﺠﻠﺴﺔ اﻟﺜﺎﻣﻨﺔ ﻟﻄﻼب اﻟﺴﻨﺔ اﻟﺜﺎﻟﺜﺔ ‪ :‬ﺣﺎﺳﺒﺎت ‪ +‬اﻟﻜﺘﺮون‬ ‫ﺁﻻت اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ‪Finite State Machines‬‬

‫اﻟﻔﺼﻞ اﻟﺪراﺳﻲ اﻷول‬ ‫‪٢٠١١ - ٢٠١٠‬‬


‫ﺁﻻت اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ‪Finite State Machines‬‬ ‫ﺗﺸﻜﻞ ﺁﻻت اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ) ‪ ( FSM‬ﺗﻘﻨﻴﺔ ﻧﻤﺬﺟﺔ ﺧﺎﺻ ﺔ ‪ Special Modeling Technique‬ﻣ ﻦ أﺟ ﻞ دارات‬ ‫اﻟﻤﻨﻄﻖ اﻟﺘﺘﺎﺑﻌﻲ ‪ . Sequential Logic Circuits‬إن ﻧﻤﻮذﺟًﺎ آﻬﺬا ﻳﻤﻜﻦ أن ﻳﻜﻮن ﻣﻔﻴ ﺪًا ﺟ ﺪًا ﻓ ﻲ ﺗﺼ ﻤﻴﻢ أﻧ ﻮاع‬ ‫ﻣﻌﻴﻨﺔ ﻣﻦ اﻷﻧﻈﻤﺔ وﺧﺎﺻﺔ ﺗﻠ ﻚ اﻟﺘ ﻲ ﺗﺸ ﻜﻞ ﻣﻬﺎﻣﻬ ﺎ ﺗﺎﺑﻌ ًﺎ ﻣﺤ ﺪدًا ﺑﺸ ﻜﻞ ﺟﻴ ﺪ ﻣ ﻦ اﻷﺣ ﺪاث ) آﺎﻟﻤﺘﺤﻜﻤ ﺎت اﻟﺮﻗﻤﻴ ﺔ‬ ‫‪ Digital Controllers‬ﻋﻠ ﻰ ﺳ ﺒﻴﻞ اﻟﻤﺜ ﺎل ( ‪ .‬ﺳ ﻮف ﻧﺒ ﺪأ اﻟﺠﻠﺴ ﺔ ﺑﻤﺮاﺟﻌ ﺔ اﻟﻤﻔ ﺎهﻴﻢ اﻷﺳﺎﺳ ﻴﺔ اﻟﻤﺘﻌﻠﻘ ﺔ ﺑ ﺂﻻت‬ ‫اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ‪ . FSMs‬ﻣﻦ ﺛﻢ ﺳﻮف ﻧﻌﺮض ﺗﻘﻨﻴﺎت اﻟﺘﺸﻔﻴﺮ اﻟﻤﻮاﻓﻘﺔ ﺑﻠﻐ ﺔ ‪ VHDL‬وﻧﺘﺒ ﻊ ذﻟ ﻚ ﺑﺄﻣﺜﻠ ﺔ ﺗﺼ ﻤﻴﻤﻴﺔ‬ ‫آﺎﻣﻠﺔ ‪.‬‬ ‫‪ -١-٨‬ﺗﻤﻬﻴﺪ ‪Introduction :‬‬ ‫ﻳﺒ ﻴﻦ اﻟﺸ ﻜﻞ )‪ (١-٨‬اﻟﻤﺨﻄ ﻂ اﻟﻜﺘﻠ ﻲ ﻵﻟ ﺔ ﺣﺎﻟ ﺔ وﺣﻴ ﺪة اﻟﻄ ﻮر ‪ . Single-Phase State Machine‬آﻤ ﺎ ه ﻮ‬ ‫ﻣﻮﺿﺢ ﻓﻲ اﻟﺸﻜﻞ ﻓ ﺈن اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ ﻳﺤﺘ ﻮي اﻟﻤﻨﻄ ﻖ اﻟﺘﺘ ﺎﺑﻌﻲ ‪ ) Sequential Logic‬اﻟﻘﻼﺑ ﺎت ( ﻓ ﻲ ﺣ ﻴﻦ أن‬ ‫اﻟﻤﻘﻄﻊ اﻟﻌﻠﻮي ﻳﺤﺘﻮي اﻟﻤﻨﻄﻖ اﻟﺘﺮآﻴﺒﻲ ‪. Combinational Logic‬‬ ‫ﻳﻤﺘﻠ ﻚ اﻟﻤﻘﻄ ﻊ اﻟﺘﺮآﻴﺒ ﻲ ) اﻟﻌﻠ ﻮي ( ﻣ ﺪﺧﻠﻴﻦ اﺛﻨ ﻴﻦ أﺣ ﺪهﻤﺎ ه ﻮ اﻹﺷ ﺎرة ‪ ) Pr_State‬اﻟﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ أو اﻟﺮاهﻨ ﺔ‬ ‫‪ ( Present State‬واﻵﺧﺮ هﻮ إﺷ ﺎرات اﻟ ﺪﺧﻞ اﻟﻔﻌﻠﻴ ﺔ ﻟﻸوﺗﻮﻣ ﺎت ‪ . External Input Proper‬آﻤ ﺎ ﻳﻤﺘﻠ ﻚ ه ﺬا‬ ‫اﻟﻤﻘﻄﻊ ﻣﺨﺮﺟﻴﻦ اﺛﻨﻴﻦ أﻳﻀًﺎ أﺣﺪهﻤﺎ هﻮ اﻹﺷ ﺎرة ‪ ) Nx_State‬اﻟﺤﺎﻟ ﺔ اﻟﺘﺎﻟﻴ ﺔ أو اﻟﻘﺎدﻣ ﺔ ‪ ( Next State‬واﻵﺧ ﺮ‬ ‫هﻮ إﺷﺎرات اﻟﺨﺮج اﻟﻔﻌﻠﻴﺔ ﻟﻸوﺗﻮﻣﺎت ‪. External Output Proper‬‬ ‫ﻳﻤﺘﻠ ﻚ اﻟﻤﻘﻄ ﻊ اﻟﺘﺘ ﺎﺑﻌﻲ ) اﻟﺴ ﻔﻠﻲ ( ﺛﻼﺛ ﺔ ﻣ ﺪاﺧﻞ ه ﻲ ﻋﻠ ﻰ اﻟﺘﺮﺗﻴ ﺐ ‪ :‬إﺷ ﺎرة ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ Clock‬و ﻣ ﺪﺧﻞ‬ ‫اﻟﺘﺼﻔﻴﺮ ‪ Reset‬وإﺷﺎرة اﻟﺤﺎﻟﺔ اﻟﺘﺎﻟﻴﺔ ‪ Nx_State‬آﻤﺎ ﻳﻤﺘﻠﻚ ﻣﺨﺮﺟًﺎ وﺣﻴﺪًا هﻮ إﺷ ﺎرة اﻟﺤﺎﻟ ﺔ اﻟﺮاهﻨ ﺔ ) اﻟﺤﺎﻟﻴ ﺔ (‬ ‫‪ . Pr_State‬ﺑﻤ ﺎ أن آﺎﻓ ﺔ اﻟﻘﻼﺑ ﺎت ﺗﻮﺟ ﺪ ﻓ ﻲ ه ﺬا اﻟﺠ ﺰء ﻣ ﻦ اﻟﻨﻈ ﺎم ﻓ ﺈن اﻹﺷ ﺎرﺗﻴﻦ ‪ Clock‬و ‪ Reset‬ﻳﺠ ﺐ أن‬ ‫ﺗﻮﺻﻼ إﻟﻴﻪ ‪.‬‬ ‫إذا آﺎﻧﺖ ﻣﺨﺎرج اﻵﻟﺔ ﺗﻌﺘﻤﺪ ﻟﻴﺲ ﻓﻘﻂ ﻋﻠﻰ اﻟﺤﺎﻟﺔ اﻵﻧﻴﺔ ﺑﻞ ﻋﻠﻰ ﻗﻴﻤﺔ اﻟﻤﺪاﺧﻞ اﻟﺤﺎﻟﻴﺔ أﻳﻀًﺎ ﻓﺈﻧﻬﺎ ﺗﺪﻋﻰ ﺣﻴﻨﺌ ٍﺬ ﺁﻟ ﺔ‬ ‫ﻣﻴﻠﻲ ‪ . Mealy Machine‬ﻓﻲ اﻟﺤﺎﻟ ﺔ اﻟﻤﻘﺎﺑﻠ ﺔ ‪ ،‬إذا آﺎﻧ ﺖ ﻣﺨ ﺎرج اﻵﻟ ﺔ ﺗﻌﺘﻤ ﺪ ﻓﻘ ﻂ ﻋﻠ ﻰ اﻟﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ ﻓ ﺈن اﻵﻟ ﺔ‬ ‫ﺗﺪﻋﻰ ﺁﻟﺔ ﻣﻮر ‪ . Moore Machine‬ﻓﻲ وﻗﺖ ﻻﺣﻖ ‪ ،‬ﺳﻴﺘﻢ ﻋﺮض أﻣﺜﻠﺔ ﻋﻠﻰ آﻞ ﻣﻦ هﺬﻳﻦ اﻟﻨﻮﻋﻴﻦ ‪.‬‬

‫اﻟﺸﻜﻞ )‪ : (١-٨‬اﻟﻤﺨﻄﻂ اﻟﺼﻨﺪوﻗﻲ ﻵﻟﺔ ﺣﺎﻟﺔ ﻣﻨﺘﻬﻴﺔ ‪State Machine Block Diagram‬‬ ‫إن ﺗﻘﺴﻴﻢ اﻟﺪارة إﻟﻰ ﻣﻘﻄﻌ ﻴﻦ ) آﻤ ﺎ ﻓ ﻲ اﻟﺸ ﻜﻞ ‪ ( ١-٨‬ﻳﺘ ﻴﺢ ﻟﻠﺘﺼ ﻤﻴﻢ أن ﻳﻜ ﻮن ﻣﺆﻟﻔ ًﺎ ﻣ ﻦ ﺟ ﺰأﻳﻦ ﻣﻨﻔﺼ ﻠﻴﻦ ﺑﺸ ﻜﻞ‬ ‫ﻣﻨﺎﺳﺐ ‪ .‬ﻣﻦ ﻣﻨﻈﻮر ﻣﻨﻄﻠﻖ ﻣﻦ ﻟﻐﺔ ‪ VHDL‬ﻓﺈﻧﻪ ﻣﻦ اﻟﻮاﺿ ﺢ أن اﻟﻘﺴ ﻢ اﻟﺴ ﻔﻠﻲ وﺑﺎﻋﺘﺒ ﺎرﻩ ﺗﺘﺎﺑﻌﻴ ًﺎ ﺳ ﻮف ﻳﺘﻄﻠ ﺐ‬ ‫ﻣﻌﺎﻟﺠﺔ ‪ PROCESS‬ﻓﻲ ﺣﻴﻦ أن اﻟﻘﺴﻢ اﻟﻌﻠﻮي وﺑﺎﻋﺘﺒﺎرﻩ ﺗﺮآﻴﺒﻴًﺎ ﻟﻦ ﻳﺘﻄﻠﺐ ﺑﺎﻟﻀﺮورة ﻣﻌﺎﻟﺠﺔ ﺧﺎﺻ ﺔ ﺑ ﻪ ‪ .‬ﻟﻜ ﻦ‬ ‫ﻋﻠ ﻰ أﻳ ﺔ ﺣ ﺎل ‪ ،‬ﻳﻤﻜ ﻦ اﻟﺘ ﺬآﻴﺮ هﻨ ﺎ أن اﻟﻜ ﻮد اﻟﺘﺘ ﺎﺑﻌﻲ ﻗ ﺎدر ﻋﻠ ﻰ ﺗﻨﺠﻴ ﺰ ‪ Implement‬آ ﻞ ﻣ ﻦ ﻧ ﻮﻋﻲ اﻟ ﺪارات‬


‫اﻟﻤﻨﻄﻘﻴ ﺔ ‪ :‬اﻟﺘﺮآﻴﺒﻴ ﺔ ﻣﻨﻬ ﺎ أو اﻟﺘﺘﺎﺑﻌﻴ ﺔ ‪ .‬ﺑﻨ ﺎ ًء ﻋﻠ ﻰ ذﻟ ﻚ ‪ ،‬إذا أردﻧ ﺎ ﻓﺈﻧ ﻪ ﺑﺎﻹﻣﻜ ﺎن أن ﻳ ﺘﻢ ﺗﻨﺠﻴ ﺰ اﻟﻘﺴ ﻢ اﻟﻌﻠ ﻮي‬ ‫) اﻟﺘﺮآﻴﺒﻲ ( ﺑﺎﺳﺘﺨﺪام ﻣﻌﺎﻟﺠﺔ ‪. PROCESS‬‬ ‫إن اﻹﺷ ﺎرﺗﻴﻦ ‪ Clock‬و ‪ Reset‬ﺗﻈﻬ ﺮان ﺑﺸ ﻜﻞ ﻋ ﺎم ﻓ ﻲ ﻻﺋﺤ ﺔ اﻟﺤﺴﺎﺳ ﻴﺔ ﻟﻠﻤﻌﺎﻟﺠ ﺔ اﻟﺨﺎﺻ ﺔ ﺑﺎﻟﻘﺴ ﻢ اﻟﺴ ﻔﻠﻲ‬ ‫) اﻟﺘﺘ ﺎﺑﻌﻲ ( ‪ .‬ﻧ ﺬآﺮ هﻨ ﺎ أن اﻹﺷ ﺎرة ‪ Reset‬ﻻ ﺗﻮﺿ ﻊ ﻓ ﻲ ﻻﺋﺤ ﺔ اﻟﺤﺴﺎﺳ ﻴﺔ ﻋﻨ ﺪﻣﺎ ﻳﻜ ﻮن اﻟﺘﺼ ﻔﻴﺮ ﻣﺘﻮاﻗﺘ ًﺎ‬ ‫‪ Synchronous‬أو ﻋﻨﺪﻣﺎ ﻻ ﺗﻤﺘﻠﻚ اﻟﺪارة ﻣﺪﺧﻞ ﺗﺼﻔﻴﺮ ﺑﺎﻷﺳﺎس ‪ ،‬آﻤﺎ ﻧﺬآﺮ أﻧﻪ ﻋﻨ ﺪ اﺳ ﺘﺨﺪام اﻟﺘﻌﻠﻴﻤ ﺔ ‪WAIT‬‬ ‫ﻻ ﻣﻦ اﻟﺘﻌﻠﻴﻤﺔ ‪ IF‬داﺧﻞ اﻟﻤﻌﺎﻟﺠﺔ ﻓﺈن اﻟﻤﻌﺎﻟﺠﺔ ﻋﻨﺪهﺎ ﻻ ﺗﻤﺘﻠﻚ ﻻﺋﺤﺔ ﺣﺴﺎﺳﻴﺔ ﻋﻠﻰ اﻹﻃﻼق !!!‬ ‫ﺑﺪ ً‬ ‫ﻋﻨﺪ ﺗﻔﻌﻴﻞ اﻹﺷﺎرة ‪ Reset‬ﻓﺈن اﻹﺷﺎرة ‪ Pr_State‬ﺳﻮف ﺗﻌﻮد إﻟ ﻰ اﻟﺤﺎﻟ ﺔ اﻻﺑﺘﺪاﺋﻴ ﺔ ﻟﻠﻨﻈ ﺎم ‪System's Initial‬‬ ‫ﻼ ( ﺳﻮف ﺗﻘﻮم اﻟﻘﻼﺑﺎت ﺑﺘﺨ ﺰﻳﻦ اﻟﻘ ﻴﻢ‬ ‫‪ State‬و إﻻ ﻓﺈﻧﻪ وﻋﻨﺪ اﻟﺠﺒﻬﺔ اﻟﻔﻌﺎﻟﺔ ﻟﻨﺒﻀﺔ اﻟﺴﺎﻋﺔ ‪ ) Clock‬اﻟﺼﺎﻋﺪة ﻣﺜ ً‬ ‫اﻟﻤﻄﺒﻘﺔ ﻋﻠﻰ ﻣﺪاﺧﻠﻬﺎ واﻟﺘﻲ ﺗﻤﺜﻞ اﻹﺷﺎرة ‪ Nx_State‬اﻷﻣﺮ اﻟﺬي ﺳ ﻴﺆدي إﻟ ﻰ ﺗﺤ ﺪﻳﺚ ﻗ ﻴﻢ ﻣﺨ ﺎرج ه ﺬﻩ اﻟﻘﻼﺑ ﺎت‬ ‫واﻟﺘﻲ ﺗﻤﺜﻞ اﻹﺷﺎرة ‪ ) Pr_State‬ﻣﺨﺮج اﻟﻘﺴﻢ اﻟﺘﺘﺎﺑﻌﻲ ﻣﻦ اﻵﻟﺔ ( ‪.‬‬ ‫ﻣﻼﺣﻈ ﺔ هﺎﻣ ﺔ ﻣﺘﻌﻠﻘ ﺔ ﺑﺎﺳ ﺘﺨﺪام ﻣﻨﻬﺠﻴ ﺔ اﻟﺘﺼ ﻤﻴﻢ ﺑﻮاﺳ ﻄﺔ ﺁﻻت اﻟﺤﺎﻟ ﺔ اﻟﻤﻨﺘﻬﻴ ﺔ ‪ FSMs‬ﺗ ﺘﻠﺨﺺ ﻓ ﻲ أﻧ ﻪ وﻋﻠ ﻰ‬ ‫اﻟﺮﻏﻢ ﻣﻦ أن أﻳﺔ دارة ﺗﺘﺎﺑﻌﻴﺔ ﻳﻤﻜﻦ ﻣﻦ ﺣﻴ ﺚ اﻟﻤﺒ ﺪأ أن ﺗﻤﺜ ﻞ آﺂﻟ ﺔ ﺣﺎﻟ ﺔ ﻣﻨﺘﻬﻴ ﺔ إﻻ أن ذﻟ ﻚ ﻟ ﻴﺲ ﺑﺎﻟﻀ ﺮورة دوﻣ ًﺎ‬ ‫ﻣﻔﻴ ﺪًا أو ﻣﻮاﺗﻴ ًﺎ ‪ .‬إن اﻟﺴ ﺒﺐ ﻓ ﻲ ذﻟ ﻚ ﻳﻌ ﻮد إﻟ ﻰ أن اﻟﻜ ﻮد ﻳﻤﻜ ﻦ أن ﻳﺼ ﺒﺢ أﻃ ﻮل وأآﺜ ﺮ ﺗﻌﻘﻴ ﺪًا و أآﺜ ﺮ ﻋﺮﺿ ﺔ‬ ‫ﻟﻸﺧﻄ ﺎء ﻣﻘﺎرﻧ ﺔ ﻣ ﻊ ﺣﺎﻟ ﺔ اﺳ ﺘﺨﺪام اﻟﻤ ﻨﻬﺞ اﻟﺘﻘﻠﻴ ﺪي ‪ . Conventional Approach‬ه ﺬﻩ ه ﻲ اﻟﺤﺎﻟ ﺔ ﻏﺎﻟﺒ ًﺎ ﻣ ﻊ‬ ‫دارات اﻟﻤﺴ ﺠﻼت اﻟﺒﺴ ﻴﻄﺔ ‪ Simple Registered Circuits‬آﺎﻟﻌ ﺪادات ﻋﻠ ﻰ ﺳ ﺒﻴﻞ اﻟﻤﺜ ﺎل ‪ .‬آﻘﺎﻋ ﺪة ﺗﺠﺮﻳﺒﻴ ﺔ‬ ‫ﺑﺴﻴﻄﺔ ‪ Simple Rule Of Thumb‬ﻓﺈن ﻣﻨﻬﺠﻴﺔ اﺳﺘﺨﺪام ﺁﻻت اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ‪ FSM Approach‬ﻣﻔﻀ ﻠﺔ ﻓ ﻲ‬ ‫اﻷﻧﻈﻤﺔ اﻟﺘﻲ ﺗﺸﻜﻞ ﻣﻬﺎﻣﻬﺎ ﻻﺋﺤﺔ ﻣﺮﺗﺒﺔ ﺑﺸﻜﻞ ﺟﻴﺪ ﻣﻦ اﻟﺤ ﺎﻻت اﻟﺘ ﻲ ﻳﻤﻜ ﻦ ﺑﺴ ﻬﻮﻟﺔ ﺗﻌ ﺪادهﺎ ‪ .‬وﺑﺎﻟﺘ ﺎﻟﻲ ﻓﺈﻧ ﻪ أﺛﻨ ﺎء‬ ‫ﺗﻨﺠﻴﺰ ‪ Implementation‬ﺁﻟﺔ ﺣﺎﻟﺔ ﻧﻤﻮذﺟﻴﺔ ) ﻗﻴﺎﺳ ﻴﺔ ( ‪ Typical State Machine‬ﺳ ﻮف ﻧﺼ ﺎدف دوﻣ ًﺎ ﻓ ﻲ‬ ‫ﺑﺪاﻳﺔ اﻟﺒﻨﻴﺔ ‪ ARCHITECTURE‬ﻣﻦ آﻮد ‪ VHDL‬ﻧﻮع ﻣﻌﻄﻴﺎت ﻣﻌﺮف ﻣﻦ ﻗﺒﻞ اﻟﻤﺴﺘﺨﺪم ﻣﻦ اﻟﻨﻮع اﻟﻤﻌ ﺪود‬ ‫‪ User-Defined Enumerated Data Type‬ﺑﺤﻴﺚ ﻳﺘﻀﻤﻦ هﺬا اﻟﻨﻮع ﻣﻦ اﻟﻤﻌﻄﻴﺎت ) واﻟﺬي ﻏﺎﻟﺒًﺎ ﻣﺎ ﻳﻌﻄ ﻰ‬ ‫اﺳﻢ ‪ ( State‬ﻻﺋﺤﺔ ﺑﺄﺳﻤﺎء آﺎﻓﺔ اﻟﺤﺎﻻت اﻟﻤﻤﻜﻨﺔ ﻟﻠﻨﻈﺎم ‪ . All Possible System States‬اﻟﻤﺘﺤﻜﻤﺎت اﻟﺮﻗﻤﻴ ﺔ‬ ‫‪ Digital Controllers‬هﻲ أﻣﺜﻠﺔ ﺟﻴﺪة ﻋﻠﻰ دارات آﻬﺬﻩ ‪.‬‬ ‫ﻧﺎﺣﻴﺔ أﺧﺮى هﺎﻣﺔ ﺗﻢ اﻟﺘﺮآﻴ ﺰ ﻋﻠﻴﻬ ﺎ ﻣﺴ ﺒﻘًﺎ ﻓ ﻲ ﺑﺪاﻳ ﺔ اﻟﺠﻠﺴ ﺔ اﻟﺨﺎﻣﺴ ﺔ ﺗ ﺘﻠﺨﺺ ﻓ ﻲ أﻧ ﻪ ﻟﻴﺴ ﺖ آﺎﻓ ﺔ اﻟ ﺪارات اﻟﺘ ﻲ‬ ‫ﺗﻤﺘﻠ ﻚ ذواآ ﺮ ه ﻲ ﺑﺎﻟﻀ ﺮورة ﺗﺘﺎﺑﻌﻴ ﺔ ‪ .‬إن ذاآ ﺮة ﻣ ﻦ ﻧ ﻮع ‪ ( Read Only Memory ) ROM‬آ ﺎن ﻗ ﺪ ﺗ ﻢ‬ ‫إﻋﻄﺎؤهﺎ آﻤﺜ ﺎل ‪ .‬ﻓ ﻲ ه ﺬﻩ اﻟﺤﺎﻟ ﺔ ‪ ،‬ﻋﻤﻠﻴ ﺔ ﻗ ﺮاءة اﻟ ﺬاآﺮة ‪ Memory-Read Operation‬ﺗﻌﺘﻤ ﺪ ﻓﻘ ﻂ ﻋﻠ ﻰ ﻗﻴﻤ ﺔ‬ ‫ﺧﺎﻧﺎت اﻟﻌﻨﻮان اﻟﻤﻄﺒﻘﺔ ﺣﺎﻟﻴًﺎ ﻋﻠﻰ ﻣﻤﺮ اﻟﻌﻨﻮﻧﺔ ﻟﻠﺬاآﺮة ‪ ) ROM‬اﻟﺪﺧﻞ اﻟﺤﺎﻟﻲ ﻟﺪارة اﻟﺬاآﺮة ( وﺑﺎﻟﺘﺎﻟﻲ ﻓﺈن اﻟﻘﻴﻤ ﺔ‬ ‫اﻟﻤﻘ ﺮوءة ﻻ ﻋﻼﻗ ﺔ ﻟﻬ ﺎ ﺑﻌﻤﻠﻴ ﺎت اﻟﻮﻟ ﻮج اﻟﺴ ﺎﺑﻘﺔ إﻟ ﻰ اﻟ ﺬاآﺮة ‪ ) Previous Memory Accesses‬اﻟﻤ ﺪاﺧﻞ‬ ‫اﻟﺴﺎﺑﻘﺔ ( ‪ .‬ﻓﻲ ﺣﺎﻻت آﻬﺬﻩ ‪ ،‬ﻓﺈن ﻣﻨﻬﺠﻴﺔ اﺳﺘﺨﺪام ﺁﻻت اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ﻏﻴﺮ ﻣﺴﺘﺤﺴﻨﺔ ‪. Not Advisable‬‬ ‫‪ -٢-٨‬ﻣﻨﻬﺞ ﺗﺼﻤﻴﻤﻲ أول ‪Design Style # 1 :‬‬ ‫إن ﻃﺮﻗ ًﺎ أو ﻣﻨ ﺎهﺞ ﻣﺘﻌ ﺪدة ﻳﻤﻜ ﻦ أن ﺗﺆﺧ ﺬ ﺑﻌ ﻴﻦ اﻻﻋﺘﺒ ﺎر ﻟ ﺪى ﺗﺼ ﻤﻴﻢ ﺁﻟ ﺔ ﺣﺎﻟ ﺔ ﻣﻨﺘﻬﻴ ﺔ ‪ . FSM‬ﺳ ﻮف ﻧﺼ ﻒ‬ ‫ﻼ ﻟﻠﺘﻄﺒﻴ ﻖ ﺑﺴ ﻬﻮﻟﺔ ‪ .‬ﻓ ﻲ ه ﺬا اﻟﻤ ﻨﻬﺞ ‪ ،‬ﺗﻮﺻ ﻴﻒ اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ‬ ‫ﻼ ﺑﺸ ﻜﻞ ﺟﻴ ﺪ وﻗ ﺎﺑ ً‬ ‫ﺑﺎﻟﺘﻔﺼ ﻴﻞ ﻧﻤﻮذﺟ ًﺎ ﻣﻬ ﻴﻜ ً‬ ‫) اﻟﺘﺘﺎﺑﻌﻲ ( ﻵﻟﺔ اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴ ﺔ ) اﻟﻤﺒﻴﻨ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ ‪ ١-٨‬اﻟﺴ ﺎﺑﻖ ( ﻣﻔﺼ ﻮل ﺗﻤﺎﻣ ًﺎ ﻋ ﻦ ﺗﻮﺻ ﻴﻒ اﻟﻤﻘﻄ ﻊ اﻟﻌﻠ ﻮي‬ ‫) اﻟﺘﺮآﻴﺒﻲ ( ‪ .‬إن آﺎﻓﺔ ﺣ ﺎﻻت اﻵﻟ ﺔ ﻣﺼ ﺮح ﻋﻨﻬ ﺎ دوﻣ ًﺎ ﺑﺸ ﻜﻞ واﺿ ﺢ ﻣ ﻦ ﺧ ﻼل اﺳ ﺘﺨﺪام ﻧ ﻮع ﻣﻌﻄﻴ ﺎت ﻣﻌ ﺪود‬ ‫) ﻗﺎﺑﻞ ﻟﻠﻌﺪ ( ‪ . Enumerated Data Type‬ﺑﻌﺪ ﻋﺮض هﺬا اﻟﻤﻨﻬﺞ اﻟﺘﺼ ﻤﻴﻤﻲ ﺳ ﻮف ﻧﻘ ﻮم ﺑﺘﻔﺤﺼ ﻪ ﻣ ﻦ وﺟﻬ ﺔ‬ ‫ﻧﻈﺮ ﺗﺨﺰﻳﻦ اﻟﻤﻌﻄﻴ ﺎت ‪ Data Storage Perspective‬وذﻟ ﻚ ﺑﻬ ﺪف ﻓﻬﻤ ﻪ ﺑﺸ ﻜﻞ أﻓﻀ ﻞ وﺟﻌ ﻞ ﺑﻨﻴﺘ ﻪ أآﺜ ﺮ دﻗ ﺔ‬ ‫اﻷﻣﺮ اﻟﺬي ﺳﻴﻘﻮدﻧﺎ إﻟﻰ اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ ‪. Design Style # 2‬‬ ‫أ‪ -‬ﺗﺼﻤﻴﻢ اﻟﻤﻘﻄﻊ اﻟﺴﻔﻠﻲ ) اﻟﺘﺘﺎﺑﻌﻲ ( ‪Design Of The Lower ( Sequential ) Section :‬‬ ‫ﻓﻲ اﻟﺸ ﻜﻞ )‪ (١-٨‬اﻟﺴ ﺎﺑﻖ ﺗﻮﺟ ﺪ اﻟﻘﻼﺑ ﺎت ‪ Flip-Flops‬ﻓ ﻲ اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ وﺑﺎﻟﺘ ﺎﻟﻲ ﻓ ﺈن ﻣ ﺪﺧﻞ ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ‬ ‫‪ Clock‬وﻣﺪﺧﻞ اﻟﺘﺼﻔﻴﺮ ) إﻋﺎدة اﻟﺘﻮﺿﻊ ( ‪ Reset‬ﻣﻮﺻﻮﻻن إﻟ ﻰ ه ﺬا اﻟﻤﻘﻄ ﻊ ‪ .‬اﻟﻤ ﺪﺧﻞ اﻵﺧ ﺮ ﻟﻠﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ‬ ‫ه ﻮ اﻹﺷ ﺎرة ‪ ) Nx_State‬اﻟﺤﺎﻟ ﺔ اﻟﺘﺎﻟﻴ ﺔ ( ﻓ ﻲ ﺣ ﻴﻦ أن اﻟﻤﺨ ﺮج اﻟﻮﺣﻴ ﺪ ﻟﻬ ﺬا اﻟﻤﻘﻄ ﻊ ه ﻮ اﻹﺷ ﺎرة ‪Pr_State‬‬ ‫) اﻟﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ ( ‪ .‬ﺑﺎﻋﺘﺒ ﺎر أن دارة اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ ه ﻲ ﺗﺘﺎﺑﻌﻴ ﺔ ﻓ ﺈن ﻣﻌﺎﻟﺠ ﺔ ‪ PROCESS‬ﺿ ﺮورﻳﺔ هﻨ ﺎ ﺣﺘﻤ ًﺎ‬


‫واﻟﺘﻲ ﻳﻤﻜﻦ داﺧﻠﻬﺎ اﺳ ﺘﺨﺪام أﻳ ﺔ ﺗﻌﻠﻴﻤ ﺔ ﺗﺘﺎﺑﻌﻴ ﺔ ﻣ ﻦ اﻟﺘﻌﻠﻴﻤ ﺎت اﻟﺘ ﻲ ﺳ ﺒﻖ ﻟﻨ ﺎ دراﺳ ﺘﻬﺎ ﻓ ﻲ اﻟﺠﻠﺴ ﺔ اﻟﺴﺎدﺳ ﺔ ) ﻣﺜ ﻞ‬ ‫اﻟﺘﻌﻠﻴﻤﺎت ‪ IF‬و ‪ WAIT‬و ‪ CASE‬و ‪. ( LOOP‬‬ ‫ﻓﻴﻤﺎ ﻳﻠﻲ ﻗﺎﻟﺐ ﺗﺼﻤﻴﻢ ﻧﻤﻮذﺟﻲ ‪ Typical Design Template‬ﻣﻦ أﺟﻞ اﻟﻤﻘﻄﻊ اﻟﺴﻔﻠﻲ ) اﻟﺘﺘﺎﺑﻌﻲ ( ‪:‬‬ ‫) ‪PROCESS ( reset, clock‬‬ ‫‪BEGIN‬‬ ‫‪IF ( reset = '1' ) THEN‬‬ ‫;‪pr_state <= state0‬‬ ‫‪ELSIF ( clock'EVENT AND clock = '1' ) THEN‬‬ ‫;‪pr_state <= nx_state‬‬ ‫;‪END IF‬‬ ‫;‪END PROCESS‬‬ ‫اﻟﻜﻮد اﻟﻤﻌﺮوض أﻋﻼﻩ ﺑﺴﻴﻂ ﻟﻠﻐﺎﻳﺔ ‪ .‬إﻧﻪ ﻳﺘﻜﻮن ﻣﻦ ﺗﺼﻔﻴﺮ ﻏﻴﺮ ﻣﺘﻮاﻗﺖ ‪ Asynchronous Reset‬واﻟ ﺬي ﻳﺤ ﺪد‬ ‫اﻟﺤﺎﻟ ﺔ اﻻﺑﺘﺪاﺋﻴ ﺔ ﻟﻠﻨﻈ ﺎم ) ‪ ( state0‬ﻣﺘﺒﻮﻋ ًﺎ ﺑﺘﺨ ﺰﻳﻦ ﻣﺘﻮاﻗ ﺖ ‪ Synchronous Storage‬ﻟﻺﺷ ﺎرة ‪nx_state‬‬ ‫) ﻋﻨﺪ اﻻﻧﺘﻘﺎل اﻟﻤﻮﺟﺐ ‪ -‬اﻟﺠﺒﻬﺔ اﻟﺼﺎﻋﺪة ‪ -‬ﻹﺷﺎرة ﻧﺒﻀﺔ اﻟﺴﺎﻋﺔ ‪ ( clock‬واﻟﺬي ﺳﻮف ﻳﻨﺘﺞ اﻹﺷ ﺎرة ‪pr_state‬‬ ‫ﻋﻨﺪ ﻣﺨﺮج اﻟﻤﻘﻄﻊ اﻟﺴﻔﻠﻲ ) اﻧﻈﺮ اﻟﺸﻜﻞ ‪ . ( ١-٨‬ﻧﻘﻄﺔ ﺟﻴﺪة ﺗﺘﻌﻠﻖ ﺑﻬﺬا اﻟﻤﻨﻬﺞ ﻣﻔﺎدهﺎ أن ﺗﺼ ﻤﻴﻢ اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ‬ ‫ﻣﻌﻴﺎري ﺑﺸﻜﻞ أﺳﺎﺳﻲ ‪. Basically Standard‬‬ ‫ﻣﻴ ﺰة أﺧ ﺮى ﻟﻬ ﺬا اﻟﻨﻤ ﻮذج اﻟﺘﺼ ﻤﻴﻤﻲ ﺗ ﺘﻠﺨﺺ ﻓ ﻲ أن ﻋ ﺪد اﻟﻤﺴ ﺠﻼت ) اﻟﻘﻼﺑ ﺎت ( اﻟﻼزﻣ ﺔ ه ﻮ أﺻ ﻐﺮي ‪ .‬ﻓ ﻲ‬ ‫اﻟﺠﻠﺴﺔ اﻟﺴ ﺎﺑﻘﺔ ) اﻟﺠﻠﺴ ﺔ اﻟﺴ ﺎﺑﻌﺔ ( رأﻳﻨ ﺎ أن ﻋ ﺪد اﻟﻘﻼﺑ ﺎت اﻟﻤﺴ ﺘﻨﺒﻄﺔ ﻣ ﻦ اﻟﻜ ﻮد أﻋ ﻼﻩ ﻣ ﻦ ﻗﺒ ﻞ اﻟﻤﺘ ﺮﺟﻢ ﻳﺴ ﺎوي‬ ‫ﺑﺒﺴﺎﻃﺔ ﻋﺪد اﻟﺨﺎﻧ ﺎت اﻟﻼزﻣ ﺔ ﻟﺘﺮﻣﻴ ﺰ آﺎﻓ ﺔ اﻟﺤ ﺎﻻت ﻵﻟ ﺔ اﻟﺤﺎﻟ ﺔ اﻟﻤﻨﺘﻬﻴ ﺔ ‪ ) FSM‬ﻷن اﻹﺷ ﺎرة اﻟﻮﺣﻴ ﺪة اﻟﺘ ﻲ ﻳ ﺘﻢ‬ ‫إﺳﻨﺎد ﻗﻴﻤﺔ إﻟﻴﻬﺎ ﻋﻨﺪ اﻻﻧﺘﻘﺎل ﻓﻲ ﻗﻴﻤﺔ إﺷﺎرة أﺧﺮى ‪ -‬وهﻲ اﻹﺷﺎرة ‪ clock‬ﻓﻲ ﺣﺎﻟﺘﻨﺎ ‪ -‬هﻲ اﻹﺷﺎرة ‪. ( pr_state‬‬ ‫وﺑﺎﻟﺘﺎﻟﻲ ﻓﺈذا ﺗﻢ اﺳﺘﺨﺪام ﻧﻤﻮذج اﻟﺘﺮﻣﻴ ﺰ اﻟﺜﻨ ﺎﺋﻲ اﻻﻓﺘﺮاﺿ ﻲ ‪ Default Binary Encoding Style‬ﻓﺈﻧ ﻪ ﺳ ﻴﻠﺰم‬ ‫ﻓﻘﻂ ﻋﺪد ﻣﻦ اﻟﻘﻼﺑﺎت ﻣﺴﺎ ٍو ﻟﻠﻘﻴﻤﺔ ‪ log2n‬ﺣﻴﺚ أن ‪ n‬هﻲ ﻋ ﺪد اﻟﺤ ﺎﻻت ﻓ ﻲ اﻷوﺗﻮﻣ ﺎت ‪Number Of States‬‬ ‫‪. In The FSM‬‬ ‫ب ‪ -‬ﺗﺼﻤﻴﻢ اﻟﻤﻘﻄﻊ اﻟﻌﻠﻮي ) اﻟﺘﺮآﻴﺒﻲ ( ‪Design Of The Upper ( Combinational ) Section :‬‬ ‫ﻓﻲ اﻟﺸﻜﻞ )‪ (١-٨‬اﻟﺴﺎﺑﻖ ﻓﺈن اﻟﻤﻘﻄﻊ اﻟﻌﻠﻮي هﻮ ﺗﺮآﻴﺒﻲ ﺑﺸﻜﻞ آﻠﻲ وﺑﺎﻟﺘﺎﻟﻲ ﻓﺈن اﻟﻜﻮد اﻟ ﺬي ﺳﻴﻮﺻ ﻔﻪ ﻻ ﻳﻠ ﺰم أن‬ ‫ﻳﻜﻮن ﺗﺘﺎﺑﻌﻴًﺎ ‪ .‬إن آﻮدًا ﺗﺰاﻣﻨﻴًﺎ ﻳﻤﻜﻦ أن ﻳﺴﺘﺨﺪم هﻨﺎ ﺑﺸﻜﻞ ﺻﺤﻴﺢ ﺗﻤﺎﻣًﺎ ‪ .‬ﻣﻊ ذﻟﻚ ‪ ،‬ﻓﻲ ﻗﺎﻟﺐ اﻟﺘﺼ ﻤﻴﻢ اﻟﻤﻌ ﺮوض‬ ‫ﻓﻴﻤﺎ ﻳﻠﻲ ﻓﺈن آﻮدًا ﺗﺘﺎﺑﻌﻴًﺎ ﻗﺪ ﺗﻢ اﺳﺘﺨﺪاﻣﻪ ﻣﻊ اﺧﺘﻴﺎر اﻟﺘﻌﻠﻴﻤﺔ ‪ CASE‬ﻟﺘﻠﻌﺐ اﻟﺪور اﻟﻤﺮآﺰي ﻓﻴﻪ ‪ .‬ﻓﻲ هﺬﻩ اﻟﺤﺎﻟﺔ ‪،‬‬ ‫ﻳﺠﺐ ﺗﺬآﺮ و ﻣﺮاﻋﺎة آﻞ ﻣﻦ اﻟﻘﺎﻋﺪﺗﻴﻦ )‪ (١‬و )‪ (٢‬اﻟﻠﺘﻴﻦ ﻋﺮﺿﺘﺎ ﻓﻲ اﻟﻤﻘﻄﻊ )‪ (١٠-٦‬ﻣﻦ اﻟﺠﻠﺴﺔ اﻟﺴﺎدﺳﺔ ‪.‬‬ ‫) ‪PROCESS ( input, pr_state‬‬ ‫‪BEGIN‬‬ ‫‪CASE pr_state IS‬‬ ‫>= ‪WHEN state0‬‬ ‫‪IF ( input = ... ) THEN‬‬ ‫;> ‪output <= < value‬‬ ‫;‪nx_state <= state1‬‬ ‫‪ELSE ...‬‬ ‫;‪END IF‬‬ ‫>= ‪WHEN state1‬‬ ‫‪IF ( input = ... ) THEN‬‬


‫;> ‪output <= < value‬‬ ‫;‪nx_state <= state2‬‬ ‫‪ELSE ...‬‬ ‫;‪END IF‬‬ ‫>= ‪WHEN state2‬‬ ‫‪IF ( input = ... ) THEN‬‬ ‫;> ‪output <= < value‬‬ ‫;‪nx_state <= state2‬‬ ‫‪ELSE ...‬‬ ‫;‪END IF‬‬ ‫‪...‬‬ ‫;‪END CASE‬‬ ‫;‪END PROCESS‬‬ ‫آﻤﺎ هﻮ واﺿﺢ ﻟﻠﻌﻴﺎن ﻓﺈن هﺬا اﻟﻜﻮد أﻳﻀًﺎ ﺑﺴﻴﻂ ﻟﻠﻐﺎﻳﺔ وهﻮ ﻳﻘﻮم ﺑﺄﻣﺮﻳﻦ اﺛﻨﻴﻦ ‪:‬‬ ‫ﺁ‪ -‬إﺳﻨﺎد اﻟﻘﻴﻤﺔ اﻟﻤﻨﺎﺳﺒﺔ إﻟﻰ اﻟﻤﺨﺮج ‪. Output Value‬‬ ‫ب‪ -‬ﺗﺠﻬﻴﺰ ﻗﻴﻤﺔ اﻟﺤﺎﻟﺔ اﻟﺘﺎﻟﻴﺔ ‪. Next State‬‬ ‫ﻧﻨ ﻮﻩ هﻨ ﺎ أﻳﻀ ًﺎ إﻟ ﻰ أن ه ﺬا اﻟﻜ ﻮد ﻳﺨﻀ ﻊ ﻟﻠﻘﺎﻋ ﺪﺗﻴﻦ )‪ (١‬و )‪ (٢‬اﻟﻤﻌﺮوﺿ ﺘﺎن ﻓ ﻲ اﻟﻤﻘﻄ ﻊ )‪ (١٠-٦‬ﻣ ﻦ اﻟﺠﻠﺴ ﺔ‬ ‫اﻟﺴﺎدﺳﺔ واﻟﻠﺘﺎن ﺗﺘﻌﻠﻘﺎن ﺑﺘﺼﻤﻴﻢ اﻟﺪارات اﻟﺘﺮآﻴﺒﻴﺔ ﺑﺎﺳﺘﺨﺪام اﻟﺘﻌﻠﻴﻤﺎت اﻟﺘﺘﺎﺑﻌﻴﺔ وذﻟﻚ ﻷن آﺎﻓﺔ إﺷﺎرات اﻟﺪﺧﻞ هﻲ‬ ‫ﻣﻮﺟ ﻮدة ﻓ ﻲ ﻻﺋﺤ ﺔ اﻟﺤﺴﺎﺳ ﻴﺔ ﻟﻠﻤﻌﺎﻟﺠ ﺔ آﻤ ﺎ أن آﺎﻓ ﺔ ﺗﺮآﻴﺒ ﺎت اﻟ ﺪﺧﻞ ‪ /‬اﻟﺨ ﺮج ﻣﺤ ﺪدة ) ﻣﻌﺎﻟﺠ ﺔ ﺿ ﻤﻦ اﻟ ـ‬ ‫‪ . All Input / Output Combinations Are Specified ( PROCESS‬أﺧﻴﺮًا ‪ ،‬ﻧﻼﺣﻆ أﻧ ﻪ ﻻ ﺗﻮﺟ ﺪ هﻨ ﺎ‬ ‫ﻋﻤﻠﻴﺎت إﺳﻨﺎد ﻗﻴﻢ إﻟﻰ إﺷ ﺎرة ﻣ ﺎ ﻋﻨ ﺪ اﻻﻧﺘﻘ ﺎل ﻓ ﻲ ﻗﻴﻤ ﺔ إﺷ ﺎرة أﺧ ﺮى وﺑﺎﻟﺘ ﺎﻟﻲ ﻓﻠ ﻦ ﻳ ﺘﻢ ﺣﺠ ﺰ أﻳ ﺔ ﻗﻼﺑ ﺎت ﻣ ﻦ ﻗﺒ ﻞ‬ ‫اﻟﻤﺘﺮﺟﻢ ‪.‬‬ ‫ﻗﺎﻟﺐ ﺁﻟﺔ اﻟﺤﺎﻟﺔ ﻣﻦ أﺟﻞ اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻷول ‪State Machine Template For Design Style # 1 :‬‬ ‫ﻓﻴﻤﺎ ﻳﻠ ﻲ ﺗ ﻢ ﻋ ﺮض ﻗﺎﻟ ﺐ آﺎﻣ ﻞ ﻣ ﻦ أﺟ ﻞ ﻧﻤ ﻮذج ﺗﺼ ﻤﻴﻤﻲ ﻵﻟ ﺔ ﺣﺎﻟ ﺔ ﻣﻨﺘﻬﻴ ﺔ ‪ .‬ﻳﻤﻜ ﻦ ﻣﻼﺣﻈ ﺔ أﻧ ﻪ ﺑﺎﻹﺿ ﺎﻓﺔ إﻟ ﻰ‬ ‫اﻟﻤﻌﺎﻟﺠﺘﻴﻦ اﻟﻤﻌﺮوﺿﺘﻴﻦ ﺳﺎﺑﻘًﺎ أﻋﻼﻩ ﻓﺈن هﺬا اﻟﻘﺎﻟﺐ ﻳﺘﻀﻤﻦ أﻳﻀًﺎ ﻧﻮع ﻣﻌﻄﻴﺎت ﻣﻦ اﻟﻨﻮع اﻟﻤﻌﺪود واﻟﻤﻌ ﺮف ﻣ ﻦ‬ ‫ﻗﺒﻞ اﻟﻤﺴﺘﺨﺪم ) واﻟﺬي ﺳﻤﻲ هﻨﺎ ﺑﺎﺳ ﻢ ‪ . User-Defined Enumerated Data Type ( state‬ه ﺬا اﻟﻨ ﻮع ﻣ ﻦ‬ ‫اﻟﻤﻌﻄﻴﺎت ﻳﻤﻜﻦ أن ﻳﺄﺧﺬ أﻳﺔ ﻗﻴﻤﺔ ﻣﻮﺟﻮدة ﺿﻤﻦ ﻻﺋﺤﺔ اﻟﺤ ﺎﻻت اﻟﺘ ﻲ ﺗﻤﺜ ﻞ اﻟﺤ ﺎﻻت اﻟﻤﻤﻜﻨ ﺔ ﻵﻟ ﺔ اﻟﺤﺎﻟ ﺔ اﻟﻤﻨﺘﻬﻴ ﺔ‬ ‫‪. FSM‬‬ ‫;‪LIBRARY ieee‬‬ ‫;‪USE ieee.std_logic_1164.all‬‬ ‫‪--------------------------------------------------------------------------------------------------‬‬‫‪ENTITY < entity_name > IS‬‬ ‫;> ‪PORT ( input : IN < data_type‬‬ ‫;‪reset, clock : IN STD_LOGIC‬‬ ‫;) > ‪output : OUT < data_type‬‬ ‫;> ‪END < entity_name‬‬ ‫‪--------------------------------------------------------------------------------------------------‬‬‫‪ARCHITECTURE < arch_name > OF < entity_name > IS‬‬ ‫;) ‪TYPE state IS ( state0, state1, state2, state3, ...‬‬ ‫;‪SIGNAL pr_state, nx_state : state‬‬ ‫‪BEGIN‬‬


------------------------------- Lower section : --------------------------PROCESS ( reset, clock ) BEGIN IF ( reset= '1' ) THEN pr_state <= state0; ELSIF ( clock'EVENT AND clock = '1' ) THEN pr_state <= nx_state; END IF; END PROCESS; ------------------------------ Upper section : ----------------------------PROCESS ( input, pr_state ) BEGIN CASE pr_state IS WHEN state0 => IF ( input = ... ) THEN output <= < value >; nx_state <= state1; ELSE ... END IF; WHEN state1 => IF ( input = ... ) THEN output <= < value >; nx_state <= state2; ELSE ... END IF; WHEN state2 => IF ( input = ... ) THEN output <= < value >; nx_state <= state3; ELSE ... END IF; ... END CASE; END PROCESS; END < arch_name >; --------------------------------------------------------------------------------------------------BCD Counter ‫ ﻋﺪاد ﻋﺸﺮي ﻣﺮﻣﺰ ﺛﻨﺎﺋﻴًﺎ‬: (١-٨) ‫اﻟﻤﺜﺎل‬ . ( ‫ وذﻟﻚ ﻷن ﻣﺨﺮﺟﻪ ﻳﻌﺘﻤﺪ ﻓﻘ ﻂ ﻋﻠ ﻰ اﻟﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ ) اﻟﻤﺨﺰﻧ ﺔ‬Moore Machine ‫اﻟﻌﺪاد هﻮ ﻣﺜﺎل ﻋﻦ ﺁﻟﺔ ﻣﻮر‬ ِ ‫ وآﻤﺴﻠ‬Simple Registered Circuit ‫آ ﺪارة ﻣﺴ ﺠﻠﻴﺔ ﺑﺴ ﻴﻄﺔ‬ ‫ ﻓ ﺈن اﻟﻌ ﺪاد ﻳﻤﻜ ﻦ أن ﻳﻨﺠ ﺰ‬Sequencer ‫ﺴ ﻞ‬ ‫ ) آﻤﺎ ﺳﺒﻖ أن رأﻳﻨﺎ ﻓ ﻲ اﻟﺠﻠﺴ ﺎت اﻟﺴ ﺎﺑﻘﺔ ( أو ﻣ ﻦ‬Conventional ‫ اﻟﺘﻘﻠﻴﺪي‬: ‫ﺑﺴﻬﻮﻟﺔ ﺑﻮاﺳﻄﺔ آﻞ ﻣﻦ اﻟﻤﻨﻬﺠﻴﻦ‬ ‫ ( ﺗﻜﻤ ﻦ ﻓ ﻲ أﻧ ﻪ ﻋﻨ ﺪﻣﺎ ﻳﻜ ﻮن ﻋ ﺪد‬FSM ‫ إن اﻟﻤﺸ ﻜﻠﺔ ﻓ ﻲ اﻟﺤﺎﻟ ﺔ اﻟﺜﺎﻧﻴ ﺔ ) ﺣﺎﻟ ﺔ اﺳ ﺘﺨﺪام ﻣﻨﻬﺠﻴ ﺔ‬. FSM ‫اﻟﻨ ﻮع‬ ‫ هﺬﻩ اﻟﻤﺸﻜﻠﺔ ﻳﻤﻜ ﻦ ﺗﺠﺎوزه ﺎ ﺑﺴ ﻬﻮﻟﺔ ﺑﺎﺳ ﺘﺨﺪام‬. Cumbersome ‫اﻟﺤﺎﻻت آﺒﻴﺮًا ﻓﺈن ﺗﻌﺪادهﺎ آﻠﻬﺎ ﻳﺼﺒﺢ ﻣﺰﻋﺠًﺎ‬ . ( ‫ ﻓﻲ اﻟﻤﻨﻬﺞ اﻟﺘﻘﻠﻴﺪي ) اﻟﻄﺮﻳﻘﺔ اﻟﺘﻘﻠﻴﺪﻳﺔ ﻟﺘﻨﺠﻴﺰ اﻟﻌﺪادات‬LOOP ‫اﻟﺘﻌﻠﻴﻤﺔ‬


‫ﻣﺨﻄﻂ اﻟﺤﺎﻻت ﻟﻌﺪاد داﺋﺮي ‪ Circular Counter‬ﻳﻌﺪ ﻣﻦ ‪ 0‬إﻟﻰ ‪ 9‬وﻳﻜﺮر دورة اﻟﻌﺪ ﺑﺎﺳﺘﻤﺮار ﻣﺒﻴﻦ ﻓﻲ اﻟﺸ ﻜﻞ‬ ‫)‪ . (٢-٨‬ﺗﻢ ﺗﺴﻤﻴﺔ اﻟﺤﺎﻻت ‪ Zero, One , Two, …. , Nine‬ﺑﺤﻴ ﺚ أن آ ﻞ اﺳ ﻢ ﻳﻮاﻓ ﻖ اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ﻟﺨ ﺮج‬ ‫اﻟﻌﺪاد ‪.‬‬

‫اﻟﺸﻜﻞ )‪ : (٢-٨‬ﻣﺨﻄﻂ اﻟﺤﺎﻻت ﻟﻌﺪاد اﻟﻤﺜﺎل )‪(١-٨‬‬ ‫آﻮد ‪ VHDL‬ﻣﺸﺎﺑﻪ ﺗﻤﺎﻣًﺎ ﻟﻘﺎﻟﺐ اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻷول اﻟﺬي ﺳﺒﻖ ﻋﺮﺿﻪ ﻣﺒﻴﻦ ﻓﻴﻤ ﺎ ﻳﻠ ﻲ ‪ .‬ﻧ ﻮع ﻣﻌﻄﻴ ﺎت ﻣ ﻦ‬ ‫اﻟﻨ ﻮع اﻟﻤﻌ ﺪود ) ‪ ( state‬ﻳﻈﻬ ﺮ ﻓ ﻲ اﻟﺴ ﻄﺮﻳﻦ ) ‪ . ( 11 - 12‬ﺗﺼ ﻤﻴﻢ اﻟﻤﻘﻄ ﻊ اﻟﺴ ﻔﻠﻲ اﻟﺘﺘ ﺎﺑﻌﻲ ) اﻟﻤﻨﺒ ﻮض‬ ‫‪ ( Clocked‬ﻣﺒ ﻴﻦ ﻓ ﻲ اﻷﺳ ﻄﺮ اﻟﻤﻜﻮﻧ ﺔ ﻟﻠﻤﻌﺎﻟﺠ ﺔ اﻷوﻟ ﻰ ) ‪ ( 16 - 23‬ﻓ ﻲ ﺣ ﻴﻦ أن ﺗﺼ ﻤﻴﻢ اﻟﻤﻘﻄ ﻊ اﻟﻌﻠ ﻮي‬ ‫اﻟﺘﺮآﻴﺒﻲ ﻣﺒﻴﻦ ﻓﻲ اﻷﺳﻄﺮ اﻟﻤﻜﻮﻧﺔ ﻟﻠﻤﻌﺎﻟﺠﺔ اﻟﺜﺎﻧﻴ ﺔ ) ‪ . ( 25 -59‬ﻓ ﻲ ه ﺬا اﻟﻤﺜ ﺎل ‪ ،‬ﻋ ﺪد اﻟﻤﺴ ﺠﻼت ) اﻟﻘﻼﺑ ﺎت (‬ ‫ﻳﺴﺎوي ‪ 4‬وهﻲ ﻗﻴﻤﺔ اﻟﻠﻮﻏﺎرﻳﺘﻢ اﻟﺜﻨﺎﺋﻲ ﻟﻠﻌﺪد ‪ ) 10‬ﻋﺪد اﻟﺤﺎﻻت ﻓﻲ اﻟﻤﺨﻄﻂ اﻟﻤﻮﺿﺢ ﻓﻲ اﻟﺸﻜﻞ ‪. ( ٢-٨‬‬ ‫ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻣﻮﺿﺤﺔ ﻓﻲ اﻟﺸﻜﻞ )‪ . (٣-٨‬آﻤﺎ هﻮ واﺿﺢ ﻟﻠﻌﻴ ﺎن ﻓ ﺈن ﻣﺨ ﺮج اﻟﻌ ﺪاد ‪ count‬ﻳﺘﺰاﻳ ﺪ ﻣ ﻦ اﻟﻘﻴﻤ ﺔ ‪0‬‬ ‫إﻟﻰ اﻟﻘﻴﻤﺔ ‪ 9‬وﻣﻦ ﺛﻢ ﻳﻌﻮد إﻟﻰ اﻟﺼﻔﺮ ﻟﺒﺪء دورة ﻋﺪ ﺟﺪﻳﺪة ﻣﺮة أﺧﺮى ‪.‬‬

‫اﻟﺸﻜﻞ )‪ : (٣-٨‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل )‪(١-٨‬‬ ‫‪1 ------------------------------------------------------------------------------------------------‬‬‫;‪2 LIBRARY ieee‬‬ ‫;‪3 USE ieee.std_logic_1164.all‬‬ ‫‪4 ------------------------------------------------------------------------------------------------‬‬‫‪5 ENTITY counter IS‬‬ ‫‪6‬‬ ‫;‪PORT ( clk, rst : IN STD_LOGIC‬‬ ‫‪7‬‬ ‫;)) ‪count : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0‬‬ ‫;‪8 END counter‬‬ ‫‪9 -------------------------------------------------------------------------------------------------‬‬


10 ARCHITECTURE state_machine OF counter IS 11 TYPE state IS ( zero, one, two, three, four, 12 five, six, seven, eight, nine ); 13 SIGNAL pr_state, nx_state : state; 14 BEGIN 15 ------------------------------- Lower section : --------------------------------------16 PROCESS ( rst, clk ) 17 BEGIN 18 IF ( rst = '1' ) THEN 19 pr_state <= zero; 20 ELSIF ( clk'EVENT AND clk = '1' ) THEN 21 pr_state <= nx_state; 22 END IF; 23 END PROCESS; 24 --------------------------------- Upper section : ------------------------------------25 PROCESS ( pr_state ) 26 BEGIN 27 CASE pr_state IS 28 WHEN zero => 29 count <= "0000"; 30 nx_state <= one; 31 WHEN one => 32 count <= "0001"; 33 nx_state <= two; 34 WHEN two => 35 count <= "0010"; 36 nx_state <= three; 37 WHEN three => 38 count <= "0011"; 39 nx_state <= four; 40 WHEN four => 41 count <= "0100"; 42 nx_state <= five; 43 WHEN five => 44 count <= "0101"; 45 nx_state <= six; 46 WHEN six => 47 count <= "0110"; 48 nx_state <= seven; 49 WHEN seven => 50 count <= "0111"; 51 nx_state <= eight; 52 WHEN eight => 53 count <= "1000"; 54 nx_state <= nine;


‫‪55‬‬ ‫>= ‪WHEN nine‬‬ ‫‪56‬‬ ‫;"‪count <= "1001‬‬ ‫‪57‬‬ ‫;‪nx_state <= zero‬‬ ‫‪58‬‬ ‫;‪END CASE‬‬ ‫‪59‬‬ ‫;‪END PROCESS‬‬ ‫;‪60 END state_machine‬‬ ‫‪61 -----------------------------------------------------------------------------------------------‬‬‫اﻟﻤﺜﺎل )‪ : (٢-٨‬ﺁﻟﺔ ﺣﺎﻟﺔ ﻣﻨﺘﻬﻴﺔ ﺑﺴﻴﻄﺔ )‪Simple FSM # 1 (١‬‬ ‫ﻳﺒﻴﻦ اﻟﺸﻜﻞ )‪ (٤-٨‬ﻣﺨﻄﻂ اﻟﺤﺎﻻت ﻵﻟﺔ ﺣﺎﻟﺔ ﻣﻨﺘﻬﻴ ﺔ ﺑﺴ ﻴﻄﺔ ﺟ ﺪًا ‪ .‬ﻳﻤﺘﻠ ﻚ اﻟﻨﻈ ﺎم ﺣ ﺎﻟﺘﻴﻦ هﻤ ﺎ ‪ stateA‬و ‪stateB‬‬ ‫وﻳﺘﻮﺟ ﺐ ﻋﻠﻴ ﻪ اﻻﻧﺘﻘ ﺎل ﻣ ﻦ إﺣ ﺪاهﺎ إﻟ ﻰ اﻷﺧ ﺮى ﻓ ﻲ آ ﻞ ﻣ ﺮة ﻳ ﺘﻢ ﻓﻴﻬ ﺎ اﺳ ﺘﻘﺒﺎل اﻟﻘﻴﻤ ﺔ '‪ d = '1‬ﻋﻠ ﻰ اﻟﻤ ﺪﺧﻞ ‪. d‬‬ ‫اﻟﺨ ﺮج اﻟﻤﻄﻠ ﻮب ه ﻮ ‪ x = a‬ﻋﻨ ﺪﻣﺎ ﺗﻜ ﻮن اﻵﻟ ﺔ ﻓ ﻲ اﻟﺤﺎﻟ ﺔ ‪ stateA‬أو ‪ x = b‬ﻋﻨ ﺪﻣﺎ ﺗﻜ ﻮن اﻵﻟ ﺔ ﻓ ﻲ اﻟﺤﺎﻟ ﺔ‬ ‫ﻼ ( هﻲ اﻟﺤﺎﻟﺔ ‪. stateA‬‬ ‫‪ . stateB‬اﻟﺤﺎﻟﺔ اﻻﺑﺘﺪاﺋﻴﺔ ) ﻋﻨﺪ اﻟﺘﺼﻔﻴﺮ ‪ Reset‬ﻣﺜ ً‬

‫اﻟﺸﻜﻞ )‪ : (٤-٨‬ﺁﻟﺔ اﻟﺤﺎﻟﺔ اﻟﻤﻨﺘﻬﻴﺔ ﻟﻠﻤﺜﺎل )‪(٢-٨‬‬ ‫ﻓﻴﻤﺎ ﻳﻠﻲ آﻮد ‪ VHDL‬ﻟﻬﺬﻩ اﻟﺪارة ﺣﻴﺚ ﺗﻢ ﻓﻴﻪ اﺳﺘﺨﺪام اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ رﻗﻢ )‪ (١‬اﻟﺬي ﺳ ﺒﻖ ﻋﺮﺿ ﻪ ﻓ ﻲ ﺑﺪاﻳ ﺔ‬ ‫اﻟﺠﻠﺴﺔ ‪.‬‬ ‫‪1 ------------------------------------------------------------------------------------------------‬‬‫‪2 ENTITY simple_fsm IS‬‬ ‫‪3‬‬ ‫;‪PORT ( a, b, d, clk, rst : IN BIT‬‬ ‫‪4‬‬ ‫;) ‪x : OUT BIT‬‬ ‫;‪5 END simple_fsm‬‬ ‫‪6 ------------------------------------------------------------------------------------------------‬‬‫‪7 ARCHITECTURE simple_fsm OF simple_fsm IS‬‬ ‫‪8‬‬ ‫;) ‪TYPE state IS ( stateA, stateB‬‬ ‫‪9‬‬ ‫;‪SIGNAL pr_state, nx_state : state‬‬ ‫‪10 BEGIN‬‬ ‫‪11‬‬ ‫‪----------------------------- Lower section : ----------------------------‬‬‫‪12‬‬ ‫) ‪PROCESS ( rst, clk‬‬ ‫‪13‬‬ ‫‪BEGIN‬‬ ‫‪14‬‬ ‫‪IF ( rst = '1' ) THEN‬‬ ‫‪15‬‬ ‫;‪pr_state <= stateA‬‬ ‫‪16‬‬ ‫‪ELSIF ( clk'EVENT AND clk = '1' ) THEN‬‬ ‫‪17‬‬ ‫;‪pr_state <= nx_state‬‬


‫‪18‬‬ ‫;‪END IF‬‬ ‫‪19‬‬ ‫;‪END PROCESS‬‬ ‫‪20‬‬ ‫‪---------------------------- Upper section : ------------------------------‬‬‫‪21‬‬ ‫) ‪PROCESS ( a, b, d, pr_state‬‬ ‫‪22‬‬ ‫‪BEGIN‬‬ ‫‪23‬‬ ‫‪CASE pr_state IS‬‬ ‫‪24‬‬ ‫>= ‪WHEN stateA‬‬ ‫‪25‬‬ ‫;‪x <= a‬‬ ‫‪26‬‬ ‫;‪IF ( d = '1' ) THEN nx_state <= stateB‬‬ ‫‪27‬‬ ‫;‪ELSE nx_state <= stateA‬‬ ‫‪28‬‬ ‫;‪END IF‬‬ ‫‪29‬‬ ‫>= ‪WHEN stateB‬‬ ‫‪30‬‬ ‫;‪x <= b‬‬ ‫‪31‬‬ ‫;‪IF ( d = '1' ) THEN nx_state <= stateA‬‬ ‫‪32‬‬ ‫;‪ELSE nx_state <= stateB‬‬ ‫‪33‬‬ ‫;‪END IF‬‬ ‫‪34‬‬ ‫;‪END CASE‬‬ ‫‪35‬‬ ‫;‪END PROCESS‬‬ ‫;‪36 END simple_fsm‬‬ ‫‪37 -----------------------------------------------------------------------------------------------‬‬‫ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة اﻟﻤﺘﻌﻠﻘﺔ ﺑﺎﻟﻜﻮد اﻟﻤﻌﺮوض أﻋﻼﻩ ﻣﺒﻴﻨ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ )‪ . (٥-٨‬ﻧﻼﺣ ﻆ أن اﻟ ﺪارة ﺗﻌﻤ ﻞ آﻤ ﺎ ه ﻮ ﻣﺘﻮﻗ ﻊ‬ ‫ﻣﻨﻬﺎ ‪ .‬ﻓﻲ اﻟﻮاﻗﻊ ‪ ،‬ﺑﺎﻟﻨﻈﺮ إﻟ ﻰ ﻣﻠﻔ ﺎت اﻟﺘﻘ ﺎرﻳﺮ ‪ Report Files‬ﻳﻤﻜ ﻦ ﻟﻠﻤ ﺮء أن ﻳﺘﺤﻘ ﻖ أﻧ ﻪ وآﻤ ﺎ ه ﻮ ﻣﻨﺘﻈ ﺮ ﻓ ﺈن‬ ‫ﻗﻼﺑًﺎ وﺣﻴﺪًا ﻓﻘﻂ ﺿﺮوري ﻟﺘﻨﺠﻴﺰ هﺬﻩ اﻟ ﺪارة ﻷﻧ ﻪ ﺗﻮﺟ ﺪ ﻓﻘ ﻂ ﺣﺎﻟﺘ ﺎن ﺗﺤﺘﺎﺟ ﺎن ﻟﻠﺘﺮﻣﻴ ﺰ ‪ .‬ﻧﻼﺣ ﻆ أﻳﻀ ًﺎ أن اﻟﻤﻘﻄ ﻊ‬ ‫اﻟﻌﻠﻮي هﻮ ﺑﺎﻟﻔﻌﻞ ﺗﺮآﻴﺒﻲ ﻷن اﻟﻤﺨﺮج ‪ ) x‬واﻟ ﺬي ﻓ ﻲ ﺣﺎﻟﺘﻨ ﺎ ه ﺬﻩ ﻳﻌﺘﻤ ﺪ ﻋﻠ ﻰ اﻟﻤ ﺪﺧﻞ ‪ a‬أو ﻋﻠ ﻰ اﻟﻤ ﺪﺧﻞ ‪ b‬وﻓﻘ ًﺎ‬ ‫ﻟﻠﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ ﻟﻶﻟ ﺔ ( ﻳﺘﻐﻴ ﺮ ﻋﻨ ﺪﻣﺎ ﺗﺘﻐﻴ ﺮ ﻗﻴﻤ ﺔ اﻟﻤ ﺪﺧﻞ ‪ a‬أو ‪ b‬ﺑﻐ ﺾ اﻟﻨﻈ ﺮ ﻋ ﻦ وﺿ ﻊ اﻹﺷ ﺎرة ‪ . clk‬إذا آ ﺎن‬ ‫اﻟﻤﺨﺮج ‪ x‬ﻳﻨﺒﻐﻲ أن ﻳﻜﻮن ﻣﺘﻮاﻗﺘًﺎ ‪ Synchronous‬ﻓﺈﻧﻨﺎ ﺣﻴﻨﺌ ٍﺬ ﻳﺠﺐ أن ﻧﺴ ﺘﺨﺪم اﻟﻨﻤ ﻮذج اﻟﺘﺼ ﻤﻴﻤﻲ اﻟﺜ ﺎﻧﻲ اﻟ ﺬي‬ ‫ﺳﻴﻌﺮض ﻓﻴﻤﺎ ﻳﻠﻲ ‪.‬‬

‫اﻟﺸﻜﻞ )‪ : (٥-٨‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل )‪(٢-٨‬‬ ‫‪ -٣-٨‬ﻣﻨﻬﺞ ﺗﺼﻤﻴﻤﻲ ﺛﺎﻧﻲ ) اﻟﺨﺮج اﻟﻤﺨﺰن ( ‪Design Style # 2 ( Stored Output ) :‬‬ ‫آﻤﺎ ﺳﺒﻖ أن رأﻳﻨﺎ ﻓﻲ اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻷول ﻓﺈن اﻹﺷﺎرة ‪ pr_state‬ﻓﻘﻂ هﻲ اﻟﺘﻲ ﺗﺨﺰن ‪ .‬ﺑﻨﺎ ًء ﻋﻠ ﻰ ذﻟ ﻚ ‪ ،‬ﻓ ﺈن‬ ‫اﻟﺪارة آﻜﻞ ﻳﻤﻜﻦ أن ﺗﻠﺨﺺ آﻤﺎ هﻮ واﺿﺢ ﻓﻲ اﻟﺸﻜﻞ )‪-٦-٨‬ﺁ( ‪ .‬ﻧﻼﺣﻆ هﻨﺎ ﻓﻲ هﺬﻩ اﻟﺤﺎﻟﺔ أﻧﻪ إذا آﺎﻧ ﺖ اﻵﻟ ﺔ ﻣ ﻦ‬ ‫ﻧﻮع ‪ ) Mealy‬واﻟﺘﻲ ﺗﻌﺘﻤ ﺪ ﻓﻴﻬ ﺎ ﻗﻴﻤ ﺔ اﻟﺨ ﺮج ﻋﻠ ﻰ اﻟ ﺪﺧﻞ اﻟﺤ ﺎﻟﻲ أﻳﻀ ًﺎ ﺑﺎﻹﺿ ﺎﻓﺔ إﻟ ﻰ اﻟﺤﺎﻟ ﺔ اﻵﻧﻴ ﺔ ( ﻓ ﺈن ﻗﻴﻤ ﺔ‬ ‫اﻟﺨﺮج ﻳﻤﻜﻦ أن ﺗﺘﻐﻴﺮ ﻋﻨﺪ ﺗﻐﻴﺮ ﻗﻴﻤ ﺔ اﻟ ﺪﺧﻞ ) وﺑﺎﻟﺘ ﺎﻟﻲ ﻓ ﺈن اﻟﺨ ﺮج ﺳ ﻴﻜﻮن ﻏﻴ ﺮ ﻣﺘﻮاﻗ ﺖ ‪. ( Asynchronous‬‬


‫ﻓﻲ ﺗﻄﺒﻴﻘﺎت ﻋﺪﻳﺪة ‪ ،‬ﻳﻠﺰم أن ﺗﻜﻮن اﻹﺷﺎرات ﻣﺘﻮاﻗﺘﺔ ‪ Synchronous‬وﺑﺎﻟﺘﺎﻟﻲ ﻓﺈن اﻟﻤﺨﺮج ﻳﺠﺐ أن ﻳُﺤﺪّث ﻓﻘ ﻂ‬ ‫ﻋﻨﺪﻣﺎ ﺗﻈﻬﺮ اﻟﺤﺎﻓ ﺔ اﻟﻔﻌﺎﻟ ﺔ ﻟﻨﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ . Clock‬ﻟﺠﻌ ﻞ ﺁﻻت ‪ Mealy‬ﻣﺘﻮاﻗﺘ ﺔ ﻓ ﺈن اﻟﺨ ﺮج ﻳﺠ ﺐ أن ﻳُﺨ ﺰّن‬ ‫أﻳﻀًﺎ آﻤﺎ هﻮ واﺿﺢ ﻓﻲ اﻟﺸﻜﻞ )‪-٦-٨‬ب( ‪.‬‬ ‫هﺬﻩ اﻟﺒﻨﻴﺔ هﻲ ﻣﻮﺿﻮع اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜ ﺎﻧﻲ ‪ . Design Style #2‬ﻟﺘﻨﺠﻴ ﺰ ه ﺬﻩ اﻟﺒﻨﻴ ﺔ اﻟﺠﺪﻳ ﺪة ﻓ ﺈن ﺗﻌ ﺪﻳﻼت‬ ‫ﻃﻔﻴﻔﺔ ﺟ ﺪًا ﻳﺠ ﺐ إﺟﺮاؤه ﺎ ‪ .‬ﻋﻠ ﻰ ﺳ ﺒﻴﻞ اﻟﻤﺜ ﺎل ‪ ،‬ﻳﻤﻜﻨﻨ ﺎ اﺳ ﺘﺨﺪام إﺷ ﺎرة إﺿ ﺎﻓﻴﺔ ‪ ) Additional Signal‬وﻟ ﺘﻜﻦ‬ ‫ﻼ اﻹﺷﺎرة ‪ ( temp‬ﻻﺣﺘﺴﺎب ﻗﻴﻤﺔ اﻟﺨﺮج ) ﻓﻲ اﻟﻤﻘﻄﻊ اﻟﻌﻠﻮي اﻟﺘﺮآﻴﺒﻲ ( وﻟﻜﻦ ﺗﻤﺮﻳ ﺮ ﻗﻴﻤ ﺔ ه ﺬﻩ اﻹﺷ ﺎرة إﻟ ﻰ‬ ‫ﻣﺜ ً‬ ‫إﺷﺎرة اﻟﺨﺮج اﻟﻔﻌﻠﻴﺔ ‪ Actual Output‬ﺳﻴﺘﻢ ﻋﻨﺪﻣﺎ ﺗﻈﻬﺮ اﻟﺤﺎﻓﺔ اﻟﻔﻌﺎﻟﺔ ﻟﻨﺒﻀ ﺔ اﻟﺴ ﺎﻋﺔ ) وه ﺬا ﺳ ﻴﺘﻢ ﻓ ﻲ اﻟﻤﻘﻄ ﻊ‬ ‫اﻟﺴﻔﻠﻲ اﻟﺘﺘﺎﺑﻌﻲ ( ‪ .‬إن هﺬﻩ اﻟﺘﻌﺪﻳﻼت ﻳﻤﻜﻦ أن ﺗُﺮى ﻓﻲ اﻟﻘﺎﻟﺐ اﻟﻤﻌﺮوض أدﻧﺎﻩ ‪.‬‬

‫اﻟﺸﻜﻞ )‪ : (٦-٨‬ﻣﺨﻄﻄﺎت اﻟﺪارة ﻣﻦ أﺟﻞ ‪:‬‬ ‫)ﺁ( اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻷول )رﻗﻢ ‪ (١‬و )ب( اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ )رﻗﻢ ‪(٢‬‬ ‫ﻗﺎﻟﺐ ﺁﻟﺔ اﻟﺤﺎﻟﺔ ﻣﻦ أﺟﻞ اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ ‪State Machine Template For Design Style #2 :‬‬ ‫;‪LIBRARY ieee‬‬ ‫;‪USE ieee.std_logic_1164.all‬‬ ‫‪--------------------------------------------------------------------------------------------------‬‬‫‪ENTITY < ent_name > IS‬‬ ‫;> ‪PORT ( input : IN < data_type‬‬ ‫;‪reset, clock : IN STD_LOGIC‬‬ ‫;)> ‪output : OUT < data_type‬‬ ‫;> ‪END < ent_name‬‬ ‫‪--------------------------------------------------------------------------------------------------‬‬‫‪ARCHITECTURE < arch_name > OF < ent_name > IS‬‬ ‫;) ‪TYPE states IS ( state0, state1, state2, state3, ...‬‬ ‫;‪SIGNAL pr_state, nx_state : states‬‬ ‫;> ‪SIGNAL temp : < data_type‬‬ ‫‪BEGIN‬‬ ‫‪------------------------------ Lower section : ----------------------------‬‬‫) ‪PROCESS ( reset, clock‬‬ ‫‪BEGIN‬‬ ‫‪IF ( reset = '1' ) THEN‬‬ ‫;‪pr_state <= state0‬‬ ‫‪ELSIF ( clock'EVENT AND clock = '1' ) THEN‬‬


‫;‪output <= temp‬‬ ‫;‪pr_state <= nx_state‬‬ ‫;‪END IF‬‬ ‫;‪END PROCESS‬‬ ‫‪------------------------------- Upper section : ------------------------------‬‬‫) ‪PROCESS ( pr_state‬‬ ‫‪BEGIN‬‬ ‫‪CASE pr_state IS‬‬ ‫>= ‪WHEN state0‬‬ ‫;> ‪temp <= < value‬‬ ‫;‪IF ( condition ) THEN nx_state <= state1‬‬ ‫‪...‬‬ ‫;‪END IF‬‬ ‫>= ‪WHEN state1‬‬ ‫;> ‪temp <= < value‬‬ ‫;‪IF ( condition ) THEN nx_state <= state2‬‬ ‫‪...‬‬ ‫;‪END IF‬‬ ‫>= ‪WHEN state2‬‬ ‫;> ‪temp <= < value‬‬ ‫;‪IF ( condition ) THEN nx_state <= state3‬‬ ‫‪...‬‬ ‫;‪END IF‬‬ ‫‪...‬‬ ‫;‪END CASE‬‬ ‫;‪END PROCESS‬‬ ‫;> ‪END < arch_name‬‬ ‫‪--------------------------------------------------------------------------------------------------‬‬‫ﺑﻤﻘﺎرﻧﺔ ﻗﺎﻟﺐ اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ ﻣﻊ ﻗﺎﻟﺐ اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻷول ﻳﻤﻜﻨﻨﺎ اﻟﺘﺤﻘ ﻖ ﻣ ﻦ أن اﻻﺧﺘﻼﻓ ﺎت ه ﻲ‬ ‫ﻓﻘﻂ ﺗﻠﻚ اﻟﻤﺘﻌﻠﻘﺔ ﺑﺈدﺧﺎل إﺷﺎرة داﺧﻠﻴﺔ ‪ . temp‬هﺬﻩ اﻹﺷﺎرة ﺳﻮف ﺗﺴﺒﺐ ﺗﺨ ﺰﻳﻦ ﻗﻴﻤ ﺔ ﻣﺨ ﺮج ﺁﻟ ﺔ اﻟﺤﺎﻟ ﺔ اﻟﻤﻨﺘﻬﻴ ﺔ‬ ‫وذﻟﻚ ﻷن ﻗﻴﻤﺔ اﻹﺷﺎرة ‪ temp‬ﺗُﻤﺮّر إﻟﻰ إﺷﺎرة ﺧﺮج اﻷوﺗﻮﻣﺎت ﻓﻘﻂ ﻋﻨ ﺪﻣﺎ ﺗﻈﻬ ﺮ اﻟﺠﺒﻬ ﺔ اﻟﻔﻌﺎﻟ ﺔ ﻟﻨﺒﻀ ﺔ اﻟﺴ ﺎﻋﺔ‬ ‫‪. Clock‬‬ ‫اﻟﻤﺜﺎل )‪ : (٣-٨‬ﺁﻟﺔ ﺣﺎﻟﺔ ﻣﻨﺘﻬﻴﺔ ﺑﺴﻴﻄﺔ )‪Simple FSM # 2 (٢‬‬ ‫ﻟﻨﻌﺘﺒﺮ اﻟﺘﺼﻤﻴﻢ اﻟﻤﻌﺮوض ﻓﻲ اﻟﻤﺜﺎل )‪ (٢-٨‬ﻣﺮة أﺧﺮى أﻳﻀًﺎ ‪ .‬وﻟﻜﻦ ﻟﻨﻘﻞ اﻵن أﻧﻨﺎ ﻧﺮﻳﺪ أن ﻳﻜﻮن اﻟﺨ ﺮج ﻣﺘﻮاﻗﺘ ًﺎ‬ ‫‪ ) Synchronous‬أي ﻳﺘﻐﻴﺮ ﻓﻘﻂ ﻋﻨﺪ ﻇﻬﻮر اﻟﺠﺒﻬﺎت اﻟﻔﻌﺎﻟﺔ ﻟﻨﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ . ( Clock‬ﺑﻤ ﺎ أن ه ﺬﻩ اﻵﻟ ﺔ ه ﻲ‬ ‫ﺁﻟﺔ ‪ Mealy‬ﻓﺈن اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ ) رﻗﻢ ‪ ( ٢‬ﻳﺠﺐ أن ﻳُﺴﺘﺨﺪم هﻨﺎ ‪.‬‬ ‫‪1 ------------------------------------------------------------------------------------------------‬‬‫‪2 ENTITY simple_fsm IS‬‬ ‫‪3‬‬ ‫;‪PORT ( a, b, d, clk, rst : IN BIT‬‬ ‫‪4‬‬ ‫;) ‪x : OUT BIT‬‬ ‫;‪5 END simple_fsm‬‬ ‫‪6 -------------------------------------------------------------------------------------------------‬‬


‫‪7 ARCHITECTURE simple_fsm OF simple_fsm IS‬‬ ‫‪8‬‬ ‫;) ‪TYPE state IS ( stateA, stateB‬‬ ‫‪9‬‬ ‫;‪SIGNAL pr_state, nx_state : state‬‬ ‫‪10‬‬ ‫;‪SIGNAL temp : BIT‬‬ ‫‪11 BEGIN‬‬ ‫‪12‬‬ ‫‪----------------------------- Lower section : ---------------------------------‬‬‫‪13‬‬ ‫) ‪PROCESS ( rst, clk‬‬ ‫‪14‬‬ ‫‪BEGIN‬‬ ‫‪15‬‬ ‫‪IF ( rst = '1' ) THEN‬‬ ‫‪16‬‬ ‫;‪pr_state <= stateA‬‬ ‫‪17‬‬ ‫‪ELSIF ( clk'EVENT AND clk = '1' ) THEN‬‬ ‫‪18‬‬ ‫;‪x <= temp‬‬ ‫‪19‬‬ ‫;‪pr_state <= nx_state‬‬ ‫‪20‬‬ ‫;‪END IF‬‬ ‫‪21‬‬ ‫;‪END PROCESS‬‬ ‫‪22‬‬ ‫‪----------------------------- Upper section : ---------------------------------‬‬‫‪23‬‬ ‫) ‪PROCESS ( a, b, d, pr_state‬‬ ‫‪24‬‬ ‫‪BEGIN‬‬ ‫‪25‬‬ ‫‪CASE pr_state IS‬‬ ‫‪26‬‬ ‫>= ‪WHEN stateA‬‬ ‫‪27‬‬ ‫;‪temp <= a‬‬ ‫‪28‬‬ ‫;‪IF ( d = '1' ) THEN nx_state <= stateB‬‬ ‫‪29‬‬ ‫;‪ELSE nx_state <= stateA‬‬ ‫‪30‬‬ ‫;‪END IF‬‬ ‫‪31‬‬ ‫>= ‪WHEN stateB‬‬ ‫‪32‬‬ ‫;‪temp <= b‬‬ ‫‪33‬‬ ‫;‪IF ( d = '1' ) THEN nx_state <= stateA‬‬ ‫‪34‬‬ ‫;‪ELSE nx_state <= stateB‬‬ ‫‪35‬‬ ‫;‪END IF‬‬ ‫‪36‬‬ ‫;‪END CASE‬‬ ‫‪37‬‬ ‫;‪END PROCESS‬‬ ‫;‪38 END simple_fsm‬‬ ‫‪39 -----------------------------------------------------------------------------------------------‬‬‫ﺑﺎﻟﻨﻈﺮ إﻟﻰ ﻣﻠﻔﺎت اﻟﺘﻘﺎرﻳﺮ اﻟﻤﻮﻟﺪة ﻣ ﻦ ﻗﺒ ﻞ اﻟﻤﺘ ﺮﺟﻢ ‪ Compiler‬ﻧﻼﺣ ﻆ أن ﻗﻼﺑ ﻴﻦ اﻵن ﻗ ﺪ ﺗ ﻢ ﺣﺠﺰهﻤ ﺎ ﻣ ﻦ ﻗﺒ ﻞ‬ ‫اﻟﻤﺘﺮﺟﻢ ‪ .‬اﻷول ﻟﺘﺮﻣﻴﺰ اﻟﺤﺎﻟﺘﻴﻦ ‪ stateA‬و ‪ stateB‬ﻟﻶﻟﺔ واﻵﺧﺮ ﻟﺘﺨﺰﻳﻦ ﻗﻴﻤﺔ اﻟﺨﺮج ) اﻟﺬي أﺻ ﺒﺢ ﻣﺨﺰﻧ ًﺎ هﻨ ﺎ‬ ‫ﺑﺴﺒﺐ اﻋﺘﻤﺎد اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻟﺜﺎﻧﻲ ( ‪.‬‬ ‫ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻣﻌﺮوﺿﺔ ﻓﻲ اﻟﺸﻜﻞ )‪ . (٧-٨‬ﻧﺬآّﺮ هﻨﺎ أﻧ ﻪ ﻋﻨ ﺪﻣﺎ ﺗﻜ ﻮن إﺷ ﺎرة ﻣ ﺎ ﻣﺨﺰﻧ ﺔ ﻓ ﺈن ﻗﻴﻤﺘﻬ ﺎ ﺳ ﻮف ﺗﺒﻘ ﻰ‬ ‫ﺑﺎﻟﻀﺮورة ﺛﺎﺑﺘ ًﺔ ) ﺳﺎآﻨﺔ ( ﺑﻴﻦ ﺟﺒﻬﺘﻴﻦ ﻣﺘﺘﺎﻟﻴﺘﻴﻦ ﻟﻨﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ . Clock‬ﺑﻨ ﺎ ًء ﻋﻠ ﻰ ذﻟ ﻚ ‪ ،‬إذا ﺗﻐﻴ ﺮ اﻟ ﺪﺧﻞ ) ‪a‬‬ ‫أو ‪ b‬ﻓﻲ اﻟﻤﺜﺎل اﻟﺴﺎﺑﻖ أﻋﻼﻩ ( ﺧﻼل هﺬﻩ اﻟﻔﺘﺮة اﻟﺰﻣﻨﻴﺔ ﻓﺈن هﺬا اﻟﺘﻐﻴﺮ ﻟﻦ ﻳُﻼﺣﻆ ) ﻳُﺮى ( ﻣﻦ ﻗﺒﻞ اﻟﺪارة ‪ .‬ﻋ ﻼو ًة‬ ‫ﻋﻠﻰ ذﻟﻚ ‪ ،‬ﺣﺘﻰ ﻋﻨﺪﻣﺎ ﻳُﻼﺣﻆ هﺬا اﻟﺘﻐﻴﺮ ﻓﻲ اﻟﺪﺧﻞ ﻓﺈن ﻇﻬﻮرﻩ ﻓﻲ اﻟﺨﺮج ﺳﻴﻜﻮن ﻣﺆﺧﺮًا ‪ Delayed‬ﻣﻘﺎرﻧ ًﺔ ﻣ ﻊ‬ ‫ﻇﻬﻮرﻩ ﻓﻲ اﻟﺪﺧﻞ ) اﻷﻣﺮ اﻟﺨﺎص اﻟﻤﻤﻴﺰ ﻟﻠﺪارات اﻟﻤﺘﻮاﻗﺘﺔ ‪. ( Synchronous Circuits‬‬


‫اﻟﺸﻜﻞ )‪ : (٧-٨‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل )‪(٣-٨‬‬ ‫اﻟﻤﺜﺎل )‪ : (٤-٨‬آﺎﺷﻒ ﺗﺴﻠﺴﻞ ) ﺗﺘﺎﺑﻊ ( ‪String ( Sequence ) Detector‬‬ ‫ﻧﺮﻳﺪ ﺗﺼﻤﻴﻢ دارة ﺗﺴﺘﻘﺒﻞ آﺪﺧﻞ ﻟﻬﺎ ﺳﻠﺴﻠﺔ ﻣﻦ اﻟﺨﺎﻧﺎت اﻟﻤﺘﺘﺎﺑﻌﺔ ﻋﻠﻰ ﻣﺪﺧﻞ ‪ d‬ﺑﻌﺮض ﺧﺎﻧﺔ واﺣﺪة وﺗﻘ ﻮم ﺑ ﺈﺧﺮاج‬ ‫ﻗﻴﻤﺔ '‪ '1‬ﻋﻠﻰ اﻟﻤﺨﺮج ‪ q‬ﻋﻨﺪ آﺸﻒ اﻟﺘﺘﺎﺑﻊ "‪ "111‬ﻋﻠﻰ اﻟﻤﺪﺧﻞ ‪ . d‬اﻟﺘﺪاﺧﻼت ‪ Overlaps‬ﻳﺠ ﺐ أن ﺗﺆﺧ ﺬ أﻳﻀ ًﺎ‬ ‫ﻻ ﻣ ﻦ أﺟ ﻞ‬ ‫ﺑﻌﻴﻦ اﻻﻋﺘﺒﺎر إي إذا ﺗ ﻢ آﺸ ﻒ اﻟﺘﺘ ﺎﺑﻊ "‪ "0111110‬ﻋﻠ ﻰ اﻟ ﺪﺧﻞ ‪ d‬ﻓ ﺈن اﻟﺨ ﺮج ‪ q‬ﻳﺠ ﺐ أن ﻳﺒﻘ ﻰ ﻓﻌ ﺎ ً‬ ‫ﻓﺘﺮة زﻣﻨﻴﺔ ﺗﺴﺎوي ﺛﻼث دورات ﻣﺘﺘﺎﻟﻴﺔ ﻟﻨﺒﻀﺎت اﻟﺴﺎﻋﺔ ‪. Clock‬‬ ‫ﻣﺨﻄﻂ اﻟﺤﺎﻻت ﻵﻟﺘﻨﺎ هﺬﻩ ﻣﺒﻴﻦ ﻓﻲ اﻟﺸﻜﻞ )‪ . (٨-٨‬آﻤﺎ هﻮ واﺿﺢ ﻓﻲ اﻟﺸﻜﻞ ‪ ،‬ﺗﻮﺟﺪ أرﺑ ﻊ ﺣ ﺎﻻت وه ﻲ ‪، Zero‬‬ ‫‪ Two ، One‬و ‪ Three‬ﺑﺤﻴ ﺚ أن آ ﻞ اﺳ ﻢ ﻳﻮاﻓ ﻖ ﻋ ﺪد اﻟﻮاﺣ ﺪات اﻟﻤﺘﺘﺎﻟﻴ ﺔ اﻟﻤﻜﺘﺸ ﻔﺔ ﻋﻠ ﻰ اﻟ ﺪﺧﻞ ‪ . d‬اﻟﺤ ﻞ‬ ‫اﻟﻤﻌﺮوض أدﻧﺎﻩ ﻳﺴﺘﺨﺪم اﻟﻤﻨﻬﺞ اﻟﺘﺼﻤﻴﻤﻲ اﻷول ) رﻗﻢ ‪. ( ١‬‬

‫اﻟﺸﻜﻞ )‪ : (٨-٨‬ﻣﺨﻄﻂ اﻟﺤﺎﻻت ﻟﻜﺎﺷﻒ اﻟﺘﺘﺎﺑﻊ ) اﻟﺘﺴﻠﺴﻞ ( ﻟﻠﻤﺜﺎل )‪(٤-٨‬‬ ‫ﻧﻼﺣ ﻆ ﻓ ﻲ ه ﺬا اﻟﻤﺜ ﺎل أن اﻟﻤﺨ ﺮج ‪ q‬ﻻ ﻳﻌﺘﻤ ﺪ ﻋﻠ ﻰ اﻟ ﺪﺧﻞ اﻟﺤ ﺎﻟﻲ ‪ . d‬ه ﺬا اﻷﻣ ﺮ ﻳﻤﻜ ﻦ اﻟﺘﺤﻘ ﻖ ﻣﻨ ﻪ ﻣ ﻦ ﺧ ﻼل‬ ‫اﻷﺳﻄﺮ ‪ 38 ، 33 ، 28‬و ‪ 43‬ﻣﻦ اﻟﻜﻮد اﻟﻤﺒﻴﻦ أدﻧ ﺎﻩ واﻟﺘ ﻲ ﺗﺒ ﻴﻦ أن آﺎﻓ ﺔ ﻋﻤﻠﻴ ﺎت اﻹﺳ ﻨﺎد ﻹﺷ ﺎرة اﻟﺨ ﺮج ‪ q‬ه ﻲ‬ ‫ﻏﻴﺮ ﻣﺸﺮوﻃﺔ ‪ ) Unconditional‬أي أﻧﻬﺎ ﻻ ﺗﻌﺘﻤ ﺪ ﻋﻠ ﻰ ﻗﻴﻤ ﺔ اﻟ ﺪﺧﻞ ‪ ( d‬وﺑﺎﻟﺘ ﺎﻟﻲ ﻓ ﺈن اﻟﻤﺨ ﺮج ‪ q‬ه ﻮ ﻣﺘﻮاﻗ ﺖ‬ ‫ﺑﺸ ﻜﻞ ﺗﻠﻘ ﺎﺋﻲ ) ﻷن اﻵﻟ ﺔ ه ﻲ ﻣ ﻦ ﻧ ﻮع ‪ ( Moore‬إذًا اﺳ ﺘﺨﺪام اﻟﻤ ﻨﻬﺞ اﻟﺘﺼ ﻤﻴﻤﻲ اﻟﺜ ﺎﻧﻲ ) رﻗ ﻢ ‪ ( ٢‬ه ﻮ ﻏﻴ ﺮ‬ ‫ﺿﺮوري ‪.‬‬ ‫إن اﻟﺪارة ﺗﺘﻄﻠﺐ ﻗﻼﺑﻴﻦ اﺛﻨﻴﻦ ﻟﺘﺮﻣﻴﺰ اﻟﺤﺎﻻت اﻷرﺑﻌ ﺔ ﻵﻟ ﺔ اﻟﺤﺎﻟ ﺔ اﻟﻤﻨﺘﻬﻴ ﺔ واﻧﻄﻼﻗ ًﺎ ﻣ ﻦ ﻣﺨﺮﺟ ﻲ ه ﺬﻳﻦ اﻟﻘﻼﺑ ﻴﻦ‬ ‫ﻳﺘﻢ اﺣﺘﺴﺎب ﻗﻴﻤﺔ اﻟﻤﺨﺮج ‪ . q‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻣﻌﺮوﺿﺔ ﻓﻲ اﻟﺸﻜﻞ )‪ . (٩-٨‬آﻤﺎ هﻮ واﺿﺢ ﻟﻠﻌﻴ ﺎن ‪ ،‬ﻓﻘ ﺪ ﺗ ﻢ ﺗﻄﺒﻴ ﻖ‬ ‫ﺗﺘﺎﺑﻊ ﺧﺎﻧﺎت اﻟﻤﻌﻄﻴﺎت "‪ d = "011101100‬ﻋﻠﻰ اﻟﻤﺪﺧﻞ ‪ d‬ﻟﻠﺪارة ﻣﻤﺎ ﻧ ﺘﺞ ﻋﻨ ﻪ ﺗﺘ ﺎﺑﻊ ﺧﺎﻧ ﺎت اﻟﻤﻌﻄﻴ ﺎت اﻟﺘ ﺎﻟﻲ‬ ‫ﻋﻠﻰ اﻟﻤﺨﺮج ‪ q‬ﻟﻠﺪارة ‪. q = "000100000" :‬‬


(٤-٨) ‫ ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل‬: (٩-٨) ‫اﻟﺸﻜﻞ‬ 1 --------------------------------------------------------------------------------------2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 --------------------------------------------------------------------------------------5 ENTITY string_detector IS 6 PORT ( d, clk, rst : IN BIT; 7 q : OUT BIT ); 8 END string_detector; 9 --------------------------------------------------------------------------------------10 ARCHITECTURE my_arch OF string_detector IS 11 TYPE state IS ( zero, one, two, three ); 12 SIGNAL pr_state, nx_state : state; 13 BEGIN 14 ---------------------------- Lower section : -----------------------------15 PROCESS ( rst, clk ) 16 BEGIN 17 IF ( rst = '1' ) THEN 18 pr_state <= zero; 19 ELSIF ( clk'EVENT AND clk = '1' ) THEN 20 pr_state <= nx_state; 21 END IF; 22 END PROCESS; 23 ---------------------------- Upper section : ------------------------------24 PROCESS ( d, pr_state ) 25 BEGIN 26 CASE pr_state IS 27 WHEN zero => 28 q <= '0'; 29 IF ( d = '1' ) THEN nx_state <= one; 30 ELSE nx_state <= zero; 31 END IF; 32 WHEN one => 33 q <= '0'; 34 IF ( d = '1' ) THEN nx_state <= two;


‫‪35‬‬ ‫;‪ELSE nx_state <= zero‬‬ ‫‪36‬‬ ‫;‪END IF‬‬ ‫‪37‬‬ ‫>= ‪WHEN two‬‬ ‫‪38‬‬ ‫;'‪q <= '0‬‬ ‫‪39‬‬ ‫;‪IF ( d = '1' ) THEN nx_state <= three‬‬ ‫‪40‬‬ ‫;‪ELSE nx_state <= zero‬‬ ‫‪41‬‬ ‫;‪END IF‬‬ ‫‪42‬‬ ‫>= ‪WHEN three‬‬ ‫‪43‬‬ ‫;'‪q <= '1‬‬ ‫‪44‬‬ ‫;‪IF ( d = '0' ) THEN nx_state <= zero‬‬ ‫‪45‬‬ ‫;‪ELSE nx_state <= three‬‬ ‫‪46‬‬ ‫;‪END IF‬‬ ‫‪47‬‬ ‫;‪END CASE‬‬ ‫‪48‬‬ ‫;‪END PROCESS‬‬ ‫;‪49 END my_arch‬‬ ‫‪50 -------------------------------------------------------------------------------------‬‬‫اﻟﻤﺜﺎل )‪ : (٥-٨‬ﻣﺘﺤﻜﻢ ﺑﺄﺿﻮاء إﺷﺎرة ﻣﺮور ) ‪Traffic Light Controller ( TLC‬‬ ‫آﻤﺎ ﻧﻮهﻨﺎ ﺳﺎﺑﻘًﺎ ‪ ،‬ﻓﺈن اﻟﻤﺘﺤﻜﻤ ﺎت اﻟﺮﻗﻤﻴ ﺔ ‪ Digital Controllers‬ه ﻲ أﻣﺜﻠ ﺔ ﺟﻴ ﺪة ﻋﻠ ﻰ اﻟ ﺪارات اﻟﺘ ﻲ ﻳﻤﻜ ﻦ أن‬ ‫ﺗﻨﺠﺰ ﺑﻔﻌﺎﻟﻴﺔ ﻋﻨ ﺪﻣﺎ ُﺗﻨَﻤ ﺬج آ ﺂﻻت ﺣﺎﻟ ﺔ ﻣﻨﺘﻬﻴ ﺔ ‪ .‬ﻓ ﻲ اﻟﻤﺜ ﺎل اﻟﺤ ﺎﻟﻲ ‪ ،‬ﻧﺮﻳ ﺪ ﺗﺼ ﻤﻴﻢ ﻣ ﺘﺤﻜﻢ ﺑﺄﺿ ﻮاء إﺷ ﺎرة ﻣ ﺮور‬ ‫‪ Traffic Light Controller‬أو ﻣ ﺎ ﻳﻌ ﺮف اﺧﺘﺼ ﺎرًا ﺑﺎﺳ ﻢ ) ‪ ( TLC‬واﻟ ﺬي ﻳﺘﻤﻴ ﺰ ﺑﺎﻟﻤﻮاﺻ ﻔﺎت اﻟﻤ ﻮﺟﺰة‬ ‫اﻟﻤﻌﺮوﺿﺔ ﻓﻲ اﻟﺠﺪول اﻟﻤﺒﻴﻦ ﻓﻲ اﻟﺸﻜﻞ )‪: (١٠-٨‬‬ ‫*** ﺛﻼﺛﺔ أﻧﻤﺎط ﻟﻠﻌﻤﻞ ‪ :‬ﻧﻈﺎﻣﻲ ‪ ، Regular‬اﺧﺘﺒﺎر ‪ Test‬و ﺑﺪﻳﻞ ) اﺳﺘﻌﺪاد ( ‪. Standby‬‬ ‫‪ -١‬ﻧﻤﻂ اﻟﻌﻤﻞ اﻟﻨﻈﺎﻣﻲ ) أو اﻟﻄﺒﻴﻌﻲ ( ‪ : Regular Mode‬هﺬا اﻟﻨﻤﻂ ﻳﺘﻜﻮن ﻣﻦ أرﺑ ﻊ ﺣ ﺎﻻت آ ﻞ ﻣﻨﻬ ﺎ ذو ﻓﺘ ﺮة‬ ‫زﻣﻨﻴﺔ ﻣﺴﺘﻘﻠﺔ ﻗﺎﺑﻠﺔ ﻟﻠﺒﺮﻣﺠﺔ وهﺬﻩ اﻟﻔﺘﺮات اﻟﺰﻣﻨﻴﺔ ﺗُﻤﺮّر إﻟﻰ اﻟﺪارة ﺑﻮاﺳﻄﺔ ﺛﻮاﺑﺖ ‪. CONSTANTS‬‬ ‫‪ -٢‬ﻧﻤﻂ اﻟﻌﻤﻞ اﻻﺧﺘﺒﺎري ‪ : Test Mode‬اﻻﻧﺘﻘﺎل إﻟﻰ هﺬا اﻟﻨﻤﻂ ﻣﻦ اﻟﻌﻤ ﻞ ﻳﻤﻜ ﻦ أن ﻳ ﺘﻢ ﻣ ﻦ ﺧ ﻼل ﻣﻔﺘ ﺎح ﻳ ﺪوي‬ ‫‪ Manual Switch‬اﻷﻣﺮ اﻟﺬي ﻳﺆدي إﻟﻰ اﺳ ﺘﺒﺪال آﺎﻓ ﺔ اﻷزﻣﻨ ﺔ اﻟﻤﺒﺮﻣﺠ ﺔ ﻣﺴ ﺒﻘًﺎ ﻣ ﻦ أﺟ ﻞ ﺣﺎﻟ ﺔ اﻟﻌﻤ ﻞ اﻟﻨﻈ ﺎﻣﻲ‬ ‫واﻋﺘﻤﺎد ﻗﻴﻤﺔ زﻣﻨﻴﺔ ﺻﻐﻴﺮة ﺛﺎﺑﺘﺔ وﺟﺪﻳﺪة ﻣﻦ أﺟ ﻞ آﺎﻓ ﺔ ﺣ ﺎﻻت اﻹﺿ ﺎءة ﻹﺷ ﺎرة اﻟﻤ ﺮور ‪ .‬ه ﺬا اﻟ ﻨﻤﻂ ﻣ ﻦ اﻟﻌﻤ ﻞ‬ ‫ﻼ ﺛﺎﻧﻴﺔ واﺣﺪة ﻟﻜﻞ ﺣﺎﻟﺔ إﺿﺎءة ( ‪ .‬ه ﺬﻩ اﻟﻔﺘ ﺮة‬ ‫ﻳﺴﻤﺢ ﺑﺈﺟﺮاء اﻻﺧﺘﺒﺎر ﻟﻠﻨﻈﺎم ﺑﺸﻜﻞ ﺳﻬﻞ ﺧﻼل ﻋﻤﻠﻴﺔ اﻟﺼﻴﺎﻧﺔ ) ﻣﺜ ً‬ ‫اﻟﺰﻣﻨﻴ ﺔ اﻟﺜﺎﺑﺘ ﺔ ﻳﺠ ﺐ أن ﺗﻜ ﻮن أﻳﻀ ًﺎ ﻗﺎﺑﻠ ﺔ ﻟﻠﺒﺮﻣﺠ ﺔ وﻳﻤﻜ ﻦ ﺗﻤﺮﻳﺮه ﺎ إﻟ ﻰ اﻟ ﺪارة ﻣ ﻦ ﺧ ﻼل ﻗﻴﻤ ﺔ ﺛﺎﺑﺘ ﺔ‬ ‫‪. CONSTANT‬‬ ‫‪ -٣‬ﻧﻤﻂ اﻟﻌﻤﻞ اﻟﺒﺪﻳﻞ ) ﻧﻤﻂ اﻻﺳﺘﻌﺪاد ( ‪ : Standby Mode‬إذا ﺗﻢ ﺗﻔﻌﻴﻞ هﺬا اﻟ ﻨﻤﻂ ) ﺑﻮاﺳ ﻄﺔ ﺣﺴ ﺎس ‪Sensor‬‬ ‫ﻳﺸﻴﺮ إﻟﻰ ﺳﻮء اﻷداء أو ﻗﺼﻮر ﻓﻲ ﻋﻤﻞ اﻟﻨﻈﺎم ﻋﻠﻰ ﺳﺒﻴﻞ اﻟﻤﺜﺎل أو ﺑﻮاﺳ ﻄﺔ ﻣﻔﺘ ﺎح ﻳ ﺪوي ( ﻓ ﺈن اﻟﻨﻈ ﺎم ﻳﺠ ﺐ أن‬ ‫ﻳُﻔﻌّﻞ اﻷﺿﻮاء اﻟﺼﻔﺮاء ﻓﻲ آﻼ اﻻﺗﺠ ﺎهﻴﻦ وﻳﺒﻘ ﻰ ﻓ ﻲ ه ﺬﻩ اﻟﺤﺎﻟ ﺔ ﻃﺎﻟﻤ ﺎ أن إﺷ ﺎرة اﻻﺳ ﺘﻌﺪاد ‪ Standby‬ﻣ ﺎ ﺗ ﺰال‬ ‫ﻓﻌﺎﻟﺔ ‪. Active‬‬ ‫*** ﺳﻨﻔﺘﺮض أن ﻧﺒﻀﺎت ﺳﺎﻋﺔ ‪ Clock‬ﺑﺘﺮدد ﻗﺪرﻩ ‪ ) 60 Hz‬ﻣﺄﺧﻮذة ﻣﻦ ﺧﻂ اﻟﻘﺪرة اﻟﻜﻬﺮﺑﺎﺋﻴ ﺔ ﻧﻔﺴ ﻪ ( ﻣﺘﺎﺣ ﺔ‬ ‫ﻣﻦ أﺟﻞ اﻻﺳﺘﺨﺪام آﺈﺷﺎرة ‪ Clock‬ﻟﻠﺪارة ‪.‬‬ ‫هﻨﺎ ﻳﻤﻜﻦ اﺳﺘﺨﺪام اﻟﻨﻤﻮذج اﻟﺘﺼﻤﻴﻤﻲ اﻷول ) رﻗﻢ ‪ ( ١‬آﻤﺎ هﻮ واﺿﺢ ﻓﻲ اﻟﻜﻮد اﻟﺘﺎﻟﻲ ‪:‬‬


(٥-٨) ‫ ﻣﻮاﺻﻔﺎت وﻣﺨﻄﻂ اﻟﺤﺎﻻت ) ﻟﻨﻤﻂ اﻟﻌﻤﻞ اﻟﻄﺒﻴﻌﻲ ( ﻟﻤﺘﺤﻜﻢ إﺷﺎرة اﻟﻤﺮور ﻟﻠﻤﺜﺎل‬: (١٠-٨) ‫اﻟﺸﻜﻞ‬ 1 ------------------------------------------------------------------------------------------------2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------------------------------------------------------------------5 ENTITY tlc IS 6 PORT ( clk, stby, test : IN STD_LOGIC; 7 r1, r2, y1, y2, g1, g2 : OUT STD_LOGIC ); 8 END tlc; 9 ------------------------------------------------------------------------------------------------10 ARCHITECTURE behavior OF tlc IS 11 CONSTANT timeMAX : INTEGER := 2700; 12 CONSTANT timeRG : INTEGER := 1800; 13 CONSTANT timeRY : INTEGER := 300; 14 CONSTANT timeGR : INTEGER := 2700; 15 CONSTANT timeYR : INTEGER := 300; 16 CONSTANT timeTEST : INTEGER := 60; 17 TYPE state IS ( RG, RY, GR, YR, YY ); 18 SIGNAL pr_state, nx_state : state; 19 SIGNAL time : INTEGER RANGE 0 TO timeMAX;


20 BEGIN 21 ------------------------- Lower section of state machine : -------------------------22 PROCESS ( clk, stby ) 23 VARIABLE count : INTEGER RANGE 0 TO timeMAX; 24 BEGIN 25 IF ( stby = '1' ) THEN 26 pr_state <= YY; 27 count := 0; 28 ELSIF ( clk'EVENT AND clk = '1' ) THEN 29 count := count + 1; 30 IF ( count = time ) THEN 31 pr_state <= nx_state; 32 count := 0; 33 END IF; 34 END IF; 35 END PROCESS; 36 -------------------------- Upper section of state machine : ------------------------37 PROCESS ( pr_state, test ) 38 BEGIN 39 CASE pr_state IS 40 WHEN RG => 41 r1 <= '1'; r2 <= '0'; y1 <= '0'; y2 <= '0'; g1 <= '0'; g2 <= '1'; 42 nx_state <= RY; 43 IF ( test = '0' ) THEN time <= timeRG; 44 ELSE time <= timeTEST; 45 END IF; 46 WHEN RY => 47 r1 <= '1'; r2 <= '0'; y1 <= '0'; y2 <= '1'; g1 <= '0'; g2 <= '0'; 48 nx_state <= GR; 49 IF ( test = '0' ) THEN time <= timeRY; 50 ELSE time <= timeTEST; 51 END IF; 52 WHEN GR => 53 r1 <= '0'; r2 <= '1'; y1 <= '0'; y2 <= '0'; g1 <= '1'; g2 <= '0'; 54 nx_state <= YR; 55 IF ( test = '0' ) THEN time <= timeGR; 56 ELSE time <= timeTEST; 57 END IF; 58 WHEN YR => 59 r1 <= '0'; r2 <= '1'; y1 <= '1'; y2 <= '0'; g1 <= '0'; g2 <= '0'; 60 nx_state <= RG; 61 IF ( test = '0' ) THEN time <= timeYR; 62 ELSE time <= timeTEST; 63 END IF;


‫‪64‬‬ ‫>= ‪WHEN YY‬‬ ‫‪65‬‬ ‫;'‪r1 <= '0'; r2 <= '0'; y1 <= '1'; y2 <= '1'; g1 <= '0'; g2 <= '0‬‬ ‫‪66‬‬ ‫;‪nx_state <= RY‬‬ ‫‪67‬‬ ‫;‪END CASE‬‬ ‫‪68‬‬ ‫;‪END PROCESS‬‬ ‫;‪69 END behavior‬‬ ‫‪70 -----------------------------------------------------------------------------------------------‬‬‫إن اﻟﻌﺪد اﻟﻤﺘﻮﻗﻊ ﻟﻠﻘﻼﺑﺎت اﻟﻼزﻣﺔ ﻟﺘﻨﺠﻴﺰ هﺬﻩ اﻟﺪارة هﻮ ‪ 15‬ﻗﻼﺑًﺎ ‪ :‬ﺛﻼﺛﺔ ﻗﻼﺑﺎت ﻟﺘﺨﺰﻳﻦ اﻹﺷﺎرة ‪ ) pr_state‬ﺁﻟ ﺔ‬ ‫اﻟﺤﺎﻟﺔ ﺗﻤﺘﻠﻚ ﺧﻤﺲ ﺣﺎﻻت وﺑﺎﻟﺘ ﺎﻟﻲ ﻓﺈﻧ ﻪ ﻳﻠ ﺰم ﺛ ﻼث ﺧﺎﻧ ﺎت ﻟﺘﺮﻣﻴﺰه ﺎ ( ﺑﺎﻹﺿ ﺎﻓﺔ إﻟ ﻰ ‪ 12‬ﻗ ﻼب ﻣ ﻦ أﺟ ﻞ اﻟﻌ ﺪاد‬ ‫‪ ) count‬ﺑﺎﻋﺘﺒﺎر أﻧﻪ ﻋﺪاد ﺑﻄﻮل ‪ 12‬ﺧﺎﻧﺔ ﻷﻧﻪ ﻳﺠﺐ أن ﻳﻌﺪ ﺑﺸﻜﻞ ﺗﺼﺎﻋﺪي ﻣ ﻦ اﻟﺼ ﻔﺮ وﺣﺘ ﻰ اﻟﻘﻴﻤ ﺔ اﻷﻋﻈﻤﻴ ﺔ‬ ‫‪. ( MAX = 2700‬‬ ‫ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻣﻮﺿﺤﺔ ﻓﻲ اﻟﺸﻜﻞ )‪ . (١١-٨‬ﻣﻦ أﺟﻞ أن ﺗﺘﺴﻊ اﻟﻨﺘﺎﺋﺞ ﺑﺸﻜﻞ ﻣﻼﺋﻢ ﺿ ﻤﻦ اﻟﻤﺨﻄﻄ ﺎت اﻟﺒﻴﺎﻧﻴ ﺔ ﻓﻘ ﺪ‬ ‫ﺗﻢ اﻋﺘﻤﺎد ﻗ ﻴﻢ أزﻣﻨ ﺔ ﺻ ﻐﻴﺮة ﺑﺤﻴ ﺚ ﺗﻜ ﻮن ﻗ ﻴﻢ آﺎﻓ ﺔ اﻟﺜﻮاﺑ ﺖ ‪ CONSTANTS‬ﻣﺴ ﺎوﻳﺔ ﻟﻠﻘﻴﻤ ﺔ ‪ 3‬ﻣ ﺎ ﻋ ﺪا اﻟ ﺰﻣﻦ‬ ‫‪ timeTEST‬اﻟﺬي أﻋﻄﻲ ﻟﻪ اﻟﻘﻴﻤﺔ ‪ . 1‬ﺑﻨﺎ ًء ﻋﻠﻰ ذﻟﻚ ‪ ،‬ﻓﺈﻧﻪ ﻣﻦ اﻟﻤﺘﻮﻗﻊ أن ﻳﻐﻴ ﺮ اﻟﻨﻈ ﺎم ﺣﺎﻟﺘ ﻪ آ ﻞ ﺛ ﻼث دورات‬ ‫ﻟﻨﺒﻀﺎت اﻟﺴﺎﻋﺔ ﻋﻨﺪﻣﺎ ﻳﻌﻤﻞ ﻓﻲ ﻧﻤﻂ اﻟﻌﻤﻞ اﻟﻨﻈﺎﻣﻲ ‪ Regular Mode‬أو آﻞ دورة ﻟﻨﺒﻀ ﺔ اﻟﺴ ﺎﻋﺔ ﻋﻨ ﺪﻣﺎ ﻳﻌﻤ ﻞ‬ ‫ﻓ ﻲ ﻧﻤ ﻂ اﻟﻌﻤ ﻞ اﻻﺧﺘﺒ ﺎري ‪ . Test Mode‬هﺎﺗ ﺎن اﻟﺤﺎﻟﺘ ﺎن ﻳﻤﻜ ﻦ ﻣﻼﺣﻈﺘﻬﻤ ﺎ ﻓ ﻲ اﻟﻤﺨﻄﻄ ﺎت اﻟﺰﻣﻨﻴ ﺔ اﻷوﻟ ﻰ‬ ‫واﻟﺜﺎﻧﻴﺔ ﻣﻦ اﻟﺸﻜﻞ )‪ (١١-٨‬ﻋﻠﻰ اﻟﺘﺘﺎﻟﻲ ‪.‬‬ ‫اﻟﻤﺨﻄﻄﺎت اﻟﺰﻣﻨﻴﺔ اﻟﺜﺎﻟﺜﺔ ﺗﺒﻴﻦ ﻧﻤﻂ ﻋﻤﻞ اﻻﺳﺘﻌﺪاد ‪ Standby Mode‬وﻓﻴﻬﺎ ﺗﻢ ﺗﻔﻌﻴﻞ هﺬا اﻟﻨﻤﻂ ‪ .‬آﻤﺎ هﻮ ﻣﻨﺘﻈﺮ‬ ‫ﻓﺈن اﻹﺷﺎرة ‪ stby‬ه ﻲ ﻏﻴ ﺮ ﻣﺘﻮاﻗﺘ ﺔ ‪ Asynchronous‬وﺗﻤﺘﻠ ﻚ اﻷوﻟﻮﻳ ﺔ اﻷﻋﻠ ﻰ ﻣﻘﺎرﻧ ًﺔ ﻣ ﻊ إﺷ ﺎرة اﻟ ﺪﺧﻞ ‪test‬‬ ‫وهﻲ ﺗﺪﻓﻊ اﻟﻨﻈﺎم ﻟﻠﺪﺧﻮل واﻟﺒﻘﺎء ﻓﻲ اﻟﺤﺎﻟﺔ ‪ ) YY‬اﻟﺤﺎﻟﺔ ‪ state4‬اﻟﻤﺘﻤﺜﻠ ﺔ ﻓ ﻲ إﺿ ﺎءة اﻷﺿ ﻮاء اﻟﺼ ﻔﺮاء ﻹﺷ ﺎرة‬ ‫اﻟﻤﺮور ﻓﻲ آﻼ اﻻﺗﺠﺎهﻴﻦ ( ﻃﺎﻟﻤﺎ أن اﻹﺷﺎرة ‪ stby‬ﻣﺎ ﺗﺰال ﻓﻌﺎﻟﺔ ‪ .‬ﻣﻦ اﻟﺠﻬ ﺔ اﻷﺧ ﺮى ‪ ،‬ﻓ ﺈن إﺷ ﺎرة اﻟ ﺪﺧﻞ ‪test‬‬ ‫هﻲ ﻣﺘﻮاﻗﺘﺔ ‪ Synchronous‬وﻟﻜﻦ ﻻ ﺣﺎﺟﺔ ﻋﻨﺪ ﺗﻔﻌﻴﻠﻬﺎ إﻟﻰ اﻻﻧﺘﻈﺎر رﻳﺜﻤﺎ ﺗﻨﺘﻬﻲ اﻟﻔﺘﺮة اﻟﺰﻣﻨﻴﺔ اﻟﺨﺎﺻ ﺔ ﺑﺎﻟﺤﺎﻟ ﺔ‬ ‫اﻵﻧﻴﺔ ﻣﻦ أﺟﻞ ﺗﻔﻌﻴﻞ هﺬا اﻟﻨﻤﻂ آﻤﺎ هﻮ واﺿﺢ ﻓﻲ اﻟﻤﺨﻄﻄﺎت اﻟﺰﻣﻨﻴﺔ اﻟﺜﺎﻧﻴﺔ ﻣﻦ اﻟﺸﻜﻞ )‪. (١١-٨‬‬ ‫اﻟﻤﺜﺎل )‪ : (٦-٨‬ﻣﻮﻟﺪ إﺷﺎرة ‪Signal Generator‬‬ ‫ﻧﺮﻳﺪ ﺗﺼﻤﻴﻢ دارة ﻗﺎدرة ﻋﻠﻰ ﺗﻮﻟﻴﺪ إﺷﺎرة اﻟﺨﺮج ‪ outp‬اﻟﻤﺒﻴﻨﺔ ﻓﻲ اﻟﺸﻜﻞ )‪-١٢-٨‬ﺁ( وذﻟﻚ اﻧﻄﻼﻗًﺎ ﻣﻦ إﺷﺎرة دﺧ ﻞ‬ ‫ﻧﺒﻀﺎت اﻟﺴﺎﻋﺔ ‪ . clk‬ﻧﻨﺒ ﻪ هﻨ ﺎ إﻟ ﻰ أن اﻟ ﺪارة ﻳﺠ ﺐ أن ﺗﻌﻤ ﻞ ﻋﻨ ﺪ آ ﻞ ﻣ ﻦ اﻟﺠﺒﻬ ﺎت اﻟﺼ ﺎﻋﺪة واﻟﻬﺎﺑﻄ ﺔ ﻟﻨﺒﻀ ﺎت‬ ‫اﻟﺴﺎﻋﺔ ‪. clk‬‬ ‫ﻟﺘﺠﺎوز ﻣﺸﻜﻠﺔ ﺗﺸﻐﻴﻞ اﻟﺪارة ﻋﻨﺪ آﻞ ﻣﻦ اﻟﺠﺒﻬﺘ ﻴﻦ اﻟﺼ ﺎﻋﺪة واﻟﻬﺎﺑﻄ ﺔ ﻓ ﺈن أﺣ ﺪ اﻟﺤﻠ ﻮل اﻟﻤﻤﻜﻨ ﺔ ﻳﺘﻤﺜ ﻞ ﻓ ﻲ ﺗﻨﺠﻴ ﺰ‬ ‫ﺁﻟﺘﻲ ﺣﺎﻟﺔ ‪ :‬اﻷوﻟﻰ ﺗﻌﻤ ﻞ ﺣﺼ ﺮﻳًﺎ ﻋﻨ ﺪ اﻟﺠﺒﻬ ﺎت اﻟﺼ ﺎﻋﺪة ﻹﺷ ﺎرة ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ clk‬واﻷﺧ ﺮى ﺗﻌﻤ ﻞ ﺣﺼ ﺮﻳًﺎ‬ ‫ﻋﻨ ﺪ اﻟﺠﺒﻬ ﺎت اﻟﻬﺎﺑﻄ ﺔ ﻹﺷ ﺎرة ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ . clk‬إن هﺎﺗ ﺎن اﻵﻟﺘ ﺎن ﺳ ﺘﻘﻮﻣﺎن ﺑﺘﻮﻟﻴ ﺪ اﻹﺷ ﺎرﺗﻴﻦ اﻟﻮﺳ ﻴﻄﻴﺘﻴﻦ‬ ‫‪ out1‬و ‪ out2‬اﻟﻤﺒﻴﻨﺘ ﻴﻦ ﻓ ﻲ اﻟﺸ ﻜﻞ )‪-١٢-٨‬ب( ‪ .‬هﺎﺗ ﺎن اﻹﺷ ﺎرﺗﺎن ﻳﻤﻜ ﻦ أن ﺗﻄﺒﻘ ﺎ ﻋﻠ ﻰ ﻣ ﺪﺧﻠﻲ ﺑﻮاﺑ ﺔ ‪AND‬‬ ‫ﻟﻠﺤﺼﻮل ﻋﻠﻰ إﺷﺎرة اﻟﺨﺮج اﻟﻤﻄﻠﻮﺑﺔ ‪. outp‬‬ ‫ﻧﻼﺣﻆ هﻨﺎ أن هﺬﻩ اﻟﺪارة ﻻ ﺗﻤﺘﻠ ﻚ ﻣ ﺪاﺧﻞ ﺧﺎرﺟﻴ ﺔ ) ﺑﺎﺳ ﺘﺜﻨﺎء إﺷ ﺎرة ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ clk‬ﺑ ﺎﻟﻄﺒﻊ ( وﺑﺎﻟﺘ ﺎﻟﻲ ﻓ ﺈن‬ ‫ﻗﻴﻤ ﺔ اﻟﺨ ﺮج ﻳﻤﻜ ﻦ أن ﺗﺘﻐﻴ ﺮ ﻓﻘ ﻂ ﻋﻨ ﺪﻣﺎ ﺗﺘﻐﻴ ﺮ ﻗﻴﻤ ﺔ إﺷ ﺎرة ﻧﺒﻀ ﺎت اﻟﺴ ﺎﻋﺔ ‪ ) clk‬أي أن اﻟﺨ ﺮج ﻣﺘﻮاﻗ ﺖ‬ ‫‪. ( Synchronous‬‬ ‫ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻣﻦ اﻟﺪارة اﻟﻤﺮآﺒﺔ اﻧﻄﻼﻗًﺎ ﻣﻦ اﻟﻜﻮد اﻟﻤﻌﺮوض أدﻧﺎﻩ ﻣﺒﻴﻨﺔ ﻓﻲ اﻟﺸﻜﻞ )‪. (١٣-٨‬‬


‫اﻟﺸﻜﻞ )‪ : (١١-٨‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل )‪(٥-٨‬‬

‫اﻟﺸﻜﻞ )‪ : (١٢-٨‬أﺷﻜﺎل اﻷﻣﻮاج ﻟﻠﻤﺜﺎل )‪ ) : (٦-٨‬ﺁ ( إﺷﺎرة اﻟﺨﺮج ‪ outp‬اﻟﺘﻲ ﻳﺮاد ﺗﻮﻟﻴﺪهﺎ اﻧﻄﻼﻗًﺎ ﻣﻦ إﺷﺎرة‬ ‫ﻧﺒﻀﺎت اﻟﺴﺎﻋﺔ ‪ ) clk‬ب ( اﻹﺷﺎرﺗﺎن اﻟﻮﺳﻴﻄﻴﺘﺎن ‪ out1‬و ‪( outp = out1 AND out2 ) out2‬‬


1 --------------------------------------------------------------------------------------2 ENTITY signal_gen IS 3 PORT ( clk : IN BIT; 4 outp : OUT BIT); 5 END signal_gen; 6 --------------------------------------------------------------------------------------7 ARCHITECTURE fsm OF signal_gen IS 8 TYPE state IS ( one, two, three ); 9 SIGNAL pr_state1, nx_state1 : state; 10 SIGNAL pr_state2, nx_state2 : state; 11 SIGNAL out1, out2 : BIT; 12 BEGIN 13 -------------------- Lower section of machine #1 : -------------------14 PROCESS ( clk ) 15 BEGIN 16 IF ( clk'EVENT AND clk = '1' ) THEN 17 pr_state1 <= nx_state1; 18 END IF; 19 END PROCESS; 20 -------------------- Lower section of machine #2 : -------------------21 PROCESS ( clk ) 22 BEGIN 23 IF ( clk'EVENT AND clk = '0' ) THEN 24 pr_state2 <= nx_state2; 25 END IF; 26 END PROCESS; 27 -------------------- Upper section of machine #1 : -------------------28 PROCESS ( pr_state1 ) 29 BEGIN 30 CASE pr_state1 IS 31 WHEN one => 32 out1 <= '0'; 33 nx_state1 <= two; 34 WHEN two => 35 out1 <= '1'; 36 nx_state1 <= three; 37 WHEN three => 38 out1 <= '1'; 39 nx_state1 <= one; 40 END CASE; 41 END PROCESS; 42 -------------------- Upper section of machine #2 : -------------------43 PROCESS ( pr_state2 ) 44 BEGIN 45 CASE pr_state2 IS


46 WHEN one => 47 out2 <= '1'; 48 nx_state2 <= two; 49 WHEN two => 50 out2 <= '0'; 51 nx_state2 <= three; 52 WHEN three => 53 out2 <= '1'; 54 nx_state2 <= one; 55 END CASE; 56 END PROCESS; 57 outp <= out1 AND out2; 58 END fsm; 59 --------------------------------------------------------------------------------------

(٦-٨) ‫ ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻠﻤﺜﺎل‬: (١٣-٨) ‫اﻟﺸﻜﻞ‬

= = = = = ‫= = = = = ﻧﻬﺎﻳﺔ اﻟﺠﻠﺴﺔ اﻟﺜﺎﻣﻨﺔ‬

VHDL 07  

Finite State Machines Design in VHDL

VHDL 07  

Finite State Machines Design in VHDL

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