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‫اﻟﺠﻤﻬﻮرﻳﺔ اﻟﻌﺮﺑﻴﺔ اﻟﺴﻮرﻳﺔ‬ ‫وزارة اﻟﺘﻌﻠﻴﻢ اﻟﻌﺎﻟﻲ‬ ‫ﺟﺎﻣﻌﺔ ﺣﻠﺐ – آﻠﻴﺔ اﻟﻬﻨﺪﺳﺔ اﻟﻜﻬﺮﺑﺎﺋﻴﺔ واﻻﻟﻜﺘﺮوﻧﻴﺔ‬ ‫ﻗﺴﻢ هﻨﺪﺳﺔ اﻟﺤﻮاﺳﻴﺐ – ﻣﺨﺒﺮ اﻟﺤﺎﺳﺒﺎت‬ ‫إﻋﺪاد اﻟﻤﻬﻨﺪس ‪ :‬أﺳﺎﻣﺔ ﻋﺰﻳﺰ‬

‫ﻣﻠﺨﺺ اﻟﺠﻠﺴﺔ اﻟﺮاﺑﻌﺔ ﻟﻄﻼب اﻟﺴﻨﺔ اﻟﺜﺎﻟﺜﺔ ‪ :‬ﺣﺎﺳﺒﺎت ‪ +‬اﻟﻜﺘﺮون‬ ‫اﻟﻤﻌﺎﻣﻼت واﻟﺨﺼﺎﺋﺺ ‪Operators and Attributes‬‬

‫اﻟﻔﺼﻞ اﻟﺪراﺳﻲ اﻷول‬ ‫‪٢٠١٠ - ٢٠٠٩‬‬


‫إن اﻟﻐﺎﻳﺔ ﻣﻦ هﺬﻩ اﻟﺠﻠﺴﺔ ﺑﺎﻹﺿ ﺎﻓﺔ إﻟ ﻰ اﻟﺠﻠﺴ ﺎت اﻟﺴ ﺎﺑﻘﺔ ه ﻲ ﻋ ﺮض اﻟﻤﺒ ﺎدئ اﻷﺳﺎﺳ ﻴﺔ ‪Basic‬‬ ‫‪ Foundations‬ﻟﻠﻐ ﺔ ‪ VHDL‬وﺑﺎﻟﺘ ﺎﻟﻲ ﻓ ﻲ اﻟﺠﻠﺴ ﺔ اﻟﻘﺎدﻣ ﺔ ﻧﺴ ﺘﻄﻴﻊ اﻟﺒ ﺪء ﺑﺎﻟﺘﻌﺎﻣ ﻞ ﻣ ﻊ ﺗﺼ ﺎﻣﻴﻢ‬ ‫دارات ﻓﻌﻠﻴ ﺔ ‪ . Actual Circuit Designs‬ﻓ ﻲ اﻟﻮاﻗ ﻊ ﻣ ﻦ اﻟﻤﺴ ﺘﺤﻴﻞ – أو ﻋﻠ ﻰ اﻷﻗ ﻞ ﺳ ﺘﻜﻮن‬ ‫اﻹﻧﺘﺎﺟﻴﺔ ﻣﻨﺨﻔﻀﺔ – آﺘﺎﺑﺔ أﻳﺔ ﺷﻴﻔﺮة ﺑﻔﻌﺎﻟﻴﺔ دون أن ﻧﺘ ﻮﻟﻰ ﻓ ﻲ اﻟﺒ ﺪء ﻣﻬﻤ ﺔ ﻓﻬ ﻢ أﻧ ﻮاع اﻟﻤﻌﻄﻴ ﺎت‬ ‫‪ Data Types‬واﻟﻤﻌﺎﻣﻼت ‪ Operators‬واﻟﺨﺼﺎﺋﺺ ‪ Attributes‬ﺑﺸﻜﻞ ﺟﻴﺪ ‪.‬‬ ‫ﺗﺸﻜﻞ اﻟﻤﻌﺎﻣﻼت واﻟﺨﺼﺎﺋﺺ ﻻﺋﺤﺔ ﻃﻮﻳﻠﺔ ﻧﺴﺒﻴًﺎ ﻣ ﻦ اﻟﺒﻨ ﻰ ﻓ ﻲ ﻟﻐ ﺔ ‪ VHDL‬واﻟﺘ ﻲ ﺗ ﺪرس ﻋ ﺎد ًة‬ ‫ﺑﺸﻜﻞ ﻣﻨﻔﺼﻞ ‪ .‬إﻻ أﻧﻪ ﻗﺪ ﺗﻢ ﺗﺠﻤﻴﻌﻬﺎ ﻣﻌًﺎ ﻓﻲ ﺟﻠﺴﺔ واﺣﺪة ﺑﻬﺪف ﺗﺰوﻳﺪ رؤﻳﺔ آﺎﻣﻠﺔ وأآﺜﺮ ﺗﻨﺎﺳﻘًﺎ ‪.‬‬ ‫ﻓﻲ ﻧﻬﺎﻳﺔ اﻟﺠﻠﺴﺔ ﺳﻴﺘﻢ ﻋﺮض ﺑﻀﻌﺔ أﻣﺜﻠﺔ ﺗﺼﻤﻴﻤﻴﺔ ‪ .‬ﻣﻊ ذﻟﻚ ‪ ،‬ﻧﻈﺮًا ﻟﺤﻘﻴﻘﺔ أن ه ﺬﻩ اﻟﺠﻠﺴ ﺔ ﺗﺒﻘ ﻰ‬ ‫ﻣﺨﺼﺼ ﺔ ﻟﻌ ﺮض " ﻣﺒ ﺎدئ " ‪ Foundations‬ﻓﻘ ﻂ ﻓ ﺈن اﻷﻣﺜﻠ ﺔ ه ﻲ ﺗﻮﺿ ﻴﺤﻴﺔ ﻓﺤﺴ ﺐ آﻤ ﺎ ﻓ ﻲ‬ ‫اﻟﺠﻠﺴﺎت اﻟﺴﺎﺑﻘﺔ ‪ .‬آﻤ ﺎ ذآﺮﻧ ﺎ أﻋ ﻼﻩ ﻓﺈﻧﻨ ﺎ ﺳ ﻨﺒﺪأ اﻟﺘﻌﺎﻣ ﻞ ﻣ ﻊ اﻟﺘﺼ ﺎﻣﻴﻢ اﻟﺤﻘﻴﻘﻴ ﺔ اﺑﺘ ﺪا ًء ﻣ ﻦ اﻟﺠﻠﺴ ﺔ‬ ‫اﻟﻘﺎدﻣﺔ ‪.‬‬ ‫‪ -١-٤‬اﻟﻤﻌﺎﻣﻼت ‪Operators‬‬ ‫ﺗﺰود ﻟﻐﺔ ‪ VHDL‬ﻋﺪة أﻧﻮاع ﻣﻦ اﻟﻤﻌﺎﻣﻼت اﻟﻤﻌﺮﻓﺔ ﻣﺴﺒﻘًﺎ ‪:‬‬ ‫ ﻣﻌﺎﻣﻼت اﻹﺳﻨﺎد ‪Assignment Operarors‬‬‫ اﻟﻤﻌﺎﻣﻼت اﻟﻤﻨﻄﻘﻴﺔ ‪Logical Operators‬‬‫ اﻟﻤﻌﺎﻣﻼت اﻟﺤﺴﺎﺑﻴﺔ ‪Arithmetic Operators‬‬‫ ﻣﻌﺎﻣﻼت اﻟﻤﻘﺎرﻧﺔ ) اﻟﻌﻼﺋﻘﻴﺔ ( ‪Relational Operators‬‬‫ ﻣﻌﺎﻣﻼت اﻹزاﺣﺔ ‪Shift Operators‬‬‫ ﻣﻌﺎﻣﻼت اﻟﻀﻢ ‪Concatenation Operators‬‬‫ﻓﻴﻤﺎ ﻳﻠﻲ ﺳﻴﺘﻢ وﺻﻒ آﻞ ﻓﺌﺔ ﻣﻦ هﺬﻩ اﻟﻔﺌﺎت ‪.‬‬ ‫ﻻ‪ .‬ﻣﻌﺎﻣﻼت اﻹﺳﻨﺎد ‪Assignment Operators :‬‬ ‫أو ً‬ ‫ﺗﺴ ﺘﺨﺪم ه ﺬﻩ اﻟﻤﻌ ﺎﻣﻼت ﻹﺳ ﻨﺎد اﻟﻘ ﻴﻢ إﻟ ﻰ اﻹﺷ ﺎرات ‪ Signals‬أو اﻟﻤﺘﻐﻴ ﺮات ‪ Variables‬أو‬ ‫اﻟﺜﻮاﺑﺖ ‪ Constants‬وهﻲ ‪:‬‬ ‫اﻟﻤﻌﺎﻣﻞ =< ﻳﺴﺘﺨﺪم ﻹﺳﻨﺎد ﻗﻴﻤﺔ ﻣﺎ إﻟﻰ إﺷﺎرة ‪. SIGNAL‬‬ ‫اﻟﻤﻌﺎﻣ ﻞ =‪ :‬ﻳﺴ ﺘﺨﺪم ﻹﺳ ﻨﺎد ﻗﻴﻤ ﺔ ﻣ ﺎ إﻟ ﻰ ﻣﺘﻐﻴ ﺮ ‪ VARIABLE‬أو ﺛﺎﺑ ﺖ ‪ CONSTANT‬أو‬ ‫ﺛﺎﺑﺖ ﻋﺎم ‪ . GENERIC‬آﻤﺎ ﻳﺴﺘﺨﺪم هﺬا اﻟﻤﻌﺎﻣﻞ أﻳﻀًﺎ ﻟﺘﻌﻴﻴﻦ اﻟﻘﻴﻢ اﻻﺑﺘﺪاﺋﻴﺔ ‪Initial Values‬‬ ‫اﻟﻤﻌﺎﻣ ﻞ >= ﻳﺴ ﺘﺨﺪم ﻹﺳ ﻨﺎد اﻟﻘ ﻴﻢ إﻟ ﻰ ﻋﻨﺎﺻ ﺮ ﺷ ﻌﺎع ﻣﻨﻔ ﺮدة ‪Individual Vector‬‬ ‫‪ Elements‬آﻤﺎ ﻳﺴﺘﺨﺪم ﻣﻊ اﻟﻜﻠﻤﺔ اﻟﻤﺤﺠﻮزة ‪. OTHERS‬‬ ‫ﻣﺜﺎل ‪ :‬ﻟﻨﻌﺘﺒﺮ أﻧﻪ ﻟﺪﻳﻨﺎ اﻟﺘﺼﺮﻳﺤﺎت اﻟﺘﺎﻟﻴﺔ ﻋﻦ إﺷﺎرات وﻣﺘﻐﻴﺮات آﻤﺎ ﻳﻠﻲ ‪:‬‬ ‫‪-- Leftmost bit is MSB‬‬ ‫‪-- Rightmost bit is MSB‬‬

‫;‪SIGNAL x : STD_LOGIC‬‬ ‫;)‪VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0‬‬ ‫;)‪SIGNAL w: STD_LOGIC_VECTOR(0 TO 7‬‬

‫ﻋﻨﺪهﺎ ﻓﺈن ﻋﻤﻠﻴﺎت اﻹﺳﻨﺎد اﻟﺘﺎﻟﻴﺔ آﻠﻬﺎ ﺻﺤﻴﺤﺔ ‪:‬‬ ‫;'‪x <= '1‬‬ ‫"=<" ‪-- '1' is assigned to SIGNAL x using‬‬ ‫;"‪y := "0000‬‬ ‫"=‪-- "0000" is assigned to VARIABLE y using ":‬‬ ‫;"‪w <= "10000000‬‬ ‫'‪-- LSB is '1', the others are '0‬‬ ‫;)'‪w <= (0 =>'1', OTHERS =>'0‬‬ ‫'‪-- LSB is '1', the others are '0‬‬ ‫ﺛﺎﻧﻴًﺎ‪ .‬اﻟﻤﻌﺎﻣﻼت اﻟﻤﻨﻄﻘﻴﺔ ‪Logical Operators :‬‬ ‫ﺗﺴﺘﺨﺪم ﻹﻧﺠﺎز اﻟﻌﻤﻠﻴﺎت اﻟﻤﻨﻄﻘﻴﺔ ‪ . Logical Operations‬اﻟﻤﻌﻄﻴﺎت ﻳﺠﺐ أن ﺗﻜﻮن ﻣ ﻦ اﻟﻨ ﻮع‬ ‫‪ BIT‬أو ‪ STD_LOGIC‬أو ‪ ) STD_ULOGIC‬أو ﺑﺸﻜﻞ واﺿﺢ اﻣﺘﺪادات هﺬﻩ اﻷﻧ ﻮاع ﻋﻠ ﻰ‬


‫ﺐ أي ‪ BIT_VECTOR‬و ‪ STD_LOGIC_VECTOR‬و‬ ‫اﻟﺘﺮﺗﻴ‬ ‫‪ . ( STD_ULOGIC_VECTOR‬إن اﻟﻤﻌﺎﻣﻼت اﻟﻤﻨﻄﻘﻴﺔ هﻲ ‪:‬‬ ‫‪ : NOT‬ﻋﻤﻠﻴﺔ اﻟﻨﻔﻲ اﻟﻤﻨﻄﻘﻲ‬ ‫‪ : AND‬ﻋﻤﻠﻴﺔ اﻟﺠﺪاء اﻟﻤﻨﻄﻘﻲ‬ ‫‪ : OR‬ﻋﻤﻠﻴﺔ اﻟﺠﻤﻊ اﻟﻤﻨﻄﻘﻲ‬ ‫‪ : NAND‬ﻋﻤﻠﻴﺔ اﻟﺠﺪاء اﻟﻤﻨﻄﻘﻲ اﻟﻤﻨﻔﻲ‬ ‫‪ : NOR‬ﻋﻤﻠﻴﺔ اﻟﺠﻤﻊ اﻟﻤﻨﻄﻘﻲ اﻟﻤﻨﻔﻲ‬ ‫‪ : XOR‬ﻋﻤﻠﻴﺔ اﻟﺠﻤﻊ اﻟﻤﻨﻄﻘﻲ اﻟﻤﻘﺼﻮر ‪Exclusive-OR‬‬ ‫‪ : XNOR‬ﻋﻤﻠﻴﺔ اﻟﺠﻤﻊ اﻟﻤﻨﻄﻘﻲ اﻟﻤﻘﺼﻮر اﻟﻤﻨﻔﻲ‬ ‫ﻣﻼﺣﻈﺎت ‪ :‬إن اﻟﻤﻌﺎﻣﻞ ‪ NOT‬ﻳﻤﺘﻠﻚ اﻷوﻟﻮﻳﺔ ﻋﻠﻰ اﻟﻤﻌﺎﻣﻼت اﻷﺧﺮى آﻤﺎ أن اﻟﻤﻌﺎﻣﻞ ‪XNOR‬‬ ‫ﻗﺪ ﺗﻤﺖ إﺿﺎﻓﺘﻪ ﻓﻲ اﻟﻨﺴﺨﺔ ‪. VHDL-93‬‬ ‫أﻣﺜﻠﺔ ‪Examples :‬‬ ‫;‪y <= NOT a AND b‬‬ ‫)‪-- (a'.b‬‬ ‫;)‪y <= NOT (a AND b‬‬ ‫')‪-- (a.b‬‬ ‫;‪y <= a NAND b‬‬ ‫')‪-- (a.b‬‬ ‫ﺛﺎﻟﺜًﺎ‪ .‬اﻟﻤﻌﺎﻣﻼت اﻟﺤﺴﺎﺑﻴﺔ ‪Arithmetic Operations :‬‬ ‫ﺗﺴﺘﺨﺪم ﻹﻧﺠﺎز اﻟﻌﻤﻠﻴ ﺎت اﻟﺤﺴ ﺎﺑﻴﺔ ‪ . Arithmetic Operations‬اﻟﻤﻌﻄﻴ ﺎت ﻳﺠ ﺐ أن ﺗﻜ ﻮن ﻣ ﻦ‬ ‫اﻟﻨ ﻮع ‪ INTEGER‬أو ‪ SIGNED‬أو ‪ UNSIGNED‬أو ‪ ) REAL‬ﺗ ﺬآﺮ ﺑ ﺄن اﻟﻨ ﻮع اﻷﺧﻴ ﺮ‬ ‫‪ REAL‬ﻻ ﻳﻤﻜﻦ أن ﻳﺘﻢ ﺗﺮآﻴﺒﻪ ﺑﺸ ﻜﻞ ﻣﺒﺎﺷ ﺮ ‪ . ( Not Synthesized Directly‬أﻳﻀ ًﺎ ‪ ،‬إذا ﺗ ﻢ‬ ‫اﺳ ﺘﺨﺪام إﺣ ﺪى اﻟﺤ ﺰﻣﺘﻴﻦ ‪ std_logic_signed‬أو ‪ std_logic_unsigned‬ﻣ ﻦ اﻟﻤﻜﺘﺒ ﺔ ‪ieee‬‬ ‫ﻓﺈﻧ ﻪ ﻋﻨ ﺪهﺎ ﻳﻤﻜ ﻦ أن ﻧﺴ ﺘﺨﺪم ﻧ ﻮع اﻟﻤﻌﻄﻴ ﺎت ‪ STD_LOGIC_VECTOR‬ﺑﺸ ﻜﻞ ﻣﺒﺎﺷ ﺮ ﻓ ﻲ‬ ‫ﻋﻤﻠﻴﺘﻲ اﻟﺠﻤﻊ ‪ Addition‬واﻟﻄﺮح ‪ ) Subtraction‬آﻤﺎ رأﻳﻨﺎ ﻓﻲ اﻟﺠﻠﺴﺔ اﻟﺴﺎﺑﻘﺔ ( ‪.‬‬ ‫‪ : +‬ﻋﻤﻠﻴﺔ اﻟﺠﻤﻊ ‪Addition‬‬ ‫ ‪ :‬ﻋﻤﻠﻴﺔ اﻟﻄﺮح ‪Subtraction‬‬‫* ‪ :‬ﻋﻤﻠﻴﺔ اﻟﻀﺮب ‪Multiplication‬‬ ‫‪ : /‬ﻋﻤﻠﻴﺔ اﻟﻘﺴﻤﺔ ‪Division‬‬ ‫** ‪ :‬ﻋﻤﻠﻴﺔ اﻟﺮﻓﻊ إﻟﻰ ﻗﻮة ‪Exponentiation‬‬ ‫‪ : MOD‬ﻋﻤﻠﻴﺔ ﺗﻌﻴﺪ ﺑﺎﻗﻲ ﻗﺴﻤﺔ ‪ y/x‬ﻣﻊ إﺷﺎرة ‪( Modulus ) x‬‬ ‫‪ : REM‬ﻋﻤﻠﻴﺔ ﺗﻌﻴﺪ ﺑﺎﻗﻲ ﻗﺴﻤﺔ ‪ y/x‬ﻣﻊ إﺷﺎرة ‪( Remainder ) y‬‬ ‫‪ : ABS‬اﻟﻘﻴﻤﺔ اﻟﻤﻄﻠﻘﺔ ‪Absolute Value‬‬ ‫ﻻ ﺗﻮﺟ ﺪ ﻗﻴ ﻮد ﺧﺎﺻ ﺔ ﺑﻌﻤﻠﻴ ﺔ اﻟﺘﺮآﻴ ﺐ ﻓﻴﻤ ﺎ ﻳﺘﻌﻠ ﻖ ﺑﻌﻤﻠﻴﺘ ﻲ اﻟﺠﻤ ﻊ ‪ Addition‬واﻟﻄ ﺮح‬ ‫‪ ، Subtraction‬واﻷﻣﺮ ﻧﻔﺴﻪ ﺻ ﺤﻴﺢ ﻋﻤﻮﻣ ًﺎ ﻣ ﻦ أﺟ ﻞ ﻋﻤﻠﻴ ﺔ اﻟﻀ ﺮب ‪ . Multiplication‬ﻣ ﻦ‬ ‫أﺟ ﻞ ﻋﻤﻠﻴ ﺔ اﻟﻘﺴ ﻤﺔ ‪ Division‬ﻓﺈﻧ ﻪ ﻓﻘ ﻂ اﻟﻘﻮاﺳ ﻢ ﻣ ﻦ ﻗ ﻮى اﻟﻌ ﺪد ‪ 2‬ﻣﺴ ﻤﻮﺣﺔ ) ﻷن اﻟﻌﻤﻠﻴ ﺔ ه ﻲ‬ ‫إزاﺣﺔ ‪ . ( Shift Operation‬ﻣﻦ أﺟﻞ ﻋﻤﻠﻴﺔ اﻟﺮﻓﻊ إﻟﻰ ﻗﻮة ‪ Exponentiation‬ﻓﺈن اﻟﻘﻴﻢ اﻟﺜﺎﺑﺘ ﺔ‬ ‫‪ Static Values‬ﻓﻘ ﻂ ﻣ ﻦ أﺟ ﻞ آ ﻞ ﻣ ﻦ اﻷﺳ ﺎس ‪ Base‬واﻷس ‪ Exponent‬ﻣﻘﺒﻮﻟ ﺔ ‪ .‬أﻣ ﺎ ﻓﻴﻤ ﺎ‬ ‫ﻳﺘﻌﻠﻖ ﺑﻤﻌﺎﻣﻠﻲ ‪ MOD‬و ‪ REM‬ﻓﺈن ‪ y mod x‬ﺗﻌﻴﺪ ﺑﺎﻗﻲ ﻗﺴﻤﺔ ‪ y/x‬ﻣﻊ إﺷﺎرة ‪ x‬ﻓﻲ ﺣﻴﻦ أن‬ ‫‪ y rem x‬ﺗﻌﻴ ﺪ ﺑ ﺎﻗﻲ ﻗﺴ ﻤﺔ ‪ y/x‬ﻣ ﻊ إﺷ ﺎرة ‪ . y‬أﺧﻴ ﺮًا ‪ ،‬اﻟﻤﻌﺎﻣ ﻞ ‪ abs ( x ) ) abs‬ﻋﻠ ﻰ ﺳ ﺒﻴﻞ‬ ‫اﻟﻤﺜﺎل ( ﻳﻌﻴﺪ اﻟﻘﻴﻤﺔ اﻟﻤﻄﻠﻘﺔ ﻟـ ‪ . x‬ﻣﻊ ﺗﻘﺪﻳﺮ ﻗﻴﻤﺔ اﻟﻤﻌ ﺎﻣﻼت اﻟﺜﻼﺛ ﺔ اﻷﺧﻴ ﺮة )‪(mod, rem, abs‬‬ ‫إﻻ أﻧﻬ ﺎ ﻋﻤﻮﻣ ًﺎ ﻣ ﺎ ﺗﻜ ﻮن ﻏﻴ ﺮ ﻣﺪﻋﻮﻣ ﺔ ﻣ ﻦ ﻗﺒ ﻞ ﻋﻤﻠﻴ ﺔ اﻟﺘﺮآﻴ ﺐ ‪ No Synthesis Support‬أو‬ ‫ﻣﺪﻋﻮﻣﺔ ﺑﺸﻜﻞ ﺑﺴﻴﻂ وﻣﻘﻴﺪ ‪.‬‬ ‫راﺑﻌًﺎ‪ .‬ﻣﻌﺎﻣﻼت اﻟﻤﻘﺎرﻧﺔ ‪Comparison Operators :‬‬


‫ﺗﺴ ﺘﺨﺪم ه ﺬﻩ اﻟﻤﻌ ﺎﻣﻼت ﻟﻠﻤﻘﺎرﻧ ﺔ ‪ . Comparison‬ﻳﻤﻜ ﻦ أن ﺗﻜ ﻮن اﻟﻤﻌﻄﻴ ﺎت ﻣ ﻦ أي ﻧ ﻮع ﻣ ﻦ‬ ‫اﻷﻧﻮاع اﻟﻤﻌﺮوﺿﺔ ﻣﺴﺒﻘًﺎ ‪ .‬إن اﻟﻤﻌﺎﻣﻼت اﻟﻌﻼﺋﻘﻴﺔ ‪ Relational Operators‬أو ﻣﺎ ﻳﻌ ﺮف ﺑﺎﺳ ﻢ‬ ‫ﻣﻌﺎﻣﻼت اﻟﻤﻘﺎرﻧﺔ ‪ Comparison Operators‬هﻲ ‪:‬‬ ‫= ‪ :‬ﻣﻌﺎﻣﻞ اﻟﺘﺴﺎوي ‪Equal To‬‬ ‫=‪ : /‬ﻣﻌﺎﻣﻞ ﻋﺪم اﻟﺘﺴﺎوي ‪Not Equal To‬‬ ‫< ‪ :‬ﻣﻌﺎﻣﻞ أﺻﻐﺮ ﺗﻤﺎﻣًﺎ ‪Less Than‬‬ ‫> ‪ :‬ﻣﻌﺎﻣﻞ أآﺒﺮ ﺗﻤﺎﻣًﺎ ‪Greater Than‬‬ ‫=< ‪ :‬ﻣﻌﺎﻣﻞ أﺻﻐﺮ ﻣﻦ أو ﻳﺴﺎوي ‪Less Than Or Equal To‬‬ ‫=> ‪ :‬ﻣﻌﺎﻣﻞ أآﺒﺮ ﻣﻦ أو ﻳﺴﺎوي ‪Greater Than Or Equal To‬‬ ‫ﺧﺎﻣﺴًﺎ‪ .‬ﻣﻌﺎﻣﻼت اﻹزاﺣﺔ ‪Shift Operators :‬‬ ‫ﺗﺴﺘﺨﺪم ه ﺬﻩ اﻟﻤﻌ ﺎﻣﻼت ﻣ ﻦ أﺟ ﻞ إزاﺣ ﺔ اﻟﻤﻌﻄﻴ ﺎت ‪ . Shifting Data‬ﺗ ﻢ إدراج ه ﺬﻩ اﻟﻤﻌ ﺎﻣﻼت‬ ‫ﻓﻲ اﻟﻨﺴﺨﺔ ‪. VHDL-93‬‬ ‫إن اﻟﺼﻴﻐﺔ اﻟﻘﻮاﻋﺪﻳﺔ ‪ Syntax‬ﻟﻬﺬﻩ اﻟﻤﻌﺎﻣﻼت هﻲ آﺎﻟﺘﺎﻟﻲ ‪:‬‬ ‫> ‪< left operand > < shift operation > < right operand‬‬ ‫اﻟﻌﺎﻣﻞ اﻷﻳﺴ ﺮ ‪ Left Operand‬ﻳﺠ ﺐ أن ﻳﻜ ﻮن ﻣ ﻦ ﻧ ﻮع اﻟﻤﻌﻄﻴ ﺎت ‪ BIT_VECTOR‬ﺣﺘﻤ ًﺎ ‪.‬‬ ‫ﻓﻲ ﺣﻴﻦ أن اﻟﻌﺎﻣﻞ اﻷﻳﻤ ﻦ ‪ Right Operand‬ﻳﺠ ﺐ أن ﻳﻜ ﻮن ﻣ ﻦ ﻧ ﻮع اﻟﻤﻌﻄﻴ ﺎت ‪INTEGER‬‬ ‫) وﻧﻨ ﻮﻩ هﻨ ﺎ أن اﻹﺷ ﺎرة ‪ +‬أو اﻹﺷ ﺎرة – ﻓ ﻲ ﺑﺪاﻳ ﺔ ه ﺬا اﻟﻌﺎﻣ ﻞ ﻣﻘﺒﻮﻟ ﺔ ﺑﺤﻴ ﺚ أﻧ ﻪ ﻋﻨ ﺪ اﺳ ﺘﺨﺪام‬ ‫اﻹﺷ ﺎرة – ﻓ ﺈن اﺗﺠ ﺎﻩ اﻹزاﺣ ﺔ ﻳﻜ ﻮن ﻣﻌﻜﻮﺳ ًﺎ !!! ( ‪ .‬إن ﻣﻌ ﺎﻣﻼت اﻹزاﺣ ﺔ ‪Shift Operators‬‬ ‫هﻲ ‪:‬‬ ‫‪ Shift Left Logic : SLL‬اﻟﻤﻮاﻗﻊ اﻟﺸﺎﻏﺮة ﻣﻦ ﺟﻬﺔ اﻟﻴﻤﻴﻦ ﺗﺄﺧﺬ اﻟﻘﻴﻤﺔ '‪. '0‬‬ ‫‪ Shift Right Logic : SRL‬اﻟﻤﻮاﻗﻊ اﻟﺸﺎﻏﺮة ﻣﻦ ﺟﻬﺔ اﻟﻴﺴﺎر ﺗﺄﺧﺬ اﻟﻘﻴﻤﺔ '‪. '0‬‬ ‫‪ Shift Left Arithmetic : SLA‬اﻟﻤﻮاﻗ ﻊ اﻟﺸ ﺎﻏﺮة ﻣ ﻦ ﺟﻬ ﺔ اﻟﻴﻤ ﻴﻦ ﺗﺄﺧ ﺬ ﻧﻔ ﺲ ﻗﻴﻤ ﺔ اﻟﺨﺎﻧ ﺔ‬ ‫اﻟﻤﻮﺟﻮدة ﻓﻲ أﻗﺼﻰ اﻟﻴﻤﻴﻦ ﻗﺒﻞ ﻋﻤﻠﻴﺔ اﻹزاﺣﺔ ) إزاﺣﺔ ﺣﺴﺎﺑﻴﺔ ( ‪.‬‬ ‫‪ Shift Right Arithmetic : SRA‬اﻟﻤﻮاﻗ ﻊ اﻟﺸ ﺎﻏﺮة ﻣ ﻦ ﺟﻬ ﺔ اﻟﻴﺴ ﺎر ﺗﺄﺧ ﺬ ﻧﻔ ﺲ ﻗﻴﻤ ﺔ اﻟﺨﺎﻧ ﺔ‬ ‫اﻟﻤﻮﺟﻮدة ﻓﻲ أﻗﺼﻰ اﻟﻴﺴﺎر ﻗﺒﻞ ﻋﻤﻠﻴﺔ اﻹزاﺣﺔ ) إزاﺣﺔ ﺣﺴﺎﺑﻴﺔ ( ‪.‬‬ ‫‪ Rotate Left : ROL‬دوران ﺑﺎﺗﺠﺎﻩ اﻟﻴﺴﺎر‬ ‫‪ Rotate right : ROR‬دوران ﺑﺎﺗﺠﺎﻩ اﻟﻴﻤﻴﻦ‬ ‫أﻣﺜﻠﺔ ‪Examples :‬‬ ‫====================================‬ ‫;)‪SUBTYPE byte IS BIT_VECTOR(7 DOWNTO 0‬‬ ‫‪--New type byte‬‬ ‫;”‪CONSTANT MINUS_77 : byte := “10110011‬‬ ‫‪-- MINUS_77 = -77‬‬ ‫;‪CONSTANT MINUS_39 : byte := MINUS_77 sra 1‬‬ ‫‪--11011001‬‬ ‫;‪CONSTANT PLUS_89 : byte := MINUS_77 srl 1‬‬ ‫‪--01011001‬‬ ‫;‪CONSTANT PLUS_103 : byte := MINUS_77 rol 1‬‬ ‫‪--01100111‬‬ ‫====================================‬ ‫ﺳﺎدﺳًﺎ‪ .‬ﻣﻌﺎﻣﻞ اﻟﻀﻢ ‪Concatenation Operator :‬‬ ‫ﻳﻤﻜﻦ ﻟﻤﻌﺎﻣﻞ اﻟﻀﻢ & أن ﻳﺸﻜﻞ ﺷﻌﺎﻋًﺎ ‪ Vector‬اﻧﻄﻼﻗًﺎ ﻣﻦ ﺷﻌﺎﻋﻴﻦ ﻣﻦ ﻧﻔﺲ ﻧ ﻮع اﻟﻤﻌﻄﻴ ﺎت أو‬ ‫ﻣﻦ ﺷﻌﺎع وﺧﺎﻧﺔ ﻣﻨﻔﺮدة ﻣﻦ ﻧﻔﺲ ﻧﻮع ﻣﻌﻄﻴﺎت ﺧﺎﻧﺎت اﻟﺸﻌﺎع وذﻟﻚ آﻤﺎ ﻓﻲ اﻷﻣﺜﻠﺔ اﻟﺘﺎﻟﻴﺔ ‪:‬‬ ‫‪--10110011‬‬ ‫‪--01011001‬‬

‫;)‪SUBTYPE byte IS BIT_VECTOR(7 DOWNTO 0‬‬ ‫;”‪CONSTANT MINUS_77 : byte := “101” & “10011‬‬ ‫;’‪CONSTANT PLUS_89 : byte := “0101100” & ‘1‬‬


Pre-Defined Attributes : ‫ اﻟﺨﺼﺎﺋﺺ اﻟﻤﻌﺮﻓﺔ ﻣﺴﺒﻘًﺎ‬-٢-٤ ‫ إﻟ ﻰ ﻧ ﻮﻋﻴﻦ‬VHDL ‫ ﻓ ﻲ ﻟﻐ ﺔ‬Pre-Defined Attributes ‫ﺗﻘﺴ ﻢ اﻟﺨﺼ ﺎﺋﺺ اﻟﻤﻌﺮﻓ ﺔ ﻣﺴ ﺒﻘًﺎ‬ Data Attributes ‫ ﺧﺼﺎﺋﺺ اﻟﻤﻌﻄﻴﺎت‬- : ‫أﺳﺎﺳﻴﻴﻦ هﻤﺎ‬ Signal Attributes ‫ ﺧﺼﺎﺋﺺ اﻹﺷﺎرة‬: ‫ﻓﻴﻤﺎ ﻳﻠﻲ ﻋﺮض ﻟﻜﻞ ﻣﻦ هﺬﻳﻦ اﻟﻨﻮﻋﻴﻦ‬ Data Attributes : ‫ﻻ – ﺧﺼﺎﺋﺺ اﻟﻤﻌﻄﻴﺎت‬ ً ‫أو‬ : ‫ واﻟﻘﺎﺑﻠﺔ ﻟﻠﺘﺮآﻴﺐ هﻲ اﻟﺘﺎﻟﻴﺔ‬VHDL ‫إن ﺧﺼﺎﺋﺺ اﻟﻤﻌﻄﻴﺎت اﻟﻤﻌﺮﻓﺔ ﻣﺴﺒﻘًﺎ ﻓﻲ ﻟﻐﺔ‬ - d’LOW: Returns lower array index - d’HIGH: Returns upper array index - d’LEFT: Returns leftmost array index - d’RIGHT: Returns rightmost array index - d’LENGTH: Returns vector size - d’RANGE: Returns vector range - d’REVERSE_RANGE: Returns vector range in reverse order Example : ‫ﻣﺜﺎل‬ : ‫ﻟﻨﻌﺘﺒﺮ اﻹﺷﺎرة اﻟﺘﺎﻟﻴﺔ‬ SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0); : ‫ﻋﻨﺪهﺎ ﻓﺈن‬ d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0, d'LENGTH=8, d'RANGE=(7 downto 0), d'REVERSE_RANGE=(0 to 7). Another Example : ‫ﻣﺜﺎل ﺁﺧﺮ‬ : ‫ﻟﻨﻌﺘﺒﺮ اﻹﺷﺎرة اﻟﺘﺎﻟﻴﺔ‬ SIGNAL x: STD_LOGIC_VECTOR (0 TO 7); : ‫ اﻷرﺑﻊ اﻟﺘﺎﻟﻴﺔ هﻲ ﻗﺎﺑﻠﺔ ﻟﻠﺘﺮآﻴﺐ وﻣﺘﻜﺎﻓﺌﺔ‬LOOP ‫ﻋﻨﺪهﺎ ﻓﺈن آﺎﻓﺔ ﺗﻌﻠﻴﻤﺎت اﻟﺤﻠﻘﺔ‬ FOR i IN RANGE (0 TO 7) LOOP ... FOR i IN x'RANGE LOOP ... FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ... FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ... : ‫ ﻋﻨﺪهﺎ‬Enumerated Type ‫إذا آﺎﻧﺖ اﻹﺷﺎرة ﻣﻦ ﻧﻮع اﻟﻤﻌﻄﻴﺎت اﻟﻤﻌﺪود‬ - d’VAL(pos): Returns value in the position specified - d’POS(value): Returns position of the value specified - d’LEFTOF(value): Returns value in the position to the left of the value specified - d’VAL(row, column): Returns value in the position specified; etc.

‫ ( ﺗﻜ ﻮن ﻏﻴ ﺮ‬Enumerated Type ) ‫ﻋﻤﻮﻣ ًﺎ ﻓ ﺈن ﺧﺼ ﺎﺋﺺ ه ﺬا اﻟﻨ ﻮع اﻷﺧﻴ ﺮ ﻣ ﻦ اﻟﻤﻌﻄﻴ ﺎت‬ Little Or No Synthesis ‫ﻣﺪﻋﻮﻣ ﺔ ﻣ ﻦ ﻗﺒ ﻞ ﻋﻤﻠﻴ ﺔ اﻟﺘﺮآﻴ ﺐ أو ذات دﻋ ﻢ ﺑﺴ ﻴﻂ وﻣﺤ ﺪود‬ . Support

- s’EVENT: - s’STABLE: - s’ACTIVE:

Signal Attributes : ‫ﺛﺎﻧﻴًﺎ – ﺧﺼﺎﺋﺺ اﻹﺷﺎرة‬ : ‫ ﻋﻨﺪهﺎ ﻓﺈن‬، s ‫ﻟﻨﻌﺘﺒﺮ إﺷﺎرة ﻣﺎ‬ Returns true when an event occurs on s Returns true if no event has occurred on s Returns true if s = ‘1’

- s’QUIET <time> :

Returns true if no event has occurred during the time specified


‫‪- s’LAST_EVENT:‬‬ ‫‪Returns the time elapsed since last event‬‬ ‫‪- s’LAST_ACTIVE:‬‬ ‫’‪Returns the time elapsed since last s = ‘1‬‬ ‫‪- s’LAST_VALUE:‬‬ ‫‪Returns the value of s before the last event; etc.‬‬ ‫ﺑ ﺎﻟﺮﻏﻢ ﻣ ﻦ أن أﻏﻠ ﺐ ﺧﺼ ﺎﺋﺺ اﻹﺷ ﺎرة ‪ Most Signal Attributes‬ه ﻲ ﻣ ﻦ أﺟ ﻞ أﻏ ﺮاض‬ ‫اﻟﻤﺤﺎآ ﺎة ﻓﻘ ﻂ ‪ Simulation Purposes Only‬ﻓ ﺈن اﻟﺨﺎﺻ ﺘﻴﻦ اﻷوﻟﻴ ﻴﻦ ﻓ ﻲ اﻟﻼﺋﺤ ﺔ أﻋ ﻼﻩ‬ ‫‪ EVENT‬و ‪ STABLE‬هﻤ ﺎ ﻗﺎﺑﻠﺘ ﺎن ﻟﻠﺘﺮآﻴ ﺐ ‪ ، Synthesizable‬ﻣ ﻊ اﻟﻌﻠ ﻢ أن اﻟﺨﺎﺻ ﺔ‬ ‫‪ s'EVENT‬هﻲ اﻷآﺜﺮ اﺳﺘﺨﺪاﻣًﺎ ﻋﻠﻰ اﻷﻏﻠﺐ ﻣﻦ هﺬﻩ اﻟﺨﺼﺎﺋﺺ ﻋﻠﻰ اﻹﻃﻼق !!!‬ ‫ﻣﺜﺎل ‪Example :‬‬ ‫ﻼ ﻣ ﻦ اﻟﺘﻌﻠﻴﻤ ﺎت اﻷرﺑﻌ ﺔ اﻟﻤﺒﻴﻨ ﺔ أدﻧ ﺎﻩ ﻗﺎﺑﻠ ﺔ ﻟﻠﺘﺮآﻴ ﺐ ‪ Synthesizable‬وﻣﻜﺎﻓﺌ ﺔ ﻟﻠﺤ ﺎﻻت‬ ‫إن آ ً‬ ‫اﻷﺧﺮى ‪ .‬هﺬﻩ اﻟﺘﻌﻠﻴﻤﺎت ﺗﻌﻴﺪ ‪ Return‬اﻟﻘﻴﻤﺔ ) ﺻﺤﻴﺢ ( ‪ TRUE‬ﻋﻨ ﺪﻣﺎ ﻳﻄ ﺮأ ﺣ ﺪث ﻣ ﺎ ‪Event‬‬ ‫) أي ﺗﻐﻴﻴﺮ ‪ ( Change‬ﻋﻠﻰ ﻗﻴﻤﺔ اﻹﺷﺎرة ‪ clk‬و ﻳﻜﻮن هﺬا اﻟﺤﺪث ) اﻟﺘﻐﻴﻴﺮ ( ﻣﻦ اﻟﻨﻮع اﻟﺼﺎﻋﺪ‬ ‫‪ ) Upward‬أي ﺟﺒﻬﺔ ﺻﺎﻋﺪة ( وﺑﻜﻠﻤﺎت أﺑﺴﻂ ‪ :‬ﻋﻨﺪ ﻇﻬﻮر ﺟﺒﻬﺔ ﺻﺎﻋﺪة ﻋﻠﻰ اﻹﺷﺎرة ‪. clk‬‬ ‫====================================‬ ‫‪IF (clk'EVENT AND clk='1')...‬‬ ‫‪-- EVENT attribute used with IF‬‬ ‫‪IF (NOT clk'STABLE AND clk='1')... -- STABLE attribute used with IF‬‬ ‫‪-- EVENT attribute used with WAIT‬‬

‫;)'‪WAIT UNTIL (clk'EVENT AND clk='1‬‬

‫‪IF RISING_EDGE(clk)...‬‬ ‫‪-- call to a function‬‬ ‫====================================‬ ‫‪ -٣-٤‬اﻟﺨﺼﺎﺋﺺ اﻟﻤﻌﺮﻓﺔ ﻣﻦ ﻗﺒﻞ اﻟﻤﺴﺘﺨﺪم ‪User-Defined Attributes :‬‬ ‫هﺬﻩ اﻟﻔﻘﺮة ﻏﻴﺮ ﻣﻄﻠﻮﺑﺔ وﻟﺬﻟﻚ ﻟﻢ ﺗﺘﺮﺟﻢ !!!‬ ‫‪ -٤-٤‬اﻟﺘﺤﻤﻴﻞ اﻟﺰاﺋﺪ ﻟﻠﻤﻌﺎﻣﻞ ‪Operator Overloading :‬‬ ‫ﻳﻤﻜﻦ ﻓﻲ ﻟﻐﺔ ‪ VHDL‬ﺗﻌﺮﻳﻒ ﻣﻌﺎﻣﻼت ﺟﺪﻳﺪة أو إﻋﺎدة إﻋﻄ ﺎء وﻇ ﺎﺋﻒ ﺟﺪﻳ ﺪة ﻟﻤﻌ ﺎﻣﻼت ﻣﻌﺮﻓ ﺔ‬ ‫ﻣﺴﺒﻘًﺎ ‪ .‬آﻤﺜﺎل ﻋﻠ ﻰ ذﻟ ﻚ ﻟﻨﻌﺘﺒ ﺮ اﻟﻤﻌ ﺎﻣﻼت اﻟﺤﺴ ﺎﺑﻴﺔ اﻟﻤﻌﺮﻓ ﺔ ﻣﺴ ﺒﻘًﺎ واﻟﺘ ﻲ ﺗ ﻢ ﻋﺮﺿ ﻬﺎ ﻓ ﻲ ﺑﺪاﻳ ﺔ‬ ‫اﻟﺠﻠﺴ ﺔ ‪ ) Pre-Defined Arithmetic Operators‬آﺎﻟﻤﻌ ﺎﻣﻼت ‪ ... +, -, *, /‬اﻟ ﺦ ( ‪ .‬ﺗﺤ ﺪد‬ ‫ه ﺬﻩ اﻟﻤﻌ ﺎﻣﻼت ﻋﻤﻠﻴ ﺎت ﺣﺴ ﺎﺑﻴﺔ ﺑ ﻴﻦ ﻣﻌﻄﻴ ﺎت ﻣ ﻦ أﻧ ﻮاع ﻣﺤ ﺪدة ) ‪ ( INTEGER‬ﻋﻠ ﻰ ﺳ ﺒﻴﻞ‬ ‫ﻼ ‪ ،‬اﻟﻤﻌﺎﻣﻞ اﻟﻤﺤﺪد ﻣﺴﺒﻘًﺎ "‪ "+‬ﻻ ﻳﺴﻤﺢ ﺑﺠﻤﻊ ﻣﻌﻄﻴﺎت ﻣﻦ ﻧﻮع ‪. BIT‬‬ ‫اﻟﻤﺜﺎل ‪ .‬ﻣﺜ ً‬ ‫ﻳﻤﻜﻨﻨﺎ ﻓﻲ ﻟﻐﺔ ‪ VHDL‬ﺗﻌﺮﻳﻒ ﻣﻌﺎﻣﻼﺗﻨﺎ اﻟﺨﺎﺻﺔ ﺑﺎﺳﺘﺨﺪام ﻧﻔ ﺲ اﻻﺳ ﻢ ‪ Name‬اﻟﻤﻌﻄ ﻰ ﻟﻤﻌﺎﻣ ﻞ‬ ‫ﻣﻌﺮف ﻣﺴﺒﻘًﺎ آﺎﻟﻤﻌﺎﻣﻞ "‪ "+‬ﻋﻠﻰ ﺳﺒﻴﻞ اﻟﻤﺜﺎل ‪.‬‬ ‫ﻣﺜﺎل ‪Example :‬‬ ‫ﻧﺮﻳﺪ أن ﻧﺴﺘﺨﺪم اﻟﻤﻌﺎﻣﻞ "‪ "+‬ﻟﺘﻌﺮﻳﻒ ﻧﻮع ﺟﺪﻳﺪ ﻣﻦ اﻟﺠﻤﻊ ﻳﺘﻴﺢ ﺟﻤ ﻊ ﻋ ﺪد ﺻ ﺤﻴﺢ ﻣ ﻊ ﺧﺎﻧ ﺔ ﻣ ﻦ‬ ‫ﻧﻮع ‪ . BIT‬ﺗﺴﻤﻰ هﺬﻩ اﻟﺘﻘﻨﻴﺔ ﺑﺎﻟﺘﺤﻤﻴﻞ اﻟﺰاﺋﺪ ﻟﻠﻤﻌﺎﻣﻞ ‪. Operator Overloading‬‬ ‫ﻓﻲ هﺬا اﻟﻤﺜﺎل ﻧﺮﻳﺪ أن ﻧﺠﻤﻊ ﻋﺪدًا ﺻﺤﻴﺤًﺎ ‪ INTEGER‬ﻣﻊ ﻋﺪد ﺛﻨﺎﺋﻲ ﺑﻄﻮل ﺧﺎﻧﺔ واﺣﺪة ‪1-bit‬‬ ‫‪ . Number‬ﻋﻨﺪهﺎ ﻓﺈن اﻟﺘﺎﺑﻊ ‪ Function‬اﻟﺘﺎﻟﻲ ﻳﻤﻜﻦ أن ﻳﺴﺘﺨﺪم ‪:‬‬ ‫‪----------------------------------------------------------------------------------------‬‬‫‪FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS‬‬ ‫‪BEGIN‬‬ ‫;‪IF (b='1') THEN RETURN a+1‬‬ ‫;‪ELSE RETURN a‬‬ ‫;‪END IF‬‬ ‫;"‪END "+‬‬ ‫‪----------------------------------------------------------------------------------------‬‬‫اﻵن ﻳﻤﻜﻨﻨﺎ اﺳﺘﺪﻋﺎء هﺬا اﻟﺘﺎﺑﻊ آﻤﺎ ﻓﻲ اﻟﻤﺜﺎل اﻟﺘﺎﻟﻲ ‪:‬‬


‫‪----------------------------------------------------------------------------------------‬‬‫;‪SIGNAL inp1, outp: INTEGER RANGE 0 TO 15‬‬ ‫;‪SIGNAL inp2: BIT‬‬ ‫)‪(...‬‬ ‫;‪outp <= 3 + inp1 + inp2‬‬ ‫)‪(...‬‬ ‫‪----------------------------------------------------------------------------------------‬‬‫ﻓ ﻲ اﻟﺘﻌﺒﻴ ﺮ " ‪ " outp <= 3 + inp1 + inp2‬ﻓ ﺈن اﻟﻤﻌﺎﻣ ﻞ اﻷول "‪ "+‬ه ﻮ ﻣﻌﺎﻣ ﻞ اﻟﺠﻤ ﻊ‬ ‫اﻟﻤﻌﺮف ﻣﺴ ﺒﻘًﺎ ) اﻻﻋﺘﻴ ﺎدي ( ﻓ ﻲ ﺣ ﻴﻦ أن اﻟﻤﻌﺎﻣ ﻞ اﻟﺜ ﺎﻧﻲ "‪ "+‬ه ﻮ ﻣﻌﺎﻣ ﻞ اﻟﺠﻤ ﻊ اﻟﻤﺤﻤ ﻞ ﺑﺸ ﻜﻞ‬ ‫زاﺋﺪ واﻟﻤﻌﺮف ﻣﻦ ﻗﺒﻞ اﻟﻤﺴﺘﺨﺪم ) واﻟﺬي ﻳﻘﻮم ﺑﺠﻤﻊ ﻋﺪد ﺻﺤﻴﺢ ‪ integer‬ﻣﻊ ﺧﺎﻧﺔ ‪. ( bit‬‬ ‫‪ -٥-٤‬اﻟﺜﺎﺑﺖ اﻟﻌﻤﻮﻣﻲ ‪GENERIC :‬‬ ‫آﻤﺎ ﻳﻮﺣﻲ اﻻﺳﻢ ﻓﺈن اﻟﺜﺎﺑﺖ اﻟﻌﻤﻮﻣﻲ ‪ GENERIC‬هﻮ ﻃﺮﻳﻘﺔ ﻟﺘﺤﺪﻳﺪ ﻗﻴﻤﺔ ﺛﺎﺑﺘﺔ ﻋﺎﻣﺔ ‪Generic‬‬ ‫‪ ) Parameter‬أي ﻗﻴﻤﺔ ﺛﺎﺑﺘﺔ واﻟﺘﻲ ﻳﻤﻜﻦ ﺑﺴﻬﻮﻟﺔ ﺗﻌﺪﻳﻠﻬﺎ و ﺟﻌﻠﻬﺎ ﻣﻼﺋﻤﺔ ﻟﺘﻄﺒﻴﻘﺎت ﻣﺨﺘﻠﻔ ﺔ ( ‪ .‬إن‬ ‫اﻟﻐﺎﻳﺔ هﻲ ﻣﻨﺢ اﻟﺸﻴﻔﺮة ﻣﺮوﻧﺔ أآﺜﺮ وﻗﺎﺑﻠﻴﺔ أآﺒﺮ ﻟﻼﺳﺘﺨﺪام ‪.‬‬ ‫إن ﺗﻌﻠﻴﻤﺔ ‪ GENERIC‬ﻋﻨﺪﻣﺎ ﺗﺴﺘﺨﺪم ﻳﺠﺐ أن ﻳﺼﺮح ﻋﻨﻬﺎ ﻓﻲ ﻗﺴﻢ اﻟﻜﻴﺎن ‪ ENTITY‬وﻋﻨ ﺪهﺎ‬ ‫ﻓﺈن اﻟﻘﻴﻤﺔ اﻟﺜﺎﺑﺘﺔ اﻟﻤﺤﺪدة ﺳﺘﻜﻮن ﺑﺎﻟﻔﻌ ﻞ ﻋﻤﻮﻣﻴ ﺔ ‪ ) Global‬أي ﺳ ﺘﻜﻮن ﻣﺮﺋﻴ ﺔ ﻣ ﻦ ﻗﺒ ﻞ اﻟﺘﺼ ﻤﻴﻢ‬ ‫آﻠﻪ ﺑﻤﺎ ﻓﻲ ذﻟﻚ ﻗﺴﻢ اﻟﻜﻴﺎن ﻧﻔﺴﻪ ( ‪ .‬إن اﻟﺼ ﻴﻐﺔ اﻟﻘﻮاﻋﺪﻳ ﺔ ‪ Syntax‬ﻟﻠﺘﻌﻠﻴﻤ ﺔ ‪ GENERIC‬ﻣﺒ ﻴﻦ‬ ‫ﻓﻴﻤﺎ ﻳﻠﻲ ‪:‬‬ ‫;)‪GENERIC (parameter_name : parameter_type := parameter_value‬‬ ‫ﻣﺜﺎل ‪Example :‬‬ ‫إن ﺗﻌﻠﻴﻤ ﺔ ‪ GENERIC‬اﻟﻤﺒﻴﻨ ﺔ ﻓﻴﻤ ﺎ ﻳﻠ ﻲ ﺗﺤ ﺪد ﻗﻴﻤ ﺔ ﺛﺎﺑﺘ ﺔ ‪ n‬ﻣ ﻦ ﻧ ﻮع اﻟﻤﻌﻄﻴ ﺎت ‪INTEGER‬‬ ‫واﻟﺘﻲ ﺗﺄﺧﺬ اﻟﻘﻴﻤﺔ ‪ . 8‬ﺑﻨﺎ ًء ﻋﻠﻰ ذﻟﻚ ‪ ،‬ﻋﻨﺪﻣﺎ ﺗﺼ ﺎدف ‪ n‬ﻓ ﻲ ﻗﺴ ﻢ اﻟﻜﻴ ﺎن ‪ ENTITY‬ﻧﻔﺴ ﻪ أو ﻓ ﻲ‬ ‫ﻗﺴﻢ اﻟﺒﻨﻴﺔ ‪ ) ARCHITECTURE‬ﻣﺮة واﺣﺪة أو أآﺜﺮ ( ﻓﺈن ﻗﻴﻤﺘﻬﺎ ﺳﻮف ﺗﻌﺘﺒﺮ ﻣﺴ ﺎوﻳﺔ اﻟﻘﻴﻤ ﺔ‬ ‫‪.8‬‬ ‫‪ENTITY my_entity IS‬‬ ‫;)‪GENERIC (n : INTEGER := 8‬‬ ‫;)‪PORT (...‬‬ ‫;‪END my_entity‬‬ ‫‪ARCHITECTURE my_architecture OF my_entity IS‬‬ ‫‪...‬‬ ‫‪END my_architecture:‬‬ ‫ﻓﻲ اﻟﺤﻘﻴﻘﺔ ﻳﻤﻜﻨﻨﺎ ﺗﺤﺪﻳﺪ أآﺜﺮ ﻣﻦ ﻗﻴﻤﺔ ﺛﺎﺑﺘﺔ ﻋﺎﻣﺔ ‪ Generic Parameter‬ﻓﻲ اﻟﻜﻴ ﺎن ‪ENTITY‬‬ ‫ﻓﻌﻠﻰ ﺳﺒﻴﻞ اﻟﻤﺜﺎل ﻳﻤﻜﻦ أن ﻧﻜﺘﺐ ‪:‬‬ ‫;)"‪GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111‬‬ ‫ﻓﻴﻤ ﺎ ﻳﻠ ﻲ ﺳ ﻴﺘﻢ ﻋ ﺮض أﻣﺜﻠ ﺔ ﺗﺼ ﻤﻴﻢ آﺎﻣﻠ ﺔ ‪ Complete Design Examples‬واﻟﺘ ﻲ ﺗﻮﺿ ﺢ‬ ‫ﺑﺸﻜﻞ إﺿﺎﻓﻲ اﺳﺘﺨﺪام ‪ GENERIC‬وﺧﺼﺎﺋﺺ ‪ Attributes‬وﻣﻌﺎﻣﻼت ‪ Operators‬أﺧﺮى‪.‬‬ ‫‪ -٦-٤‬أﻣﺜﻠﺔ ﺗﺼﻤﻴﻤﻴﺔ ‪Design Examples :‬‬ ‫ﺳ ﻨﻌﺮض اﻵن ﺑﻀ ﻌﺔ أﻣﺜﻠ ﺔ ﺗﺼ ﻤﻴﻢ آﺎﻣﻠ ﺔ ﺑﻬ ﺪف ﺗﻮﺿ ﻴﺢ اﺳ ﺘﺨﺪام اﻟﻤﻌ ﺎﻣﻼت ‪Operators‬‬ ‫واﻟﺨﺼﺎﺋﺺ ‪ Attributes‬واﻟﻘﻴﻢ اﻟﺜﺎﺑﺘﺔ اﻟﻌﺎﻣ ﺔ ‪ GENERIC‬ﺑﺸ ﻜﻞ أﻓﻀ ﻞ ‪ .‬ﻧ ﺬآﺮ هﻨ ﺎ ﻋﻠ ﻰ آ ﻞ‬ ‫ﺣ ﺎل ‪ ،‬ﺑﺄﻧ ﻪ ﺣﺘ ﻰ اﻵن آﻨ ﺎ ﻧﻌﻤ ﻞ ﻋﻠ ﻰ ﺗﻮﺿ ﻴﺢ اﻟﻤﻔ ﺎهﻴﻢ واﻷﺳ ﺲ اﻟﺮﺋﻴﺴ ﻴﺔ ﻟﻠﻐ ﺔ ‪ VHDL‬أﻣ ﺎ‬ ‫اﻟﻤﻨﺎﻗﺸ ﺔ اﻟﻘﻮاﻋﺪﻳ ﺔ ﻟﺘﻘﻨﻴ ﺎت اﻟﺘﺸ ﻔﻴﺮ ‪ Coding Techniques‬ﻓﺴ ﺘﺒﺪأ ﻓ ﻲ اﻟﺠﻠﺴ ﺔ اﻟﻘﺎدﻣ ﺔ ) وه ﻲ‬ ‫ﺑﻌﻨﻮان اﻟﺸ ﻴﻔﺮة اﻟﻤﺘﻨﺎﻓﺴ ﺔ أو اﻟﻤﺘﻮازﻳ ﺔ ‪ . ( Concurrent Code‬ﻟ ﺬﻟﻚ ﻓ ﺈن اﻟﻄﺎﻟ ﺐ اﻟ ﺬي ﻳ ﺪرس‬ ‫ﻟﻐﺔ ‪ VHDL‬ﻟﻠﻤﺮة اﻷوﻟ ﻰ ﻳﺠ ﺐ أﻻ ﻳﺸ ﻌﺮ ﺑﺎﻹﺣﺒ ﺎط إذا ﺑ ﺪت ﻟ ﻪ اﻟﺒﻨ ﻰ ‪ Constructs‬ﻓ ﻲ اﻷﻣﺜﻠ ﺔ‬


‫اﻟﺘﺎﻟﻴﺔ ﻏﺎﻣﻀﺔ وﻏﻴ ﺮ ﻣﺄﻟﻮﻓ ﺔ ‪ .‬ﻋﻮﺿ ًﺎ ﻋ ﻦ ذﻟ ﻚ ‪ ،‬ﻳﻤﻜ ﻦ ﻟﻠﻄﺎﻟ ﺐ أن ﻳﻠﻘ ﻲ ﻧﻈ ﺮة ﻋﻠ ﻰ ه ﺬﻩ اﻷﻣﺜﻠ ﺔ‬ ‫اﻵن وﻣ ﻦ ﺛ ﻢ وﺑﻌ ﺪ دراﺳ ﺔ اﻟﺠﻠﺴ ﺘﻴﻦ اﻟﺨﺎﻣﺴ ﺔ واﻟﺴﺎدﺳ ﺔ ﻳﻤﻜﻨ ﻪ اﻟﻌ ﻮدة إﻟ ﻰ ه ﺬﻩ اﻷﻣﺜﻠ ﺔ وإﻋ ﺎدة‬ ‫ﺗﻔﺤﺼﻬﺎ وﻓﻬﻤﻬﺎ ﺑﺸﻜﻞ ﺟﻴﺪ !!!‬ ‫اﻟﻤﺜﺎل ) ‪ : ( ١-٤‬ﻓﺎك ﺷﻴﻔﺮة ﻋﺎم ‪Generic Decoder‬‬ ‫ﻳﺒﻴﻦ اﻟﺸﻜﻞ ) ‪ ( ١-٤‬ﻣﺨﻄﻂ اﻟﻤﺴﺘﻮى اﻷﻋﻠﻰ ‪ Top-Level Diagram‬ﻟﻔﺎك ﺷﻴﻔﺮة ﻋﺎم ﻣﻦ ﻧ ﻮع‬ ‫‪ . m-by-n‬ﺗﻤﺘﻠ ﻚ اﻟ ﺪارة ﻣ ﺪﺧﻠﻴﻦ أﺣ ﺪهﻤﺎ ه ﻮ اﻟﻤ ﺪﺧﻞ ‪ sel‬وه ﻮ ﺑﻌ ﺮض ‪ m‬ﺧﺎﻧ ﺔ ) ‪( m bits‬‬ ‫واﻵﺧﺮ هﻮ اﻟﻤﺪﺧﻞ ‪ ena‬وهﻮ ﺑﻌﺮض ﺧﺎﻧﺔ وﺣﻴﺪة ) ‪ ( single bit‬آﻤﺎ أﻧﻬ ﺎ ﺗﻤﺘﻠ ﻚ ﻣﺨﺮﺟ ًﺎ وﺣﻴ ﺪًا‬ ‫هﻮ اﻟﻤﺨﺮج ‪ x‬ﺑﻌﺮض ‪ n‬ﺧﺎﻧﺔ ) ‪ . ( n bits‬ﺳﻮف ﻧﻔﺘ ﺮض أن ‪ n‬ه ﻲ إﺣ ﺪى ﻗ ﻮى اﻟﻌ ﺪد ‪ 2‬ﺑﺤﻴ ﺚ‬ ‫أن ‪ . m = log2 ( n ) :‬إذا آﺎﻧﺖ ﻗﻴﻤﺔ اﻟﻤ ﺪﺧﻞ '‪ ena = '0‬ﻓ ﺈن آﺎﻓ ﺔ ﺧﺎﻧ ﺎت اﻟﻤﺨ ﺮج ‪ x‬ﻳﺠ ﺐ أن‬ ‫ﺗﻜﻮن ﺑﺤﺎﻟﺔ '‪ ( High ) '1‬وإﻻ ﻓﺈن ﺧﺎﻧﺔ اﻟﺨﺮج اﻟﻤﺨﺘ ﺎرة ‪ Selected‬ﺑﻮاﺳ ﻄﺔ اﻟﻤ ﺪﺧﻞ ‪ sel‬ﻳﺠ ﺐ‬ ‫أن ﺗﻜﻮن ﺑﺤﺎﻟﺔ '‪ ( Low ) '0‬وذﻟﻚ آﻤﺎ هﻮ ﻣﻮﺿﺢ ﻓﻲ ﺟﺪول اﻟﺤﻘﻴﻘ ﺔ ‪ Truth Table‬اﻟﻤﻌ ﺮوض‬ ‫ﻓﻲ اﻟﺸﻜﻞ ) ‪. ( ١-٤‬‬

‫اﻟﺸﻜﻞ ) ‪ : ( ١-٤‬ﻣﺨﻄﻂ اﻟﻤﺴﺘﻮى اﻷﻋﻠﻰ وﺟﺪول اﻟﺤﻘﻴﻘﺔ ﻟﻔﺎك اﻟﺸﻴﻔﺮة اﻟﻌﺎم ﻟﻠﻤﺜﺎل ) ‪( ١-٤‬‬ ‫إن اﻟﺒﻨﻴﺔ ‪ ARCHITECTURE‬اﻟﻤﻌﺮوﺿﺔ أدﻧﺎﻩ ه ﻲ ﻋﺎﻣ ﺔ ﺑﺸ ﻜﻞ ﺗ ﺎم ﻷن اﻟﺘﻐﻴﻴ ﺮات اﻟﻤﻄﻠﻮﺑ ﺔ‬ ‫ﻟﻠﻌﻤﻞ ﻣﻊ ﻗﻴﻢ ﻣﺨﺘﻠﻔﺔ ﻟﻜﻞ ﻣﻦ ‪ m‬و ‪ n‬هﻲ ﻓﻲ ﻗﺴﻢ اﻟﻜﻴ ﺎن ) ﻣ ﻦ ﺧ ﻼل ‪ sel‬ﻓ ﻲ اﻟﺴ ﻄﺮ اﻟﺴ ﺎﺑﻊ و ‪x‬‬ ‫ﻓ ﻲ اﻟﺴ ﻄﺮ اﻟﺜ ﺎﻣﻦ ﻋﻠ ﻰ اﻟﺘﺮﺗﻴ ﺐ ( ‪ .‬ﻓ ﻲ ه ﺬا اﻟﻤﺜ ﺎل ‪ ،‬اﺳ ﺘﺨﺪﻣﻨﺎ ‪ m = 3‬و ‪ . n = 8‬ﻋﻠ ﻰ آ ﻞ ‪،‬‬ ‫ﺑﺎﻟﺮﻏﻢ ﻣﻦ أن هﺬا اﻟﻤﺜﺎل ﻋﺎم ﺑﺎﻟﻔﻌﻞ وﻳﻌﻤﻞ ﺑﺸﻜﻞ ﺟﻴﺪ إﻻ أن اﺳﺘﺨﺪام ‪ GENERIC‬ﺳﻮف ﻳﺠﻌ ﻞ‬ ‫ﻼ ﻗﻴﻤﺘﺎن ﺛﺎﺑﺘﺘﺎن ﻋﺎﻣﺘ ﺎن ‪ . Generic Parameters‬وذﻟ ﻚ ﺑﺎﻟﻔﻌ ﻞ‬ ‫ﻣﻦ اﻷوﺿﺢ أن ‪ m‬و ‪ n‬هﻤﺎ ﻓﻌ ً‬ ‫اﻹﺟﺮاء اﻟﺬي ﺳﻴﺘﻢ ﺗﺒﻨﻴﻪ ﻓﻲ اﻟﻤﺜﺎﻟﻴﻦ اﻵﺧﺮﻳﻦ اﻟﻘﺎدﻣﻴﻦ ‪.‬‬ ‫ﻻﺣﻆ ﻓﻲ اﻟﺸﻴﻔﺮة اﻟﺘﺎﻟﻴﺔ اﺳﺘﺨﺪام اﻟﻤﻌﺎﻣﻼت ‪ ) "+" :‬ﻓﻲ اﻟﺴ ﻄﺮ ‪ ) "*" ، ( 22‬ﻓ ﻲ اﻟﺴ ﻄﺮﻳﻦ ‪22‬‬ ‫و ‪ ) ":=" ، ( 24‬ﻓﻲ اﻷﺳﻄﺮ ‪ 17‬و ‪ 18‬و ‪ 22‬و ‪ 24‬و ‪ ) "<=" ، ( 27‬ﻓﻲ اﻟﺴﻄﺮ ‪، ( 29‬‬ ‫و اﻟﻤﻌﺎﻣﻞ ">=" ) ﻓﻲ اﻟﺴﻄﺮ ‪. ( 17‬‬ ‫ﻻﺣﻆ أﻳﻀًﺎ اﺳﺘﺨﺪام اﻟﺨﺼﺎﺋﺺ اﻟﺘﺎﻟﻴﺔ ‪ ) HIGH :‬ﻓﻲ اﻟﺴ ﻄﺮﻳﻦ ‪ 14‬و ‪ ( 15‬و ‪ ) RANGE‬ﻓ ﻲ‬ ‫اﻟﺴﻄﺮ ‪. ( 20‬‬ ‫إن وﻇﺎﺋﻔﻴﺔ ﻓﺎك اﻟﺸﻴﻔﺮة ‪ Decoder‬اﻟﻤ���ﺮوض ﻓﻲ هﺬا اﻟﻤﺜﺎل ﻳﻤﻜﻦ أن ﻳﺘﻢ اﻟﺘﺤﻘﻖ ﻣﻦ ﺻﺤﺘﻬﺎ ﻣﻦ‬ ‫ﺧﻼل ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ‪ Simulation Results‬اﻟﻤﺒﻴﻨ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ ) ‪ . ( ٢-٤‬آﻤ ﺎ ﻳﻤﻜ ﻦ أن ﻧ ﺮى ‪،‬‬ ‫ﻓﺈن آﺎﻓ ﺔ ﺧﺎﻧ ﺎت اﻟﻤﺨ ﺮج ‪ x‬ه ﻲ ﺑﺤﺎﻟ ﺔ ‪ ) x = "11111111" High‬أي اﻟﻘﻴﻤ ﺔ ‪ 255‬ﻓ ﻲ اﻟﻨﻈ ﺎم‬ ‫اﻟﻌﺸﺮي ( ﻋﻨﺪﻣﺎ ﺗﻜ ﻮن ﻗﻴﻤ ﺔ اﻟﻤ ﺪﺧﻞ '‪ . ena = '0‬ﺑﻌ ﺪ أن ﻳ ﺘﻢ ﺗﻔﻌﻴ ﻞ اﻟﻤ ﺪﺧﻞ ‪ ena‬أي '‪ena = '1‬‬ ‫ﻓﺈن ﺧﺎﻧﺔ وﺣﻴﺪة ﻓﻘﻂ ﻣ ﻦ ﺧﺎﻧ ﺎت اﻟﻤﺨ ﺮج ‪ ) x‬وه ﻲ اﻟﺨﺎﻧ ﺔ اﻟﻤﺤ ﺪدة ﺑﻮاﺳ ﻄﺔ اﻟﻤ ﺪﺧﻞ ‪ ( sel‬ﺗﻜ ﻮن‬ ‫ﺑﺤﺎﻟ ﺔ ‪ . Low‬ﻋﻠ ﻰ ﺳ ﺒﻴﻞ اﻟﻤﺜ ﺎل ‪ ،‬ﻋﻨ ﺪﻣﺎ ﺗﻜ ﻮن "‪ ) sel = "000‬اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 0‬ﻓ ﺈن ﻗﻴﻤ ﺔ‬ ‫اﻟﻤﺨﺮج "‪ ) x = "11111110‬اﻟﻘﻴﻤﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 254‬أﻣ ﺎ ﻋﻨ ﺪﻣﺎ ﺗﻜ ﻮن "‪ ) sel = "001‬اﻟﻘﻴﻤ ﺔ‬ ‫اﻟﻌﺸﺮﻳﺔ ‪ ( 1‬ﻓﺈن "‪ ) x = "11111101‬اﻟﻘﻴﻤﺔ اﻟﻌﺸﺮﻳﺔ ‪ ( 253‬وأﺧﻴﺮًا ﻋﻨﺪﻣﺎ ﺗﻜﻮن ﻗﻴﻤ ﺔ اﻟﻤ ﺪﺧﻞ‬ ‫"‪ ) sel = "010‬اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 2‬ﻓ ﺈن "‪ ) x = "11111011‬اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 251‬وهﻜ ﺬا‬ ‫دواﻟﻴﻚ ‪.‬‬


1 -------------------------------------------------------------------------------------2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -------------------------------------------------------------------------------------5 ENTITY decoder IS 6 PORT ( ena : IN STD_LOGIC; 7 sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 8 x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 9 END decoder; 10 ------------------------------------------------------------------------------------11 ARCHITECTURE generic_decoder OF decoder IS 12 BEGIN 13 PROCESS (ena, sel) 14 VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); 15 VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH; 16 BEGIN 17 temp1 := (OTHERS => '1'); 18 temp2 := 0; 19 IF (ena='1') THEN 20 FOR i IN sel'RANGE LOOP 21 IF (sel(i)='1') THEN 22 temp2:=2*temp2+1; 23 ELSE 24 temp2 := 2*temp2; 25 END IF; 26 END LOOP; 27 temp1(temp2):='0'; 28 END IF; 29 x <= temp1; 30 END PROCESS; 31 END generic_decoder; 32 -------------------------------------------------------------------------------------

( ١-٤ ‫ ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻤﺜﺎل ﻓﺎك اﻟﺸﻴﻔﺮة اﻟﻌﺎم ) اﻟﻤﺜﺎل‬: ( ٢-٤ ) ‫اﻟﺸﻜﻞ‬


‫اﻟﻤﺜﺎل ) ‪ : ( ٢-٤‬آﺎﺷﻒ ازدواﺟﻴﺔ ﻋﺎم ‪Generic Parity Detector :‬‬ ‫ﻳﺒ ﻴﻦ اﻟﺸ ﻜﻞ ) ‪ ( ٣-٤‬ﻣﺨﻄ ﻂ اﻟﻤﺴ ﺘﻮى اﻷﻋﻠ ﻰ ‪ Top-Level Diagram‬ﻟﻜﺎﺷ ﻒ ازدواﺟﻴ ﺔ‬ ‫‪ . Parity Detector‬ﻳﺠﺐ أن ﺗﺰود اﻟﺪارة اﻟﻘﻴﻤﺔ '‪ output = '0‬ﻋﻨﺪﻣﺎ ﻳﻜﻮن ﻋﺪد اﻟﻮاﺣ ﺪات ‪'1's‬‬ ‫ﻓﻲ ﺷﻌﺎع اﻟﺪﺧﻞ زوﺟﻴًﺎ ‪ . Even‬أو '‪ output = '1‬ﻓﻲ اﻟﺤﺎﻟﺔ اﻟﻤﻌﺎآﺴﺔ ) ﻋ ﺪد اﻟﻮاﺣ ﺪات ‪ '1's‬ﻓ ﻲ‬ ‫ﺷﻌﺎع اﻟﺪﺧﻞ ﻓﺮدي ‪ . ( Odd‬ﻻﺣ ﻆ ﻓ ﻲ ﺷ ﻴﻔﺮة ‪ VHDL‬اﻟﻤﻌﺮوﺿ ﺔ أدﻧ ﺎﻩ أن اﻟﻜﻴ ﺎن ‪ENTITY‬‬ ‫ﻳﺘﻀﻤﻦ ﺗﻌﻠﻴﻤﺔ ‪ ) GENERIC‬ﻓﻲ اﻟﺴﻄﺮ اﻟﺜﺎﻟﺚ ( واﻟﺘﻲ ﺗﺤﺪد ‪ n‬آﻘﻴﻤﺔ ﺛﺎﺑﺘﺔ ﻋﺎﻣﺔ ﻣﻘﺪارهﺎ ‪. 7‬‬ ‫ه ﺬﻩ اﻟﺸ ﻴﻔﺮة ﺳ ﻮف ﺗﻌﻤ ﻞ ﻣ ﻦ أﺟ ﻞ أي ﺣﺠ ﻢ ﺁﺧ ﺮ ﻟﺸ ﻌﺎع اﻟ ﺪﺧﻞ ‪ input‬وﻋﻨ ﺪهﺎ ﺳ ﻴﻜﻮن ﻣ ﻦ‬ ‫اﻟﻀ ﺮوري ﻓﻘ ﻂ ﺗﻐﻴﻴ ﺮ ﻗﻴﻤ ﺔ ‪ n‬ﻓ ﻲ ذﻟ ﻚ اﻟﺴ ﻄﺮ ) ‪ . ( 3‬اﻟﻄﺎﻟ ﺐ ﻣ ﺪﻋﻮ ﻟﺘﺄﺷ ﻴﺮ اﻟﻤﻌ ﺎﻣﻼت‬ ‫‪ Operators‬واﻟﺨﺼﺎﺋﺺ ‪ Attributes‬اﻟﺘﻲ ﺗﻈﻬﺮ ﻓﻲ اﻟﻜﻮد ) اﻟﺸﻴﻔﺮة ( !!!‬

‫اﻟﺸﻜﻞ ) ‪ : ( ٣-٤‬ﻣﺨﻄﻂ اﻟﻤﺴﺘﻮى اﻷﻋﻠﻰ ﻟﻜﺎﺷﻒ اﻻزدواﺟﻴﺔ اﻟﻌﺎم ﻟﻠﻤﺜﺎل ) ‪( ٢-٤‬‬ ‫‪1 -------------------------------------------------------------------------------------‬‬‫‪2 ENTITY parity_det IS‬‬ ‫‪3‬‬ ‫;)‪GENERIC (n : INTEGER := 7‬‬ ‫‪4‬‬ ‫;)‪PORT ( input: IN BIT_VECTOR (n DOWNTO 0‬‬ ‫‪5‬‬ ‫;)‪output: OUT BIT‬‬ ‫;‪6 END parity_det‬‬ ‫‪7 -------------------------------------------------------------------------------------‬‬‫‪8 ARCHITECTURE parity OF parity_det IS‬‬ ‫‪9 BEGIN‬‬ ‫‪10‬‬ ‫)‪PROCESS (input‬‬ ‫‪11‬‬ ‫;‪VARIABLE temp: BIT‬‬ ‫‪12‬‬ ‫‪BEGIN‬‬ ‫‪13‬‬ ‫;'‪temp := '0‬‬ ‫‪14‬‬ ‫‪FOR i IN input'RANGE LOOP‬‬ ‫‪15‬‬ ‫;)‪temp := temp XOR input(i‬‬ ‫‪16‬‬ ‫;‪END LOOP‬‬ ‫‪17‬‬ ‫;‪output <= temp‬‬ ‫‪18‬‬ ‫;‪END PROCESS‬‬ ‫;‪19 END parity‬‬ ‫‪20 ------------------------------------------------------------------------------------‬‬‫ﻧﺘ ﺎﺋﺞ اﻟﻤﺤﺎآ ﺎة ﻣ ﻦ اﻟ ﺪارة اﻟﻤﺮآﺒ ﺔ ‪ Synthesized‬ﺑﻮاﺳ ﻄﺔ اﻟﺸ ﻴﻔﺮة أﻋ ﻼﻩ ﻣﻌﺮوﺿ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ‬ ‫) ‪ . ( ٤-٤‬ﻻﺣ ﻆ أﻧ ﻪ ﻋﻨ ﺪﻣﺎ ﻳﻜ ﻮن "‪ ) input = "00000000‬اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 0‬ﻓ ﺈن ﻗﻴﻤ ﺔ‬ ‫اﻟﻤﺨﺮج '‪ output = '0‬ﻷن ﻋﺪد اﻟﻮاﺣ ﺪات ﻓ ﻲ ه ﺬﻩ اﻟﺤﺎﻟ ﺔ ) اﻟﺼ ﻔﺮ ( ه ﻮ ﻗﻴﻤ ﺔ زوﺟﻴ ﺔ ‪. Even‬‬


‫ﻋﻨ ﺪﻣﺎ ﻳﻜ ﻮن "‪ ) x = "00000001‬اﻟﻘﻴﻤ ﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ ( 1‬ﻓ ﺈن ﻗﻴﻤ ﺔ اﻟﻤﺨ ﺮج '‪ output = '1‬ﻷن‬ ‫ﻋﺪد اﻟﻮاﺣﺪات ﻓﻲ هﺬﻩ اﻟﺤﺎﻟﺔ ) اﻟﻮاﺣﺪ ( هﻮ ﻗﻴﻤﺔ ﻓﺮدﻳﺔ ‪ Odd‬وهﻜﺬا دواﻟﻴﻚ ‪.‬‬

‫اﻟﺸﻜﻞ ) ‪ : ( ٤-٤‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻤﺜﺎل آﺎﺷﻒ اﻻزدواﺟﻴﺔ اﻟﻌﺎم ) اﻟﻤﺜﺎل ‪( ٢-٤‬‬ ‫اﻟﻤﺜﺎل ) ‪ : ( ٣-٤‬ﻣﻮﻟﺪ ازدواﺟﻴﺔ ﻋﺎم ‪Generic Parity Generator :‬‬ ‫إن اﻟ ﺪارة اﻟﻤﺒﻴﻨ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ ) ‪ ( ٥-٤‬ﻳﺠ ﺐ أن ﺗﻀ ﻴﻒ ﺧﺎﻧ ﺔ واﺣ ﺪة ‪ One Bit‬إﻟ ﻰ ﺷ ﻌﺎع اﻟ ﺪﺧﻞ‬ ‫) وﺗﺤﺪﻳ ﺪًا إﻟ ﻰ ﻳﺴ ﺎرﻩ ( ‪ .‬ه ﺬﻩ اﻟﺨﺎﻧ ﺔ ﻳﺠ ﺐ أن ﺗﻜ ﻮن '‪ '0‬إذا آ ﺎن ﻋ ﺪد اﻟﻮاﺣ ﺪات ‪ '1's‬ﻓ ﻲ ﺷ ﻌﺎع‬ ‫اﻟ ﺪﺧﻞ زوﺟﻴ ًﺎ ‪ Even‬أو ﻳﺠ ﺐ أن ﺗﻜ ﻮن '‪ '1‬إذا آ ﺎن ﻋ ﺪد اﻟﻮاﺣ ﺪات ‪ '1's‬ﻓ ﻲ ﺷ ﻌﺎع اﻟ ﺪﺧﻞ ﻓﺮدﻳ ًﺎ‬ ‫‪ . Odd‬ﻓﻲ هﺬﻩ اﻟﺤﺎﻟﺔ ﻓﺈن اﻟﺸﻌﺎع اﻟﻨﺎﺗﺞ ‪ Resulting Vector‬ﺳ ﻮف ﻳﺤﺘ ﻮي دوﻣ ًﺎ ﻋ ﺪدًا زوﺟﻴ ًﺎ‬ ‫ﻣﻦ اﻟﻮاﺣﺪات ‪ ) '1's‬ازدواﺟﻴﺔ زوﺟﻴﺔ ‪. ( Even Parity‬‬ ‫ﺷﻴﻔﺮة ‪ VHDL‬ﻣﻦ أﺟﻞ ﻣﻮﻟ ﺪ اﻻزدواﺟﻴ ﺔ اﻟﻤﻄﻠ ﻮب ﻣﺒﻴﻨ ﺔ ﻓﻴﻤ ﺎ ﻳﻠ ﻲ ‪ .‬ﻣ ﺮة أﺧ ﺮى ‪ ،‬ﻓ ﺈن اﻟﻄﺎﻟ ﺐ‬ ‫ﻣﺪﻋﻮ ﻟﺘﺄﺷﻴﺮ اﻟﻤﻌﺎﻣﻼت ‪ Operators‬واﻟﺨﺼﺎﺋﺺ ‪ Attributes‬اﻟﻤﺴﺘﺨﺪﻣﺔ ﻓﻲ هﺬا اﻟﺘﺼﻤﻴﻢ ‪.‬‬ ‫‪1 -------------------------------------------------------------------------------------‬‬‫‪2 ENTITY parity_gen IS‬‬ ‫‪3‬‬ ‫;)‪GENERIC (n : INTEGER := 7‬‬ ‫‪4‬‬ ‫;)‪PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0‬‬ ‫‪5‬‬ ‫;))‪output: OUT BIT_VECTOR (n DOWNTO 0‬‬ ‫;‪6 END parity_gen‬‬ ‫‪7 -------------------------------------------------------------------------------------‬‬‫‪8 ARCHITECTURE parity OF parity_gen IS‬‬ ‫‪9 BEGIN‬‬ ‫‪10‬‬ ‫)‪PROCESS (input‬‬ ‫‪11‬‬ ‫;‪VARIABLE temp1: BIT‬‬ ‫‪12‬‬ ‫;)‪VARIABLE temp2: BIT_VECTOR (output'RANGE‬‬ ‫‪13‬‬ ‫‪BEGIN‬‬ ‫‪14‬‬ ‫;'‪temp1 := '0‬‬ ‫‪15‬‬ ‫‪FOR i IN input'RANGE LOOP‬‬ ‫‪16‬‬ ‫;)‪temp1 := temp1 XOR input(i‬‬ ‫‪17‬‬ ‫;)‪temp2(i) := input(i‬‬ ‫‪18‬‬ ‫;‪END LOOP‬‬ ‫‪19‬‬ ‫;‪temp2(output'HIGH) := temp1‬‬ ‫‪20‬‬ ‫;‪output <= temp2‬‬ ‫‪21‬‬ ‫;‪END PROCESS‬‬ ‫;‪22 END parity‬‬ ‫‪23 ------------------------------------------------------------------------------------‬‬‫ﻧﺘ ﺎﺋﺞ اﻟﻤﺤﺎآ ﺎة ‪ Simulation Results‬ﻣﻌﺮوﺿ ﺔ ﻓ ﻲ اﻟﺸ ﻜﻞ ) ‪ . ( ٦-٤‬آﻤ ﺎ ﻳﻤﻜ ﻦ أن ﻧ ﺮى ‪،‬‬ ‫ﻋﻨﺪﻣﺎ ﻳﻜﻮن "‪ ) input = "0000000‬اﻟﻘﻴﻤﺔ اﻟﻌﺸ ﺮﻳﺔ ‪ 0‬ﺑﺴ ﺒﻊ ﺧﺎﻧ ﺎت ( ﻓ ﺈن ﻗﻴﻤ ﺔ إﺷ ﺎرة اﻟﺨ ﺮج‬ ‫"‪ ) output = "00000000‬اﻟﻘﻴﻤﺔ اﻟﻌﺸﺮﻳﺔ ‪ 0‬ﺑﺜﻤﺎن ﺧﺎﻧﺎت ( أﻣﺎ ﻋﻨﺪﻣﺎ ﺗﻜﻮن ﻗﻴﻤﺔ إﺷﺎرة اﻟ ﺪﺧﻞ‬


‫"‪ ) input = "0000001‬اﻟﻘﻴﻤﺔ اﻟﻌﺸﺮﻳﺔ ‪ 1‬ﺑﺴﺒﻊ ﺧﺎﻧﺎت ( ﻓ ﺈن ﻗﻴﻤ ﺔ "‪output = "10000001‬‬ ‫) اﻟﻘﻴﻤﺔ اﻟﻌﺸﺮﻳﺔ ‪ 129‬ﺑﺜﻤﺎن ﺧﺎﻧﺎت ( وهﻜﺬا دواﻟﻴﻚ ‪.‬‬

‫اﻟﺸﻜﻞ ) ‪ : ( ٦-٤‬ﻧﺘﺎﺋﺞ اﻟﻤﺤﺎآﺎة ﻟﻤﺜﺎل ﻣﻮﻟﺪ اﻻزدواﺟﻴﺔ اﻟﻌﺎم ﻟﻠﻤﺜﺎل ) ‪( ٣-٤‬‬ ‫‪ -٧-٤‬ﺧﻼﺻﺔ ‪Summary :‬‬ ‫ﻓ ﻲ اﻟﺠ ﺪوﻟﻴﻦ ) ‪ ( ١-٤‬و ) ‪ ( ٢-٤‬ﺗ ﻢ ﻋ ﺮض ﺧﻼﺻ ﺘﻴﻦ ﻟﻠﻤﻌ ﺎﻣﻼت واﻟﺨﺼ ﺎﺋﺺ ﻓ ﻲ ﻟﻐ ﺔ‬ ‫‪ . VHDL‬اﻟﺒﻨﻰ ﻏﻴﺮ اﻟﻘﺎﺑﻠﺔ ﻟﻠﺘﺮآﻴﺐ ﺗﻢ اﻹﺷﺎرة إﻟﻴﻬﺎ ﺑﻤﻌﻴﻦ ﺻﻐﻴﺮ أﺳﻮد إﻟﻰ ﺟﺎﻧﺒﻬﺎ ‪.‬‬

‫اﻟﺠﺪول ) ‪ : ( ١-٤‬ﺧﻼﺻﺔ ﻋﻦ اﻟﻤﻌﺎﻣﻼت ﻓﻲ ﻟﻐﺔ ‪VHDL‬‬

‫اﻟﺠﺪول ) ‪ : ( ٢-٤‬ﺧﻼﺻﺔ ﻋﻦ اﻟﺨﺼﺎﺋﺺ ﻓﻲ ﻟﻐﺔ ‪VHDL‬‬


= = = Problems = = = Problems 4.1 to 4.3 are based on the following signal declarations: SIGNAL a : BIT := '1'; SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100"; SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010"; SIGNAL d : BIT_VECTOR (7 DOWNTO 0); SIGNAL e : INTEGER RANGE 0 TO 255; SIGNAL f : INTEGER RANGE -128 TO 127; Problem 4.1: Operators (fill in the blanks) : x1 <= a & c; x2 <= c & b; x3 <= b XOR c; x4 <= a NOR b(3); x5 <= b sll 2; x6 <= b sla 2; x7 <= b rol 2; x8 <= a AND NOT b(0) AND NOT c(1); d <= (5=>'0', OTHERS=>'1');

-> x1 <= ________ -> x2 <= ________ -> x3 <= ________ -> x4 <= ________ -> x5 <= ________ -> x6 <= ________ -> x7 <= ________ -> x8 <= ________ -> d<= ________

Problem 4.2: Attributes (fill in the blanks) : c'LOW d'HIGH c'LEFT d'RIGHT c'RANGE d'LENGTH c'REVERSE_RANGE

-> ______ -> ______ -> ______ -> ______ -> ______ -> ______ -> ______

Problem 4.3: Legal and Illegal Operations : Verify whether each of the operations below is legal or illegal. Briefly justify your answers : b(0) AND a a + d(7) NOT b XNOR c c+d e-f


IF (b<c) ... IF (b>=a) ... IF (f/=e) ... IF (e>d) ... b sra 1 c srl -2 f ror 3 e*3 5**5 f/4 e/3 d <= c d(6 DOWNTO 3) := b e <= d f := 100 Problem 4.4: Generic Decoder : The questions below are related to decoder circuit designed in example 4.1. (a) In order for that design to operate with another vector size, two values must be changed: the range of sel (line 7) and the range of x (line 8). We want now to transform that design in a truly generic one. In order to do so, introduce a GENERIC statement in the ENTITY, specifying the number of bits of sel (say, n = 3), then replace the upper range limits of sel and x by an attribute which is a function of n. Synthesize and simulate your circuit in order to verify its functionality. (b) In example 4.1, a binary-to-integer conversion was implemented (lines 20â&#x20AC;&#x201C;26). This conversion could be avoided if sel had been declared as an INTEGER. Modify the code, declaring sel as an INTEGER. The code should remain truly generic, so the range of sel must be specified in terms of n. Synthesize and simulate your new code. Problem 4.5 : List all operators, attributes and generics employed in examples 4.2 and 4.3.


VHDL 03