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STUDY AND DESIGN ANALYSIS OF INTERCONNECTS BETWEEN DDR II RAM AND MPC8315E PROCESSOR. BY GIRISH KUMAR AJMERA [2012CRF2503] 1

HEMANT KUMAR SINGHAL [2012CRF2966]


BOARD FILE : MPC8315E • Allegro Free viewer.

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STUDY ABOUT THE ARCHITECTURE OF BOARD. • Clock circuitry • Processor : MPC8315E • DDR Controller

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16 LAYERS PCB • Signal Traces • Ground Planes • Power Planes

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LAYER 5 [V]

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LAYER 5 [H]

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LAYER 11 [V]

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LAYER 12 [H]

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DDR RAM  PROCESSOR 1. 200 pin small outline dual in-line memory module 2. 64 Traces for data Transfer. [DQ0 – DQ63] These are for bidirectional data input/output.

3. Differential data strobe option. Source synchronous mode of operation is also there with 8 traces. For Reading of data edge is edge is aligned, for writing the data center is aligned.

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DDR II RAM

Processor

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EXAMPLE : DQ0 TRACE ANALYSIS. • What kind of line? • Layer in which line is etched out? • Design parameters of the line? • Width of trace? • Length of trace? • Dielectric constant of material? • Separation between two layers? • Loss Tangent? • Frequency of operation?

These all things can be known from the Allegro Free viewer, as the board file contain all the parameters

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EXAMPLE : DQ0 TRACE ANALYSIS. • Calculation of Characteristic impedance of the line. (Asymmetric Strip Line) 𝑍0 = 2(𝑍𝑜1 ||𝑍𝑜2 ) 𝑍𝑜1 = 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 𝑜𝑓 𝑠𝑦𝑚𝑚𝑒𝑡𝑟𝑖𝑐 𝑠𝑡𝑟𝑝𝑙𝑖𝑛𝑒 𝑤𝑖𝑡ℎ ℎ𝑒𝑖𝑔ℎ𝑡 2𝐻1 + 𝑇 𝑍𝑜2 = 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 𝑜𝑓 𝑠𝑦𝑚𝑚𝑒𝑡𝑟𝑖𝑐 𝑠𝑡𝑟𝑝𝑙𝑖𝑛𝑒 𝑤𝑖𝑡ℎ ℎ𝑒𝑖𝑔ℎ𝑡 2𝐻2 + 𝑇 Characteristic impedance of a symmetric strip line is given by 𝑍0 =

30𝜋 𝑏 ( ) 𝜀𝑟 (𝑊𝑒 +0.441𝑏

Where We is the effective width of the conductor and is given by 𝑊𝑒 𝑏

𝑊 𝑊 = 𝑤ℎ𝑒𝑛 > 0.35 𝑏 𝑏 𝑊 𝑊 2 𝑊 = − 0.35 − 𝑤ℎ𝑒𝑛 < 0.35 𝑏 𝑏 𝑏

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1.56 mil L4

1.38 mil 1.56 mil đ?&#x2018;?01 = 60 đ?&#x2018;&#x153;â&#x201E;&#x17D;đ?&#x2018;&#x161; đ?&#x2018;?02 = 41.3 đ?&#x2018;&#x153;â&#x201E;&#x17D;đ?&#x2018;&#x161;

2.655 mil

H2 = 4.215 mil T = 0.69 mil L5

2.655 mil So Z = 48.95 ohm 4.5 mil

H1 = 9.215mil

L6

2.06 mil 1.38 mil 2.06 mil

L7 14


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This Tool is available online at http://www.eeweb.com/toolbox/asymmetric-stripline-impedance


EXAMPLE : DQ0 TRACE ANALYSIS. â&#x20AC;˘ Calculation of Attenuation (due to dielectric). 2đ?&#x153;&#x2039; 2đ?&#x153;&#x2039;đ?&#x2018;&#x201C; đ?&#x153;&#x2013;đ?&#x2018;&#x; đ?&#x2018;&#x2DC;= = Ć&#x203A; đ?&#x2018;? tan đ?&#x203A;ż đ?&#x203A;źđ?&#x2018;&#x2018; = đ?&#x2018;&#x2DC;. 2

đ?&#x203A;źđ?&#x2018;&#x2018; đ?&#x2018;&#x2013;đ?&#x2018;&#x203A; đ?&#x2018;&#x2018;đ??ľ = 20 ln đ?&#x2018;&#x2019; đ?&#x203A;ź đ?&#x2018;&#x2018;đ??ľ/đ?&#x2018;&#x161;đ?&#x2018;&#x2019;đ?&#x2018;Ąđ?&#x2018;&#x2019;đ?&#x2018;&#x;

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EXAMPLE : DQ0 TRACE ANALYSIS. Height or separation between layers (h) : 6 mil Width of the Trace (W) : 6.25 mil Length of the Trace (L) : 3444.64 mil Frequency of operation : 333 MHz for Data transmission Loss tangent : 0.035 Effective Dielectric Constant : 4.1 Characteristic impedance : As calculated from the Equation [1] : 48.95 ohms As calculated from the Tool : 48.95 ohms Attenuation constant : 0.247 Np/m = 4.94 dB/m Total Loss : 0.432 dB Electrical Length : 70.84 Degree 17

Propagation Delay : 590.35 pS


PARAMETRIC SWEEP

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PARAMETRIC SWEEP

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PARAMETRIC SWEEP : COUPLED LINE

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PARAMETRIC SWEEP : COUPLED LINE

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BENDING EFFECT

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BENDING EFFECT

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DQ0 SIMULATION IN MOMENTUM.

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DQ0 SIMULATION IN MOMENTUM.

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DQ0 SIMULATION IN MOMENTUM.

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DQ0 SIMULATION IN MOMENTUM.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION USING MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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ANALYSIS IN SPICE.

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• Extracted the Design parameter of a Trace using Allegro tool. • Calculated the other parameters using SERENADE, Lincalc, paper pen analysis. • Simulated trace in ADS. • Layout was drawn in momentum and the whole trace was created as component.

• Effect of bending was studied. 45


LAYER 12 Er=Er(FR-4)=4.10 4.10

PIN NO. A1 A3 A5 A8 A9 A10 A13 BA0 BA2

TYPE ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS CONTROAL CONTROAL

loss tangent = 0.035 U33 FROM AE15 AG14 AE14 AF13 AD13 AG12 AE12 AH16 AG15

Er(FR-4)=4.1 PIN NO. CKE DDRCS0# DDRCS1# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM1 DQM3 DQS3 MODT0 MODT1

TYPE CONTROAL CONTROAL CONTROAL DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA CONTROAL CONTROAL DATA CONTROAL CONTROAL

U33 FROM AE4 AH3 AD5 AH19 AD19 AG20 AH20 AH21 AE21 AH22 AD21 AE9 AH6 AH5 AG6 AH4 AE6 AD8 AF5 AE20 AF6 AF7 AE3 AD4

loss tangent thickness=4.5 = 0.035

U59 TO 101 99 97 93 91 105 116 107 85

TYPE2 OUT OUT OUT OUT OUT OUT OUT OUT OUT

LAYER 11 loss tangent = 0.035 U59 TO TYPE2 79 OUT 110 OUT 115 OUT 23 BI 25 BI 35 BI 37 BI 20 BI 22 BI 36 BI 38 BI 61 BI 63 BI 73 BI 75 BI 62 BI 64 BI 74 BI 76 BI 26 OUT 67 OUT 70 BI 114 OUT 119 OUT

SERPENT YES YES YES YES YES YES YES VERY SMALL YES

thickness = 4.5

LENGTH WIDTH 3815.82 3715.3 3801.94 3771.24 3855.9 3716.98 3813.81 3668.04 3718.94

ELECTRIACAL LENGTH 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25

Z0 39.3561 38.3193 39.2129 38.8963 39.7695 38.3366 39.3353 37.8319 38.3569

TD 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63

0.6542 0.6369 0.6518 0.6465 0.661 0.6372 0.6538 0.6288 0.6376

thickness = 6 SERPENT YES YES YES YES YES DIFF SIZE MULTIPLE SMALL YES YES SMALL YES YES YES YES YES SMALL NO YES YES YES SMALL NO NO

LENGTH WIDTH 3494.87 3511.29 3700.03 3335.23 3466.38 3338.88 3274.83 3288.1 3398.7 3286.5 3445.02 3425.95 3274.22 3234.48 3295.57 3196.54 3345.64 3471.25 3328.46 3422.04 3326.35 3384.06 3646.83 3746.01

ELECTRIACAL LENGTH 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25

Z0 36.0458 36.2152 38.1618 68.5926 71.2899 68.6677 67.3504 67.6233 69.8979 67.5904 70.8506 70.4584 67.3379 66.5206 67.777 65.7403 68.8067 71.39 68.4534 35.2947 34.3077 69.5969 37.6131 38.6361

TD 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95

0.5991 0.602 0.6343 0.5718 0.5943 0.5724 0.5614 0.5637 0.5827 0.5634 0.5906 0.5873 0.5613 0.5545 0.565 0.548 0.5736 0.5951 0.5706 0.5867 0.5703 0.5802 0.6252 0.6422


LAYER 6 Er(FR-4) = 4.1

PIN NO. A0 A2 A4 A6 A7 A11 A12 A14 BA1 CAS# RAS# WE#

TYPE ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS CONTROAL CONTROAL CONTROAL CONTROAL

loss tangent = 0.035 U33 FROM AD15 AH14 AF14 AH13 AH12 AH11 AH0 AF11 AH15 AG4 AD7 AE5

U59 TO 102 100 98 94 92 90 89 86 106 113 108 109

TYPE2 0UT 0UT 0UT 0UT 0UT 0UT 0UT 0UT 0UT 0UT 0UT 0UT

LAYER 6 Er(FR-4) = 4.1

PIN NO. DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM0 DQM2 DQS0 DQS2

TYPE DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA CONTROAL CONTROAL DATA DATA

thickness 4.5

SERPENT YES SMALL YES YES YES YES YES YES NO YES YES SMALL

U59 TO 5 7 17 19 4 6 14 16 43 45 55 57 44 46 56 58 10 52 13 51

TYPE2 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT BI BI

ELECTRIACAL LENGTH 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25

Z0 39.8017 37.9688 38.713 37.9323 37.8952 38.1471 37.5038 38.9264 37.9146 36.4133 38.5488 38.001

TD 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63 51.63

0.6616 0.6311 0.6435 0.6305 0.6299 0.6341 0.6234 0.647 0.6302 0.6053 0.6408 0.6316

LAYER = 5

loss tangent = 0.035 U33 FROM AF16 AE17 AH17 AG17 AG18 AH18 AD18 AF19 AG10 AH9 AH8 AD11 AH7 AG7 AF8 AD10 AE18 AF10 AF17 AG9

LENGTH WIDTH 3859.03 3681.32 3753.47 3677.78 3674.18 3698.6 3636.23 3774.16 3676.06 3530.5 3737.55 3684.44

thickness = 6

SERPENT YES YES YES YES YES MANY YES NO YES YES YES YES SMALL NO YES YES YES SMALL YES YES

LENGTH WIDTH 3444.67 3501.83 3354.99 3378.88 3386.81 3350.56 3506.87 3436.19 3348.08 3297.99 3290.63 3484.19 3265.88 3285.34 3341.28 3515.73 3473.04 3447.58 3417.47 3358.1

ELECTRIACAL LENGTH 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25

Z0 70.8434 72.0189 68.999 69.4903 69.6534 68.9079 72.1226 70.669 68.8569 67.8267 67.6754 71.6561 67.1664 67.5666 68.717 72.3048 35.8207 35.5581 70.284 69.063

TD 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95 48.95

0.5905 0.6003 0.5752 0.5793 0.5806 0.5744 0.6012 0.5891 0.574 0.5654 0.5641 0.5973 0.5599 0.5632 0.5728 0.6027 0.5954 0.591 0.5859 0.5757


all dimensions are in mil resistance in ohm time delay(TD) in nano sec U33 Processor Chip U59 memory Chip

Research_study_of_Crosstalk_in_Stripline_and_Microstrip_traces_Girish_IIT_Delhi.  

Research study of Crosstalk in Stripline & Microstrip traces on Freescale’s MPC8315 Board done at IIT Delhi.