Page 1

STUDY AND DESIGN ANALYSIS OF INTERCONNECTS BETWEEN DDR II RAM AND MPC8315E PROCESSOR. BY GIRISH KUMAR AJMERA [2012CRF2503] 1

HEMANT KUMAR SINGHAL [2012CRF2966]


BOARD FILE : MPC8315E • Allegro Free viewer.

2


STUDY ABOUT THE ARCHITECTURE OF BOARD. • Clock circuitry • Processor : MPC8315E • DDR Controller

3


16 LAYERS PCB • Signal Traces • Ground Planes • Power Planes

4


LAYER 5 [V]

5


LAYER 5 [H]

6


LAYER 11 [V]

7


LAYER 12 [H]

8


DDR RAM  PROCESSOR 1. 200 pin small outline dual in-line memory module 2. 64 Traces for data Transfer. [DQ0 – DQ63] These are for bidirectional data input/output.

3. Differential data strobe option. Source synchronous mode of operation is also there with 8 traces. For Reading of data edge is edge is aligned, for writing the data center is aligned.

9


10


DDR II RAM

Processor

11


EXAMPLE : DQ0 TRACE ANALYSIS. • What kind of line? • Layer in which line is etched out? • Design parameters of the line? • Width of trace? • Length of trace? • Dielectric constant of material? • Separation between two layers? • Loss Tangent? • Frequency of operation?

These all things can be known from the Allegro Free viewer, as the board file contain all the parameters

12


EXAMPLE : DQ0 TRACE ANALYSIS. • Calculation of Characteristic impedance of the line. (Asymmetric Strip Line) 𝑍0 = 2(𝑍𝑜1 ||𝑍𝑜2 ) 𝑍𝑜1 = 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 𝑜𝑓 𝑠𝑦𝑚𝑚𝑒𝑡𝑟𝑖𝑐 𝑠𝑡𝑟𝑝𝑙𝑖𝑛𝑒 𝑤𝑖𝑡ℎ ℎ𝑒𝑖𝑔ℎ𝑡 2𝐻1 + 𝑇 𝑍𝑜2 = 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 𝑜𝑓 𝑠𝑦𝑚𝑚𝑒𝑡𝑟𝑖𝑐 𝑠𝑡𝑟𝑝𝑙𝑖𝑛𝑒 𝑤𝑖𝑡ℎ ℎ𝑒𝑖𝑔ℎ𝑡 2𝐻2 + 𝑇 Characteristic impedance of a symmetric strip line is given by 𝑍0 =

30𝜋 𝑏 ( ) 𝜀𝑟 (𝑊𝑒 +0.441𝑏

Where We is the effective width of the conductor and is given by 𝑊𝑒 𝑏

𝑊 𝑊 = 𝑤ℎ𝑒𝑛 > 0.35 𝑏 𝑏 𝑊 𝑊 2 𝑊 = − 0.35 − 𝑤ℎ𝑒𝑛 < 0.35 𝑏 𝑏 𝑏

13


1.56 mil L4

1.38 mil 1.56 mil đ?&#x2018;?01 = 60 đ?&#x2018;&#x153;â&#x201E;&#x17D;đ?&#x2018;&#x161; đ?&#x2018;?02 = 41.3 đ?&#x2018;&#x153;â&#x201E;&#x17D;đ?&#x2018;&#x161;

2.655 mil

H2 = 4.215 mil T = 0.69 mil L5

2.655 mil So Z = 48.95 ohm 4.5 mil

H1 = 9.215mil

L6

2.06 mil 1.38 mil 2.06 mil

L7 14


15

This Tool is available online at http://www.eeweb.com/toolbox/asymmetric-stripline-impedance


EXAMPLE : DQ0 TRACE ANALYSIS. â&#x20AC;˘ Calculation of Attenuation (due to dielectric). 2đ?&#x153;&#x2039; 2đ?&#x153;&#x2039;đ?&#x2018;&#x201C; đ?&#x153;&#x2013;đ?&#x2018;&#x; đ?&#x2018;&#x2DC;= = Ć&#x203A; đ?&#x2018;? tan đ?&#x203A;ż đ?&#x203A;źđ?&#x2018;&#x2018; = đ?&#x2018;&#x2DC;. 2

đ?&#x203A;źđ?&#x2018;&#x2018; đ?&#x2018;&#x2013;đ?&#x2018;&#x203A; đ?&#x2018;&#x2018;đ??ľ = 20 ln đ?&#x2018;&#x2019; đ?&#x203A;ź đ?&#x2018;&#x2018;đ??ľ/đ?&#x2018;&#x161;đ?&#x2018;&#x2019;đ?&#x2018;Ąđ?&#x2018;&#x2019;đ?&#x2018;&#x;

16


EXAMPLE : DQ0 TRACE ANALYSIS. Height or separation between layers (h) : 6 mil Width of the Trace (W) : 6.25 mil Length of the Trace (L) : 3444.64 mil Frequency of operation : 333 MHz for Data transmission Loss tangent : 0.035 Effective Dielectric Constant : 4.1 Characteristic impedance : As calculated from the Equation [1] : 48.95 ohms As calculated from the Tool : 48.95 ohms Attenuation constant : 0.247 Np/m = 4.94 dB/m Total Loss : 0.432 dB Electrical Length : 70.84 Degree 17

Propagation Delay : 590.35 pS


PARAMETRIC SWEEP

18


PARAMETRIC SWEEP

19


PARAMETRIC SWEEP : COUPLED LINE

20


PARAMETRIC SWEEP : COUPLED LINE

21


BENDING EFFECT

22


BENDING EFFECT

23


DQ0 SIMULATION IN MOMENTUM.

24


DQ0 SIMULATION IN MOMENTUM.

25


DQ0 SIMULATION IN MOMENTUM.

26


DQ0 SIMULATION IN MOMENTUM.

27


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

28


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

29


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

30


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

31


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

32


DQ0 SIMULATION USING MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

33


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

34


DQ0 SIMULATION IN MOMENTUM. â&#x20AC;˘ We created a component of this layout using the momentum. Now that component can be directly used in the schematic.

35


ANALYSIS IN SPICE.

36


ANALYSIS IN SPICE.

37


ANALYSIS IN SPICE.

38


ANALYSIS IN SPICE.

39


ANALYSIS IN SPICE.

40


ANALYSIS IN SPICE.

41


ANALYSIS IN SPICE.

42


ANALYSIS IN SPICE.

43


ANALYSIS IN SPICE.

44


• Extracted the Design parameter of a Trace using Allegro tool. • Calculated the other parameters using SERENADE, Lincalc, paper pen analysis. • Simulated trace in ADS. • Layout was drawn in momentum and the whole trace was created as component.

• Effect of bending was studied. 45

Study and design analysis of interconnects between ddr  

A Research study of Crosstalk in Stripline & Microstrip traces on Freescale’s MPC8315 Board. conducted at Indian Institute of Techn...