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DESIGN AND OPTIMIZATION OF HIGH EFFICIENCY MULTI-STANDARD MULTISTAGE DOHERTY POWER AMPLIFIER. Presenter: Girish Kumar Ajmera [2012CRF2503] Supervisor: Dr. Karun Rawat Prof. Ananjan Basu Centre for Applied Research in Electronics, IIT Delhi.


Hunt For Green Communication Power Supply

Typical Standards GSM (GMSK) : 900/1800 MHz 3.01 dB PAPR EDGE : 6.18 dB PAPR WCDMA (3G-UMTS) : 2.14 GHz 10 dB PAPR OFDM(Wi-Max, LTE) : 12 dB PAPR POWER CONSUMPTION IN BASE STATION Others 10%

Base Station PA Input Signal

Cooling 24%

Cooling System

Signal Processi ng 9%

PA 57%

With Upcoming Technologies, Emphasis is on to minimize the spectrum use with more sophisticated Modulation schemes typically having 8-10 dB PAPR, it becomes difficult PA consumes highest Power in the Base station and Converts Roughly 40-50 % into Heat. to achieve both efficiency and linearity simultaneously.


I,max

SIMPLE DOHERTY ARCHITECTURE Quarter Wave Line , ZT

Back-off Region

PA #1

2 Way Power Splitter

đ?‘?1 =

Input Power

đ?‘?đ?‘‡

2

I,max/2

Z1

đ?‘?đ?‘‡ 2 đ?‘?1 = đ?‘?đ??ż I1

đ??ź2 đ?‘?đ??ż 1 + đ??ź1

Saturation Region

0

Vin,max/2

Vin,max

I2 PA #2 Quarter Wave Line, ZT

For Phase Compensation. For ZL=25 â„Ś , ZT = 50 â„Ś Z1 at Saturation = 50 â„Ś Z1 at Back-off = 100 â„Ś

Quarter Wave Line 35.35 â„Ś

Z2

ZL

Z2 = ∞

đ?‘?2 =

đ?‘?đ?‘‡ 2

50 â„Ś

đ??ź1 đ?‘?đ??ż 1 + đ??ź2

For PA#1 Load seen at Back-off is twice the load seen at saturation. Thus Load Modulation is done using Impedance Inverting Network : Quarter Wave Section


SIMPLE DOHERTY : SIMULATION PA Design 1. 2. 3. 4. 5.

Device Specification : Cree CGH40010 10 W GaN HEMT Biasing : VDS = 28 V, IDS = 200 mA. Stabilization : Input Matching : Conjugate Matching Output Matching : Optimum Load matching (Using Load Pull)

For this single PA Efficiency is found to be 76-77 % with 41-41.5 dBm Output Power at a single Frequency 1.96 GHz .


SIMPLE DOHERTY : SIMULATION Comparison with Class AB

Single Class AB with Gate Bias -2.75 V

Frequency = 1.96 GHz, Pin=33 dBm

Balanced Class AB with Gate Bias -2.75 V

2 Stage Doherty Architecture with Peaking Bias = -5.75 Volt


MULTI STAGE DOHERTY PA#1

PA#1 and PA#2 are Designed as Standard Doherty Configuration. When Both PA#1 and PA#2 are approaching their Saturation, PA#3 is turned on, which modulates the load seen by PA#1-#2 Pair. From Now onwards, PA#1-#2 Pair can be treated as a Single Amplifier operating at Saturation. Such Concept is iterated inserting further PA , Each introducing a new break Point , resulting in theoretical efficiency as

PA#2

Input Power

Load Combiner. PA#3

N Way Power Splitter.

PA#N Ref: Analysis and Design of High Efficiency Multi Stage Doherty Power Amplifier, Nuttapong Sriratna, Phillip E. Allen.


DESIGN OF LOAD COMBINER FOR MULTI-STAGE DOHERTY.

V 1 , I1 PA #1

Z1

Îť/4 , Z0

PA #2

From N Way Splitter

Îť/4 , Z0(N-1)

đ?‘–

V 2 , I2

Z2

Îť/2 , Z0

Depending on the Back-off Level Z0i can be calculated.

ZB

đ?‘?đ?‘œđ?‘– = đ?‘…đ??ż

ZA Îť/4 , Z0(N-2)

PA #3 Z3

Îť/4 , Z01

PA #N

(N-1)Îť/4 , Z0

VL , IL

đ?‘— (đ?‘–+đ?‘˜)/2

� �

ZC

Load, RL

��

2đ?‘—−đ?‘˜

=

đ??ľđ?‘– 1020

As derived by Neo et al. 2007, Pelk et al., 2008


DESIGN OF LOAD COMBINER FOR MULTI-STAGE DOHERTY : LOAD MODULATION

V 1 , I1

For N=3 PA #1

Z1

λ/4 , Z0

PA #2

From 3 Way Splitter

V 2 , I2

PA #3

V L , IL

For High Power Region, When All 3 PA are on.

b=V3/V2

𝑍2 =

𝛾1 𝛾2 𝑅𝐿 (𝑏𝛾2 − 1)

ZB

𝑍𝑜22 2 𝑍1 = = 𝛾 𝑅𝐿 2 𝑍𝑜12 ( 𝑅𝐿 )

V 3 , I3

Z3

𝑍1 = 𝛾1 𝛾2 𝑅𝐿

At Low Power Operation, Only PA#1 is On

ZA λ/4 , Z01

Z2

λ/2 , Z0

λ/4 , Z02

𝑍3 =

𝑏𝛾1 𝑅𝐿 (𝑏𝛾1 − 1)

Load, RL

𝑍2 = 𝑍3 = ∞

At medium Power Operation, PA#1 is at Saturation and PA#2 is also on. 𝑍𝐴 = 𝑍𝐵||𝑍2

𝑍022 𝑍𝐵 = 𝑍1

𝑉𝐿2 𝑉22 𝑉12 𝑉22 = = + 𝑅𝐿 𝑍𝐴 𝑍1 𝑍2

𝑍1 =

a=V2/V1

𝑍02 𝛾1 𝛾2 𝑅𝐿 = 𝑎 𝑎

𝑎 ∗ 𝑍02 𝑍𝐴 𝑎𝛾12 𝛾2 𝑅𝐿 𝑍2 = = 𝑍3 = ∞ 𝑎 ∗ 𝑍02 − 𝑍𝐴 (𝑎𝛾2 − 𝛾1)


Implementation of Phase Offset Lines in Doherty Architecture IDS, Main

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation IDS, Peaking

Device Intrinsic Parasitic and Packaging Parasitic

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation

Quarter Wave Line , ZT =50 Ω

Device Intrinsic Parasitic and Packaging Parasitic

At Backoff Output Impedance of Matching Network in Peaking Side should be an Open Circuit So that There is No leakage From Main to Peaking. If a Phase offset line is implemented Output impedance can be made to approximate open circuit.


Implementation of Phase Offset Lines in Doherty Architecture IDS, Main

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation IDS, Peaking

Device Intrinsic Parasitic and Packaging Parasitic

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation

50 Ω Phase Offset Line (δC)

In Saturation mode PA is Matched Near to 50 Ω. So shift due these Phase offset line will not affect Matching at Saturation.

50 Ω Phase Offset Line (δP)

Quarter Wave Line , ZT =50 Ω

Device Intrinsic Parasitic and Packaging Parasitic

Near to Open Circuit.


DUAL BAND DOHERTY ARCHITECTURE

Dual Band Power Splitter at f1,f2

Input Power

Dual Band PA#1

Dual Band ∓ 900 , ZT at f1,f2

Dual Band ∓ 900 line Require Transmission Line with Same Characteristic Impedance ZT and Same Electrical Length 900 at f1,f2.

Dual Band Power Splitter Require Dual Quarter Wave Line of 70.7 ohm at f1,f2 50 Ω Dual Band Phase Offset line (δc) at f1,f2.

50 Ω Dual Band Phase Offset line (δc) at f1,f2.

Dual Band ∓ ZT at f1,f2

900

,

Dual Band PA#2

Dual Band ∓ 900 , ZT at f1,f2

50 Ω Dual Band Phase Offset line (δP) at f1,f2.

Dual Band PA Require Design of Dual Band Input & Output Matching Circuit . It also Need Design of Dual Band ∓ 900 line for Biasing.

50 Ω Dual Band Phase Offset line (δP) at f1,f2.

Load 50 Ω

Dual Band Phase offset line Require Dual Band Transmission Line with Same Characteristic Impedance and Dual Electrical Length at f1,f2.

Dual Band Impedance Transformer at f1,f2


DESIGN OF DUAL BAND TRANSMISSION LINE * As reported By K. Rawat et. al, 2011

Zs , θS θC1

jBS

ZT , θT jBS

θC1

900

đ??śđ?‘œđ?‘ đ?œƒđ?‘‡ = đ??śđ?‘œđ?‘  đ?œƒđ?‘† − đ??žđ?‘†đ?‘–đ?‘› đ?œƒđ?‘† 900

θC2

On Comparing the ABCD Matrix of Both Structures,

θC2

Frequency Varying Image Impedance Feature of Pi- Type Structure is exploited to Make Dual Band Transmission Line*

đ?‘?đ?‘ 2 2 2 = 1 − đ??ž + 2đ??žđ??śđ?‘œđ?‘Ą(đ?œƒđ?‘† ) đ?‘?đ?‘‡

đ??ž = đ?‘?đ?‘ đ??ľđ?‘†

To Get These Design Parameters These Two Equation has to be solved Simultaneously at two desired frequencies.

Matlab Code is Written to solve these Equations iteratively at two frequencies in order to get 1. Same Electrical Length and Dual Characteristic impedance at two frequencies 2. Same Characteristic Impedance and Dual Electrical Length at two frequencies


Dual Band Quarter Wave Line of 50 Ohm

Response : Dual Band 50 Ohm 900 line at f1=1.96GHz & f2=2.35 GHz

Results Obtained from MatLab

Layout

DUAL BAND TRANSMISSION LINE : DESIGN EXAMPLE


Dual Band Phase Offset Line of 50 Ohm with Phase Delay 1000 at 1.96 GHz and 280 at 2.35 GHz

Response : Dual Band 50 Ohm Phase offset Line with 1000 at f1=1.96GHz & 280 f2=2.35 GHz

Results Obtained from MatLab

Layout

DUAL BAND TRANSMISSION LINE : DESIGN EXAMPLE


DESIGN AND OPTIMIZATION OF DUAL BAND TRI STAGE DOHERTY POWER AMPLIFIER. For Proof of Concept, At the Place of Dual Band PA, A Broadband PA Module is used. Wilkinson Based 3 Way Power Splitter is Used which is also wideband covering Chosen frequencies. Using the Concept of Dual Band Transmission Line, 1. Dual Band Phase offset lines are Made 2. Tri- Stage Doherty Load Combiner is Designed By Replacing Each of Quarter Wave Line By its Equivalent Dual Band Line.

Simulation is done in ADS with all the Real Components with Two Frequency Chosen as 1.96 GHz which is Standard for Wideband-Code Division Multiple Access and 2.35 GHz which is Standard for LTE.


Input Power

Wilkinson Power Divider @ 2.155 GHz

Wilkinson Power Divider @ 2.155 GHz

Terminated By 50 Ω

To PA#1 Dual Band λ/4 , 50Ω

Wilkinson Power Divider @ 2.155 GHz

Dual Band λ/2 , 50Ω

3 Way Power Splitter with Dual Band ∓ 900 Phase Compensation Line.

Dual Band Wilkinson Power Divider can be realized Using Monzon Impedance Transformers. For the Chosen Set of Frequencies A simple Wilkinson have enough band.

To PA#2 To PA#3

There is further scope for using Hybrid Coupler for Power Splitting which also incorporate the Phase Compensation Line. Further Analysis can be done to design a generic N Way Dual Band Power Splitter using Hybrid Coupler with desired Phase Difference at the Output.


Dual Band

From PA#1

λ/4 , 100Ω

From PA#2

Dual Band λ/4 , 25Ω

Dual Band Impedance transformer λ/4 , 25Ω

Load, 25Ω

Load, RL

From PA#3 Dual Band Tri Stage Output Load Combiner With Impedance Transformer.

Further Scope is to use T Section Structure for Dual Band Transmission Line to have a better Layout Pattern for Output Load Combiner. As with T-Type Structure there is only One Stub Which can be Flipped in the gap between two PAs. On Using PiType Structure Additional Line has to be patterned to maintain Sufficient Spacing between Stubs of Two Dual Band Line.


Simulation Result* for Dual Band Tri-Stage Doherty At 10 dB Back-off Drain Efficiency is roughly 70% .In a Typical Class AB Configuration at 10 dB Back-off Drain Efficiency is lower than 20%

Drain Efficiency Vs Output Power (in dBm) @ 1.96 GHz


Simulation Result* for Dual Band Tri-Stage Doherty

Drain Efficiency Vs Output Power (in dBm) @ 2.35 GHz


Zs=Zin*

Dual Band Output Matching Network Optimum Load Matching

PA

Zin=Zs*

Another Way is to Use the Dual Band Stubs and Dual Band Impedance Transformer*.

PA Y1 = G1+ jB1 at f1 Y2 = G2 +jB2 at f2

50Ω

Real Load

Low Pass Matching Network embedding Reactive Part of Load as L/C

1. Embedding of Reactive Part of Load in prototype Matching Network. 2. Extension form Low Pass to Dual Band Pass Matching Network.

However, generally The Optimum Load Point is clustered and there is not huge variation with frequency. So A Point Matching ZOptimum can be done. Such As Multi Section Chebyshev Transformer, Monzon Transformer Can be used. But As Explained Earlier Zoptimum is not real Due to Device Intrinsic and Packaging Parasitic.

ZLoad

A New technique is under analysis for Dual Band conjugate Input Matching. Code is written in Matlab, which provides desired parameters for a dual band conjugate matching circuit.

It is not Conjugate Matching. So Load can not be mapped to Shunt/Series RC/RL model. Further Work Needs to be done to Have an Optimum Dual Band Output Matching.

Y1 = G1 at f1 Y2 = G2 at f2

θC1

900 θC2

jB1 at f1 jB2 at f2

∓ 900 at f1,f2 ZT1 at f1 ZT2 at f2 Dual Band Dual Impedance Transformer

Load, 50Ω

Dual Band Input Matching Network Conjugate Matching

*As Reported By K. Rawat et.al , 2011


Results Obtained from MatLab

Design of Dual Band* Conjugate Matching Circuit.

Return Loss Response for Dual Band Conjugate Matching Circuit at 400-560 MHz, & 800-1080 MHz It is observed that problem of unrealizable values of L, C can also be solved by tuning the Values in such a way that LC product remains constant. *Extension of the idea by R. Levy et.al, 1964

ADS Schematic Using Lumped Components


Future Perspective 1. Dual Band Input Matching Technique : Conjugate Matching 2. Dual Band Load Matching Technique for Complex Load to Real Impedance. 3. Shrinking the Size of Dual Band Transmission Line : Analysis of T- Structure Transmission Line to find a converging Solution for Dual Band Transmission Line 4. Complete Design of a Dual Band Multi Stage Doherty with High Efficiency. 5. Design of N Way Dual Band Hybrid Coupler incorporating Dual Band Phase Compensation Line 6. Extension of Dual Band Transmission line to Tri-Band 7. Extension of Dual Band Matching Techniques to Tri Band 8. Modification in Multi Stage Doherty Architecture : In Conventional Multi-Stage Architecture Load Modulation of Main PA stops at a certain power level, leaving in it deep saturation region, that causes degradation in linear performance. 9. LINC (Linear Amplification Using Non Linear Components) implementation

To be Continued ..


1. Context of Proposed Research : Hunt For Green Communication 2. Simple Doherty Architecture : How it modulates the load to improve the Efficiency of PA at Back off. 3. Simulation Results of a Simple Doherty PA based on cree CGH40010F, 10 Watt Device, operating at 1.96 GHz with more than 70% Drain efficiency. Also shown the comparison of simple Doherty with Classical balanced Mode class AB PA. 4. Multi Stage Doherty Architecture : It is required for deeper Back off regions, as the simple Doherty (2 Stage) is limited to 6 dB back off level only. 5. Load Combiner Architecture : By Mathematical Analysis*, showed how it modulates the load to improve the efficiency at several back off levels simultaneously. 6. Implementation of Phase Offset line in simple Doherty : It stops any current leaking from Main to *As derived by Neo et al. 2007, Pelk et al., 2008 Auxiliary. 7. Dual Band Doherty PA Architecture and what is required to move from single Band to Dual Band. Same Electrical Length and Dual Characteristic impedance at Dual frequencies Same Characteristic Impedance and Dual Electrical Length at Dual frequencies 8. Mathematical Analysis of Dual Band Transmission Line in which Frequency Varying Image Impedance Feature of Pi- Type Structure is exploited to Make Dual Band Transmission Line. This now has been extended for T type Structures as well. In addition to that methodology for design of Tri band transmission line is also done. 9. Design of Tri Stage Dual Band Doherty PA


Size : 37 cm X 16 cm


DUAL BAND 50 Ω QUARTER WAVE LINE : SPECIFICATIONS ZS, θS @f1 jBS(f1) jBS(f2)

jBS(f1) jBS(f2)

ZT, θT

θT =±90º @ f1 and f2 50Ω @ f1 and 50Ω @ f2 Fig.2

* As reported By K. Rawat et. al, 2011

Fig.1

900 Phase shift @ 1.8 GHz @2.4 GHz

Fig.3

Fig.4

Fig.5


Implementation of Phase Offset Lines in Doherty Architecture IDS, Main

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation IDS, Peaking

Device Intrinsic Parasitic and Packaging Parasitic

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation

Quarter Wave Line , ZT =50 Ω

Device Intrinsic Parasitic and Packaging Parasitic

At Back off Output Impedance of Matching Network in Peaking Side should be an Open Circuit So that There is No leakage From Main to Peaking.

If a Phase offset line is implemented Output impedance can be made to approximate open circuit.


Implementation of Phase Offset Lines in Doherty Architecture IDS, Main

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation IDS, Peaking

Device Intrinsic Parasitic and Packaging Parasitic

PA Output Matching Network (Match To optimum Load)

Zopt,1 at Back-off Matching Network is Zopt,2 at Saturation designed to Match the 50 Ω to Zopt at 2Ropt =100 Ω at Back-off Saturation Ropt = 50 Ω at Saturation

50 Ω Phase Offset Line (δC)

In Saturation mode PA is Matched Near to 50 Ω. So shift due these Phase offset line will not affect Matching at Saturation.

50 Ω Phase Offset Line (δP)

Quarter Wave Line , ZT =50 Ω

Device Intrinsic Parasitic and Packaging Parasitic

Near to Open Circuit.


Dual Band Phase Offset Line : Operation & specifications

Θ1 =700 @ f1 = 1.8 GHz Θ1 =1400 @ f1 = 2.4 GHz

Carrier Offset Line Operation

Fig.1

Fig.2

Peaking Offset Line Operation


Dual Band Tri Stage DoherTY Power Amplifier Simulation Results Comparison of Doherty PA with Typical Balanced Mode Class AB PA, at two Frequencies of Operation f1=1.8 GHz and f2=2.4 GHz

Fig.1

Fig.2


Dual Band Tri Stage DoherTY Power Amplifier Simulation Results Drain Efficiency at Saturation,6 dB Back off and 12 dB Back off and gain at Saturation at two Frequencies of Operation f1=1.8 GHz and f2=2.4 GHz

Fig.1

Fig.2


Dual Band Tri Stage DoherTY Power Amplifier Simulation Results Comparison of Drain Efficiency, Gain and Pout at two Frequencies of Operation f1=1.8 GHz and f2=2.4 GHz

Fig.1

Fig.2

Fig.3


Future Perspective 1. 2. 3. 4. 5. 6. 7.

Measurement of Dual Band Tri Stage Doherty PA. Implementation Digital Pre Distortion (DPD) for linearized Performance of PA. Extension of Tri Band Transmission Line to Quad Band. Design of Tri Band Multi Stage Doherty PA Architecture. Multi Band Matching Solutions for optimum Load Matching. Design of N Way Dual Band Hybrid Coupler incorporating Dual Band Phase Compensation Line Modification in Multi Stage Doherty Architecture : In Conventional Multi-Stage Architecture Load Modulation of Main PA stops at a certain power level, leaving in it deep saturation region, that causes degradation in linear performance. 8. LINC (Linear Amplification Using Non Linear Components) implementation

To be Continued ..

Design and optimization of multi standard multi stage doherty power amplifier girish iit delhi  

Design and optimization for Multi Standard Multi Stage Doherty Power Amplifier done at IIT Delhi

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