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Jennifer Zhao General Manager of System Management Products

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CONTENTS

PULSE

Jennifer Zhao

GENERAL MANAGER OF SYSTEM MANAGEMENT PRODUCTS AT NXP

A conversation about how the inventors of I2C are constantly innovating to remain industry leaders.

NXP’s I2C GPIO Family

This new family of devices features Agile I/O, which helps integrate common system functions within the semiconductor.

Featured Products This week’s latest products from EEWeb.

4

Cloud-based Regression Testing for Chip Design This test allows designers to spot last minute tweaks or design flaws in a module.

Sudoku: A Logical Test

How to build a Sudoku program in the Java coding language.

Challenges for ESD-Robust Design

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An overview of design challenges in state-ofthe-art analog technologies.

RTZ

Return to Zero Comic

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PULSE

NXP Semiconductors provides high performance mixed signal and standard product solutions. The company was formerly known as Philips Semiconductors, which is cred for inventing the I2C interface over 30 years ago. To this date, the company maintains position as the number one supplier of I2C solutions and is determined to keep it that way.

Jennifer Zhao started working at Philips Semiconductors as a Regional Marketing Manager for microcontrollers and then moved to logic and interface products. Her rol within the company changed throughout the years, moving into higher level sales and marketing positions to better her understanding of customer’s needs. In 2009, sh became General Manager for the System Management Product Line at NXP, which is her current position at the company. We spoke with Jennifer Zhao about the key initiatives of the interface business line, about their broad I2C portfolio, and how the company is constantly innovating to maintain its position at the top.

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INTERVIEW

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PULSE What are the key initiatives in the interface business line? The key initiatives in my current role are maintaining NXP’s number one position in I2C products in the market. I’m also responsible for delivering financial targets that the company set for the product line. This includes top line revenue, gross margin, and EBITs, which stands for earnings before interest and taxes. I have also put a lot of focus on innovation and expanding our group to address some key growing markets, like the mobile sector. It’s a rapidly growing and competitive market, so you have to be fast-to-market. Of course, in order to achieve all of these goals, it’s important to have a strong team, so managing the team and the people involved is an important part of my role. At NXP, we put a lot of focus on employee engagement—we use Gallup employee engagement surveys, and we have a lot of activities around people management and engagement. With an engaged team, our chances of being a great company are greatly improved.

Could you give us an overview of NXP’s system management products? The system management product line consists of a broad portfolio of I2C products. I believe we have the broadest portfolio of I2C in the market. This portfolio includes I2C I/O expanders, muxes and switches, bus buffers, level shifters, and bus controllers. In addition, we also have local and remote temperature sensors, constant current and voltage source LED controllers, and LED flash drivers. You can see that some of these families are really targeting mobile and computing. It’s a pretty expansive portfolio.

My experience in the embedded space has really helped me in working with this portfolio. With the interface products, we developed them around the core. The ways in which we work with the SoC microprocessors and microcontrollers is really important, so we focus primarily on the interface. It’s important to understand the trends on the core, so processors are really important for us. We also work with our microcontrollers group really closely. In some of the microcontrollers like the Cortex M0, we worked to have it support the I2C I/O, which is the first microcontroller of its kind to be able to support it.

Do you find that you have customers that are using your interface products even if they aren’t using your processor? Yes, we do. For example, a lot of our products work well with SoC, which NXP supports. We work closely with some of the SoC vendors like Qualcomm and we also have a really strong relationship with Intel.

Do a lot of your products in the interface area have development boards available? Absolutely. For all of our products, we provide demo boards. The newest one that we have is called Fast-mode Plus development kit. Basically, we have the main board connect to our microcontroller and then have multiple daughter cards so you can plug in and evaluate the parts. Pretty much, for every product, we supply a demo board, which makes it much easier for the designers to evaluate the parts.

How are NXP’s system management products positioned in the market?

Philips Semiconductor (now NXP) invented the I2C-bus in 1982. Since its creation, I2C has been adopted by several competitors to bring I2C products to the market—all of which are compatible with NXP’s original system.

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NXP is the leading I2C product provider in the market. The I2C bus was created by Philips Semiconductor in the early 1980s, which was first used in TVs and really expanded from there. The I2C allows easy communication between components that reside on the same circuit board. It’s not just to be used on single boards, but to connect components which are linked through a cable. It’s able to be adapted widely because it’s simple and flexible, which are key characteristics that engineers are looking for. That’s why this bus is really attractive for a lot of applications.


INTERVIEW

Jennifer Zhao (Center) with system management team.

Philips Semiconductor migrated to NXP back in 2006, so we took over the portfolio and IP, which included the I2C-buses.

What trends in technology do NXP’s products support? As I mentioned earlier, we work very closely with the core chip, because we provide interface solutions. One trend we are seeing is that the SoC is going towards lower voltage applications. A few years ago, the SoC was operating at 3.3V, but later on, it went down to 1.8V. Now, the lowest has gone down to 0.9V. Many peripherals are still operating at 3.3V, so there is a strong need for level translation. Our level shifter family addresses this trend in the market. We have products that translate voltages from 1.8V to 3.3V and vice versa. The other trend we see is higher speeds. The original I2C ran at 100Kb per second, then we developed a Fast-mode I2C specification, which runs at 400Kb per second. Now, we’re seeing customers adopting 1Mb per second, which we call Fast-mode Plus I2C-bus. We have all these different speed families to support the higher speed trends in the system.

“At NXP, we put a lot of focus on employee engagement...With an engaged team, our chances of being a great company are greatly improved.”

What is the company culture like at NXP? I would describe NXP as a high performance culture. We also have a lot of focus on values. We implement the highest company values, which we try to carry out with all of our employees. We stress raising the bar, engaging curiosity, taking initiative, developing the core competency, and working together. Our motto is “Customer Focused Passion to Win.” It’s been a great pleasure working with a really professional team and we all want our company to be a great company. ■ Visit: eeweb.com

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PULSE

With added complexity in embedded systems comes the need for more pins especially general purpose inputs and outputs that are more versatile. In late 2012, NXP Semiconductors—the inventors of the I2C-bus—launched a GPIO family of devices to remedy these limitations. The new family of peripheral expanders includes an innovative feature set called Agile I/O that helps integrate common system functions within the semiconductor. This new family allows the user to expand their interface without taking up much additional board space.

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Device Family Overview “These peripheral expanders are an expansion of our current GPIO family, which is the broadest portfolio in the market,” says Jennifer Zhao, General Manager of NXP’s System Management product line. NXP’s new line is able to expand the two wires of the I2Cbus into 8-bit and 16-bit, inputs and outputs. These general-purpose I/O pins have consolidated interfacing functions that eliminate the amount of external components needed on the PCB, which saves space and simplifies the design.

Addressing Industry Trends The Agile I/O expanders also have a reduced package size, which is another trend in the industry. “We have what we call HLA BGA, which is a really small 0.4 mm pitch package to address the trend of saving board space,” says Jennifer Zhao. Although the new packages are significantly smaller, there is no cost premium.


FEATURED ARTICLE

Addressing the industry trend of lower voltages, the new GPIO family has very low voltage operation, from 1.65 to 5.5 volts. In addition, it has a very low standby current with a maximum of 3mA. With an expansive

voltage range to choose from, NXP has allowed customers the option of selecting the optimal device for their applications. Some devices have two supply pins to allow separate voltage selections for the I2C-bus interface and the I/O interface.

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PULSE

PCAL Family

Fm+ Development Kit

One of the unique features of the Agile I/O expanders is what NXP calls the PCAL family. “The L stands for latch,” Zhao told us, “which allows the input to lock in changes on input pins and to the input port register.” This allows for more flexibility for the design, which is one of the key characteristics of the Agile I/O family. Latching inputs are important in applications like alarm system monitoring, where one alarm in a series is going in and out intermittently. “If your inputs don’t latch,” says Chris Anderson of EEWeb Tech Lab, “then by the time you’re microcontroller gets around to servicing that interrupt, and you may have missed which input has changed.” This would prevent receiving any information about which alarm is going off. The Agile I/O devices also has a programmable pull-up and pull-down resisters, open drain output, programmable output drive strength and an interrupt mask—options that NXPs customers have expressed interest in.

NXP has an I2C development kit called the OM13320, which includes a number of target devices for exploring the I2C-bus. The kit is centered on the OM13260 development board, as well as GPIO target boards, bridge board and buffer board with additional separately purchased DIP EVM board, DIP adapter boards and daughter cards. The Fm+ Dev system includes a Graphic User Interface (GUI) that allows point and click operation from your PC to control all the registers of the 16-bit Agile I/O GPIO PCAL6416A and several other devices when they are electrically connected. There is also an Expert Mode which allows the more advanced users to write code specifically for the device to operate in a specific manner.

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World’s lowest power capacitive sensors with auto-calibration NXP is a leader in low power capacitance touch sensors, which work based on the fact that the human body can serve as one of the capacitive plates in parallel to the second plate, connected to the input of the NXP capacitive sensor device. Thanks to a patented auto-calibration technology, the capacitive sensors can detect changes in capacitance and continually adjust to the environment. Things such as dirt, humidity, freezing temperatures, or damage to the electrode do not affect the device function. The rise of touch sensors in modern electronics has become a worldwide phenomenon, and with NXP’s low power capacitive sensors it’s never been easier to create the future.

Learn more at: touch.interfacechips.com


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PULSE

Cloud-Bas Regression Test for Chip Desig 18

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sed ting gns

TECH ARTICLE

HarnHua Ng Founder, Plunify

Background

Many compilation cycles are needed throughout the course of developing an FPGA design. As an IP vendor, it is imperative that changes to an IP core will not break the entire circuit. As a circuit designer, you would like to try different “what if� scenarios--for example, if you constrain the circuit in a certain way, or if you add a particular IP core, or if the cache size of your embedded microcontroller is changed to a particular value. Whether your design in a particular configuration will fit into different target devices might be an unknown in the first place.

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PULSE

R

egression testing and benchmarking have other equally important objectives, for example, in cases where customers or the marketing team would like to compare your IP cores against a competitor’s. Whether a design has been modified, or the logic around a specific module which is part of a bigger system has been changed, or if there is a last-minute netlist tweak, regression testing involves running a series of tests and then analyzing the results to see if all is well.

CHALLENGES

REGRESSION TEST DETAILS

How long it takes to run the tests and how fast one can analyze the results are key factors in an effective regression, benchmarking or design exploration effort. Many times, FPGA designers have to forgo trying really interesting “what-if” scenarios for a variety of reasons, including the ones below:

• Target device: Altera Stratix III device with 142K Logic Elements

• Schedules are tight and the design changes required for the testcase in mind were too complicated or numerous to be done in a reasonable amount of time. • Designers did not want the resulting builds to consume too many server resources and slow down colleagues’ builds. • It was too tedious to send a large number of builds out to the local compute server farm to be scheduled and executed.

SOLUTION In a cloud-computing environment, running and analyzing builds at scale becomes much easier. Making use of a cloud-based FPGA design platform, this case study shows how regression testing can be done for an FPGAbased embedded system that uses the LEON3 processor IP core. In this example, the impact on utilization and timing performance of different RAM configurations for the LEON3 processor is evaluated by varying the data width and depth of the processor’s external memory modules.

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• FPGA tool version: Quartus II 12.0 • RAM module configurations: • Number of words, W: 16, 32, 64, 128, 256, 512, 1024 • Word widths (bits), D: 64, 128, 256, 512, 1024, 2048, 4095, 8192 Total number of configurations: 56 • Build server specification: 2 virtual CPU cores, 17GB RAM, high IO speed Total number of servers used: 56 Each configuration is made into an individual Quartus II project and stored in a folder named after it, like the following: … leon3mp/W16_D64/ leon3mp/W16_D128/ leon3mp/W16_D256/ …

RUNNING BUILDS IN PARALLEL The designer issues builds using a Tcl API known as FPGAAccel that the cloud platform provides. Executing Tcl commands at the top-level “leon3mp” folder, each project’s build is submitted to compile simultaneously.


TECH ARTICLE

Figure 1: Timing and area results

Figure 2: Time taken for synthesis and implemtation across all builds

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PULSE Excerpts from a typical build script:

ANALYSIS

… cd W16_D64 quartus_sh –t ~/fpgaaccel/tcl/quartus/ cloudcompile.tcl –project leon3mp –op compile –src cd .. cd W16_D128 quartus_sh –t ~/fpgaaccel/tcl/quartus/ cloudcompile.tcl –project leon3mp –op compile –src cd .. …

After compilation, analysis and comparison of the results is another potential time-sink. Over time, most engineers will build up a collection of custom scripts to automate compilation builds and parse results. However, changes in tool versions, design report formats and server environment require extra engineering hours in maintaining those scripts. Having analysis capabilities already in the tools can save much effort and time.

RESULTS Not all builds are expected to be completed successfully, because some of the RAM configurations are theoretically too resourceheavy to either fit into the target device or pass timing. To prevent any build from running for too long, the designer specified a maximum runtime of 24 hours. The platform has a feature where any build taking more than a specified duration would be automatically terminated. When all the builds were done, nine out of the 56 configurations failed, as shown in Figure 1. Upon examination, eight of the builds exceeded the maximum runtime, indicating that any RAM configuration with 1024 words could not be implemented in a reasonable amount of time. One of the builds crashed during the Fitter stage, due to insufficient memory even though 17GB was allocated to it.

Figures 1 and 2 show basic timing and area statistics, comparing the successful builds to see which ones performed better. Looking at the former, the configuration with 64 memory words and a word width of 128 bits had the best maximum frequency whereas its 2048-bitwidth counterpart had the worst. From a qualitative point of view, this design’s timing seemed more ‘sensitive’ when the number of memory words was 64. Some of the RAM module configurations like W64_D2048, despite being smaller, had worse timing performance than larger ones such as W256_D2048. Within configurations with the same number of memory words, it was clear that certain bit-widths were better suited for this design in terms of the timing results. The total time needed to run all the builds was about 33 hours and average build time was 42.1 minutes. Because of the ability to spawn a virtual server for each build, all the builds were done in slightly more than an hour’s time. In general, larger RAM configurations need more compilation time, which is not surprising. Again, comparing configurations of the same number of memory words and smaller data bit-widths sometimes takes longer to synthesize and implement.

SUMMARY Due to limitations on compute resources, a cloud-based design platform for FPGA designs enables design teams to carry out benchmarking, regression testing and design optimization efforts that often cannot be done locally, or does not have the priority for immediate execution. For competitive analysis or technical support reasons, product lines need to be constantly re-evaluated or re-compiled on new or legacy tool versions. These tasks require engineers and IT teams to maintain legacy tool versions and server environments. This case study shows how a cloud platform can save time and effort for design teams due to its scalability and flexibility in having on-demand compute resources available. ■

» CLICK HERE Failed configurations

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Get the Datasheet and Order Samples http://www.intersil.com

Power Factor Correction Controllers ISL6730A, ISL6730B, ISL6730C, ISL6730D The ISL6730A, ISL6730B, ISL6730C, ISL6730D are active Features power factor correction (PFC) controller ICs that use a boost topology. (ISL6730B, ISL6730C, ISL6730D are Coming Soon.) The controllers are suitable for AC/DC power systems, up to 2kW and over the universal line input.

The ISL6730A, ISL6730B, ISL6730C, ISL6730D are operated in continuous current mode. Accurate input current shaping is achieved with a current error amplifier. A patent pending breakthrough negative capacitance technology minimizes zero crossing distortion and reduces the magnetic components size. The small external components result in a low cost design without sacrificing performance. The internally clamped 12.5V gate driver delivers 1.5A peak current to the external power MOSFET. The ISL6730A, ISL6730B, ISL6730C, ISL6730D provide a highly reliable system that is fully protected. Protection features include cycle-by-cycle overcurrent, over power limit, over-temperature, input brownout, output overvoltage and undervoltage protection.

• Reduce component size requirements - Enables smaller, thinner AC/DC adapters - Choke and cap size can be reduced by 66% - Lower cost of materials • Excellent power factor over line and load regulation - Internal current compensation - CCM Mode with Patent pending IP for smaller EMI filter • Better light load efficiency - Automatic pulse skipping - Programmable or automatic shutdown • High reliable design - Cycle-by-cycle current limit - Input average power limit - OVP and OTP protection - Input brownout protection

The ISL6730A, ISL6730B provide excellent power efficiency and transitions into a power saving skip mode during light load conditions, thus improving efficiency automatically. The ISL6730A, ISL6730B, ISL6730C, ISL6730D can be shut down by pulling the FB pin below 0.5V or grounding the BO pin. The ISL6730C, ISL6730D have no skip mode.

• Small 10 Ld MSOP package

Two switching frequency options are provided. The ISL6730B, ISL6730D switch at 62kHz, and the ISL6730A, ISL6730C switch at 124kHz.

• TV AC/DC power supply

• Desktop computer AC/DC adaptor • Laptop computer AC/DC adaptor • AC/DC brick converters

100

VI

VLINE

Applications

+

VOUT

95

EFFICIENCY (%)

90

VCC ISEN

GATE

ICOMP

GND

ISL6730

VIN

FB

ISL6730A, SKIP

80 ISL6730C

75 70

COMP BO

85

65

VREG

60

0

20

FIGURE 1. TYPICAL APPLICATION

40 60 OUTPUT POWER (W)

80

100

FIGURE 2. PFC EFFICIENCY

TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6730

February 26, 2013 FN8258.0

VERSION

ISL6730A

ISL6730B

ISL6730C

ISL6730D

Switching Frequency

124kHz

62kHz

124kHz

62kHz

Skip Mode

Yes-Fixed

Yes-Fixed

No

No

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S u d a Logical Test Sudoku is a perfect logical test with some fun involved. For those who have never played Sudoku, it is a game starting with a grid containing 36 elements. The elements are arranged in rows and columns in a 9 by 9 grid style. The board generally comes with squares filled in based on difficulty. The number of elements shown does not directly correlate with the difficulty which is an important distinction. The order of the elements makes the difference. Shown below is an example of a Sudoku board.

The order they are to be filled in should match with every other row, column and 3x3 box. With this in mind, there are a slew of possibilities the numbers can be hidden to create different difficulties for the user. With a certain amount of logical reasoning, most puzzles can be solved without guessing. This got me thinking. I am studying computer engineering and from my experience this has been a degree with elements of both electrical and software engineering. Logic is present throughout all aspects of these engineering topics. With this in mind, building a Sudoku program in the Java coding language is a great test in improving both logical and engineering skills. This is not an article about building a Sudoku program from scratch and the possibilities that are available to do so. Like with any computer program, there are multitudes of different ways to structure and code a Sudoku program.

Figure 1. Example Sudoku Board

This appears to be around a medium difficulty Sudoku puzzle. The goal is to fill in this board so every cell has just one number. The numbers you choose are required to be chosen out of the range of 1 through 9. Notice how 3x3 boxes have been bolded as to distinguish a constraint. There should be no duplicates in the following fashion: • Each row should have the numbers 1–9 • Each column should have the numbers 1–9 • Each 3x3 box should have the numbers 1–9

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Originally, it seemed the simplest way to structure the programming for this project is to use FOR loops and IF statements. With some tinkering and multiple attempts later, a Sudoku program was materializing. This was possible because you could randomly generate a number. Then recursively through FOR loops you could eliminate from which constraints to eliminate numbers. For example, if a 3 was generated, you could save the three in an array, and you could then only generate 1–2 and 4–9. Doing this created a random board without duplicates.

Following the generation of the board came hiding the numbers. As I have mentioned before, just hiding more numbers does not determine difficulty. Some easy Sudoku puzzles have more hidden numbers than harder difficulty puzzles. So, how do you hide numbers in a way that changes difficulty? Essentially, when answering this question you have to ask yourself, “How do you want users answering your puzzle?” It then boils down to figuring out a similar version of a Sudoku solver. The key to discovering a solution lies in understanding how the game works scientifically. In order to create challenging puzzles in Sudoku, algorithms based on Knuth’s Algorithm X to solve the Exact Cover problem need to be developed. This solution is termed as the Dancing Links technique, which is fairly useful in software engineering. Here begins the problem. Exact Cover, Knuth’s Algorithm, and the Dancing Links Technique. We have what is technically called the “Exact Cover” problem. On Wikipedia’s terms, the exact cover problem is as such; “given a collection S of subsets of a set X, an exact cover is a subcollection S* of S such that each element in X is contained in exactly one subset in S*. One says that each element in X is covered by exactly one subset in S*. An exact cover is a kind of cover” (Wikipedia 2013). In relation to Sudoku, the exact cover problem is associated with the restrictions that make Sudoku the game it is. Each element represents the individual cells. The S* references the constraints of the game Sudoku. The collection


TECH ARTICLE

o k u Rob Riemen Electrical Engineering Student of these subset S* is what is coined as S. S is then of the set X which is the game of Sudoku itself. To simplify this concept, we take a look at the following matrix:

done until the program finds the correct rows that solve the problem. This is exactly what would help in finding correct solutions for Sudoku. Recently, we have been referring to a matrix that contains just 1’s and 0’s. When referring to Sudoku, the Dancing Links Technique works in the same way as with 1’s and 0’s. The program has to determine which number it is analyzing and the numbers it touches. Then through Dancing Links it can “dance” around the 9x9 matrix until it has a record of what numbers exist. From this array of numbers, the program would then be able to determine which number fills an empty cell.

Figure 2. Exact Cover Matrix Example

The problem is to select a certain number of rows so that each column contains a 1. Knuth’s Algorithm provides a way to select rows in which all columns contain a 1. The solution to this example picks Rows A, D, and F. These satisfy the constraints. With an algorithm, the user has to develop a solution that will cycle through each column and row. In software engineering, circular doubly linked lists of the 1s in the matrix are used to check the progress of finding the correct rows. Each 1 in the matrix can check every square it is touching with a “link.” In the end the algorithm efficiently can find a solution choosing the correct rows. This technique using the circular doubly linked lists is referred to as the Dancing Links Technique. As the code moves around the matrix the linked lists cause the links to “dance” with partner links. This is

By figuring out a way to solve a Sudoku puzzle through Dancing Links, we can choose how to hide numbers. From analyzing how the algorithm works, we see that when the program can easily eliminate numbers in rows, it can execute faster. In reality, our minds are working similarly to the algorithm. We scan each row, column, and box to see what numbers are available to us. The more significant numbers that are shown, the easier the puzzle becomes. Say, for example, there are five to seven 6’s shown on the board. From this information, we know that there are only several more possibilities available for 6’s. Hypothetically, this is compared to the two 1’s that are shown. As the program is dancing through the program and more of a certain number is shown, execution time decreases. The program will have a much easier time completing the range of 6’s than the range of 1’s.

Using this information, the algorithm will be implemented to dance through and randomly choose more of similarities above to un-hide as to change difficulty. For example, several rows and columns may show more numbers, as well as more 2’s, 3’s, 5’s and 8’s are un-hidden as to give an easy difficulty. Then the next board generated will increase the number of hidden numbers in this fashion. Or, in context with my statement earlier, keep the same number of squares hidden, but switch the numbers that are hidden and what order they are shown. Conclusion Obviously, Sudoku puzzles can be graded on difficulty based on the number of numbers revealed. It will be easier to solve a puzzle with plenty of numbers shown, and will be harder to complete when more are hidden. But, this is not the most efficient way to randomly create playable Sudoku boards. When coding and analyzing the exact cover problem in Sudoku, Knuth’s Algorithm helps solve the problem. The Dancing Links Technique is implementing Knuth’s Algorithm into the software which helps essentially solve an unsolved Sudoku board. Using this knowledge of how this algorithm and technique works, we can develop an efficient way to generate random Sudoku boards that actually match their true difficulty. Bibliography “Exact Cover.” Wikipedia. Wikimedia Foundation, 03 June 2013. Web. 17 Mar. 2013.

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TECH ARTICLE

Gianluca Boselli Texas Instruments, Analog ESD Team

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s the popularity of portable electronics, “smart devices�, and automotive electronics keeps increasing, so does the need for analog functions to be embedded in ICs. This drives the demand for specific analog technologies, which are becoming a bigger and bigger portion of the overall semiconductor market.

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PULSE With some simplification, analog technologies can be binned into three main categories:

◉ ELECTROSTATIC DISCHARGE (ESD) An electrostatic charge transfer from a body to an object, which results in high currents (several amperes) during a short period of time (hundreds of nanoseconds.

1. High-Power BiCMOS: Main targets are the power devices’ RDSON and breakdown voltage. A very wide array of components’ type is usually featured (Bipolar, CMOS, LDMOS, and DEMOS devices), to cover applications from Low-Voltage (LV, few Volts) up to very High-Voltage (HV, hundreds of Volts). 2. High-Speed BiCMOS: Main target is the speed of the bipolar devices, to support high-speed applications, up to several hundreds of GHz. 3. Analog-CMOS: Main feature is a high-density CMOS logic, along with low-parasitic, lownoise and high-quality passives. They tend to be “derivatives” of CMOS technologies. Electrostatic discharge (ESD) events can be caused by IC’s human handling/testing during manufacturing process and can lead to catastrophic damage. To guarantee ESD robustness against handling/testing, each IC is qualified against standard ESD tests, usually human-body model (HBM) and chargeddevice model (CDM).

To achieve the required level of ESD robustness, dedicated on-chip circuitry (typically referred to as “ESD Protection” or “ESD Clamp”) is added to each pad to absorb ESD energy to a safe level for the protected circuitry. In a typical ESD protection implementation, each pad-to-pad combination must have a valid ESD discharge path through an ESD protection (Fig. 1). There are many challenges that analog technologies pose in terms of ESD-robust design.

ESD TECHNOLOGY CHALLENGES One fundamental difference between CMOS and Analog technologies lies in the fact that the latter are often built modular. This allows the IC designer to select only a portion of available process masks, to exactly tailor design needs (not all the components available in a given process may be used for a design). From an ESD design standpoint this implies that ESD designers have to support identical ESD applications with a different mask set. This could be very challenging in that the actual behaviour of the ESD protection strongly depends on the mask set. In other words, several version of the same ESD protection may need to be built, depending on the mask set available. Another challenging aspect of analog technologies lies in the utilization model. While state-of-the-art CMOS technologies have a few years life span, analog technologies may be used for 10-15, and even 20 years. The resulting applications’ portfolio during this life span is quite a challenge for ESD design.

ESD DESIGN CHALLENGES Drain-Extended MOS

Figure 1: Typical ESD protection network implementation: a valid ESD discharge path must exist between each pad-to-pad combination.

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A drain-extended MOS (DEMOS) is a device where a same-type low-doped region is added to a high-doped drain region, or drain extension (Fig. 2). This impacts both voltage rating (i.e. breakdown increases) and drain-gate voltage drop (relevant for gate oxide reliability). On the other hand, this type of design degrades driving current characteristics, as the channel is in general not


TECH ARTICLE optimized for this junction. A more sophisticated version, the laterally diffused MOS (LDMOS), has better current driving characteristics. From an ESD standpoint, DEMOS transistors feature very low ESD robustness, i.e. the ability to withstand high current densities under ESD conditions. The DEMOS’ ESD weakness is a major challenge for efficient ESD Design, in that it requires special ESD protection circuitry that does not exercise DEMOS transistors during ESD events (which has an impact in terms of area). This specific issue has been addressed by multiple studies in the last 15 years, thanks also to the utilization of these components in state-of-the-art CMOS technologies. In a recent work [1] it has been shown that the blocking of the silicidation process over the high-doped/low-doped drain region (“SBLK” region in Figure 3) can significantly increase DEMOS transistors’ ESD robustness.

Figure 2: Cross-section of a generic lateral DEMOS transistor.

This construction basically increases the resistance on the drain side. While its detailed impact is rather complex, it can be viewed as a way to prevent non-uniform current conduction through the ESD current distribution over the entire width of the device. 3-dimensional TCAD electro-thermal simulation clearly depicts the uniform ESD current distribution along the entire width of the device with the blocking of the silicidation in the drain region (Fig. 4). This will allow some of the ESD energy to be dissipated by the DEMOS with such construction, thereby reducing constraints on the ESD protection design. High-Voltage Active FETs “Active FETs” are very popular ESD protection devices, typically for low-voltage applications. The name refers to the fact that the ESD current is shunted through MOS devices in active operation mode. This mode is enabled during ESD-conditions only, through an ESD event detector. The circuit is timed to remain in on-condition for the entire duration of the ESD events (1-2 microseconds). In CMOS technologies, where the oxide and the drain junction share the same voltage rating, the on-condition is achieved through transiently coupling the drain with the gate. A basic implementation of this concept is shown in Figure 5. For HV devices (like the aforementioned DEMOS and LDMOS), the drain rating can be much higher than the gate rating (for instance, drain could be rated 20V, while the gate only 3.3V). Therefore, a circuit like the one depicted would not work, as drain and gate would basically have the same voltage, leading to gate reliability issues (Fig. 5).

Figure 3: TOP: Typical DEMOS Transistor BOTTOM: DEMOS with blocking of the silicidation process.

A way to divide the pad voltage down to achieve an appropriate gate voltage is needed. This can be achieved with a source-follower stage (Fig. 6). This scheme allows typical HV devices to work within

Figure 4: TCAD simulation of DEMOS

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PULSE With reference to Figure 2, the integration of an SCR into any DeMOS (or LDMOS) is pretty straightforward, through the addition of a high-doped P-type diffusion within the drain well extension. As one can see from Figure 7, a pnpn structure with the mutually coupled npn and pnp, is formed. In addition, the presence of the gate can be used to further tune the HV-SCR ESD characteristics.

Figure 5: (Left) Typical low-voltage transiently triggered active-FET Circuit Figure 6: (Right) Basic transiently triggered active-FET circuit utilizing source-follower buffer

The fundamental issue with this type of SCRs is their ability to maintain power-scaling characteristics [2], as the pulse width of the applied ESD stress increases. More specifically, based on the maximum power dissipated by the SCR under 100ns ESD pulse, one would expect [2] a certain power dissipated under 200ns and 500ns ESD pulses. However, the actual maximum power dissipated under 200ns and 500ns ESD pulses is much lower than the expectation (Fig. 8). This is a significant issue, especially in the case of ESD pulses deriving from system-level events, where the stress duration can largely exceed that of standard HBM events. High-Voltage Bipolars HV bipolar devices are not immune to poor scaling power scaling characteristics, as highlighted for HV SCRs. This is highlighted in Figure 9 where the actual maximum power dissipated does not follow power-scaling law from 100ns on.

Figure 7: Generic HV SCR construction in a DEMOS (similar concept applies to LDMOS)

the normal drain and gate operating ratings. Additionally, it also provides two significant benefits over the circuit (Fig. 5): 1. The capacitance is much smaller as it drives a much smaller transistor. 2. The turn-on/turn-off time constants are separated out and can be individually optimized. High-Voltage Silicon Controlled Rectifiers (SCR) Silicon-controlled rectifiers (SCR) are pnpn structures. By virtue of the mutual coupling of the vertical pnp transistor and the lateral npn transistor embedded in this pnpn structure, SCRs are the most efficient devices in terms of ESD power dissipation. Once one of the two bipolars turns on, it will turn on the other one, and so on.

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Besides power-scaling issues associated to HV bipolar devices designed as ESD protection circuits, there is another aspect related to HV bipolars that needs to be considered: parasitic bipolars formed by N-diffusions tied to adjacent bondpads. With reference to Figure 10, bondpads (PAD1 and PAD2) usually have an ESD protection referenced to a common ground (GND). In the case of an ESD event from PAD1 to PAD2, the ESD current (red solid line in Figure 10) will flow from ESD Protection 1, through the common GND and ESD Protection 2, to reach PAD2. With the N-diffusions tied to PAD1 and PAD2, a parasitic npn bipolar is now formed (the common p-substrate acts as base of the bipolar), which can conduct current during ESD events and, eventually, fail. The main issue with this configuration is due to the fact that the base of the parasitic


TECH ARTICLE bipolar (common ground) has an elevated potential, due to ESD current flowing in ESD Protection 2. This makes the parasitic bipolar very susceptible to triggering and, hence, prone to failure. Unlike CMOS technologies, in Analog technologies it is pretty common to have multiple N-type diffusions to support many different voltage ratings and isolation techniques. Therefore, any permutation of N-type diffusions will create a parasitic in a scenario similar to that depicted in Figure 10. Considering the number of emitter, collector, base types and geometric effects, it is quite possible to generate hundreds of parasitic bipolars in a given technology. This is rather challenging for ESD design, in that the ESD protection network must be able to adequately protect the aforementioned parasitics.

ESD QUALIFICATION CHALLENGES “On-Chip” System-Level Requirements To guarantee robustness to ESD events during IC’s manufacturing process, HBM and CDM tests are performed. In the last few years, a new trend to require system-level ESD protection at IC level is emerging. Normally system-level ESD protection is addressed at system-level, by placing on the board (in proximity to ESD stress sources) dedicated transient voltage suppressors (TVS) circuits. The rationale behind the trend is that TVS can be eliminated (thereby reducing cost and system design complexity), if the individual IC’s are ESD system-level robust.

Figure 8: Power-to-failure for HV SCR. It can be seen that power-scaling law does not hold.

Without digressing into why this rationale is flawed, the impact of these requirements for IC-level ESD design is dramatic, not only in terms of ESD area but also in terms of design complexity and learning cycles needed. Custom ESD Level Requirements Typical ESD level requirements for IC-level ESD robustness are 2000V HBM and 500V CDM. Although it has been unambiguously demonstrated that 1000V HBM and 250V CDM provide very reliable ESD design in today’s manufacturing environment, certain customers may require >8KV HBM performance on selected pins to deal with unspecified system-level events. The impact of these requirements is, again, very significant in terms of area and development time.

Figure 9: Similar non-scaling power characteristics, as in the case of HV SCRs, are observed with 20V CER NPN.

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Figure 10: Parasitic NPN between two pad-connected N-type diffusions. The common p-substrate acts as base on the NPN.

ESD STRATEGY

REFERENCES

The breadth of analog technologies components portfolio and the subsequent large number of applications to protect, does not lend itself to a “single ESD strategy” that would fit all the requirements. Therefore, ESD engineers in analog technologies are looking at all ESD protection strategies, carefully weighting pros and cons to find the most suitable solution. 1. Active FETs: They are very effective and popular for low-voltage applications. However, for high-voltage applications, the combination of low FETs’ drive current and large area makes them less appealing. 2. Breakdown-based devices: They rely on parasitic bipolar npn or pnp. Npn-based are very popular thanks to excellent area/ESD performance trade-off. The main drawback is the difficulty to control performance over process variations. 3. S  CRs: These solutions are the most efficient in terms of area/ESD performance and they are pretty easy to design. However, inherent latch-up risks and difficult implementation from DRC-LVS standpoint, somewhat limit their usage. 4. S  elf-protection: This solution is very effective in the case of large output drivers, which can be designed to withstand ESD events as well. The drawback is the need for a co-design effort between the IP and ESD. As the relevance of Analog technologies has been rapidly increasing over recent years, in this work we have reviewed the ESD challenges associated to technology, design and qualification requirements.

[1] A. Salman et al, Proceedings of International Reliability Physics Symposium, 2012 [2] D.C. Wunsch and R.R. Bell, in IEEE Trans. Nucl. Sci., 1968 [3] IEC61000-4-2: Electromagnetic compatibility (EMC) – Part 4-2

About the Author Gianluca Boselli joined Texas Instruments (TI) in 2001 where he focused on ESD and Latch-up development for advanced CMOS technologies, with particular emphasis on process and modeling aspects. In 2007, his responsibilities extended into ESD development of TI’s Analog technologies portfolio, where he is now the manager of the Analog ESD Team. He completed his Master’s in EE at the University of Parma, Italy, in 1996. In 2001 he completed his Ph.D. at the University of Twente, The Netherlands, where he worked on high current phenomena in CMOS technologies. Dr. Boselli is currently a member of the Board of Directors of the ESD Association, where he is the Symposium Business Unit Manager, and serves on the Editorial Board of the IEEE Transactions on Device and Materials Reliability (T-DMR). He is an IEEE senior member and holds seventeen patents with several pending. ■

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