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April 2014

INTERSIL

POWERING THE SMART DEVICES OF THE FUTURE

Powering an FPGA System

Medical Power Design Standards

Necip Sayiner CEO of Intersil


All the forces in the world are not as powerful as an idea whose time has come. —Victor Hugo, 1800

Power Developer contains new ideas that come every month. —Power Developer Editors, 2013

POWERDEVELOPER

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RIGHT AT THE BEGINNING.

Power Developer

By Chris Ammann, Global Technical Marketing Engineer

As FPGAs continue to become increasingly powerful, adequately powering these devices becomes even more critical to unlock their full potential,IMPLEMENTATION yet often times the power design is left until nearly the end of the design process. The trend of lower moved away from thevoltages driver relative to shrinking process prevalent. Here are some basic geometries guidelines foristhe design of he parasitic capacitance a Dual now Stripline in levels Fig.1 under 1V. Some of today’s devices runas atshown voltage he layout can dominate, Lower voltage requirements for FPGAs and processors create 1. Close traces, decreasing the “D” dimension ate performance of the additional challenges, especially at inductance, higher currents, lowers the intrinsic Lo. that require der to minimize these serious attention when designing the power architecture for a new article describes a layout 2. Increasing the traceand width, W for will a decrease Lo. It’s important to think about plan power system ws the power stage toplatform. be as at the outset of the design. Supply placement, passive component om the driver and still work 3. Increasing copper thickness, T will increase Lo. selection and PCB design become even more critical as voltage asis of the operating theory is 4. Increasing will not change Zo but will and length even PCB traces and planes can MOSFETs is a pulse of drops currentacross components increase of parasitic capacitance s the drive conductorsintroduce substantial errorthe intoamount your system.

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CONTENTS TESTING The Exar XRP7714 is a four-channel step-down digital power controller and one of Exar’s XRP77xx series of programmable power management solutions that integrate high- and low-side gate drivers for each of the PWM channels.

TECH ARTICLE As such the XRP7714 was an ideal candidate

testing this Dual Stripline technique for Planningfor for Power indriving an FPGA System extending the gate range. The tests

and inductance that the driver will see. This will add to the losses in the driver.

on line with a capacitive nd Miller capacitance) then It’s not uncommon for each FPGA family to consist of a wide range be minimized. 5. Designs can accommodate some

were undertaken using the printed circuit board (PCB) layout shown below, taking account of the circuit configuration and design considerations described.

of products. The smallest FPGA may clock in at less than 100 MHz,

discontinuities (e.g.current vias, unequal traces) and require less than 1 Amp of peak for core logic,to while called a broadside allow for getting These runs are the largest in the family may needa14layout Ampsrouted. or more for core logic as chosen in order that notFPGAs as critical manycore digital signals. clocked at 300 MHz. withaslower voltage needs will produced from the current require a large amount current, which must bebysupplied with a and discharges the MOSFET 6. Theof capacitance is affected the distance celled by the proximity effect low noise floor andtoathe minimum ripple voltage ground amount plane, H of and thickness of the ents. This lowers the trace trace, T. The thinner the dielectric, the higher Dual Stripline. In addition the capacitance. Also the higher the PCB wered since the gate traces dielectric constant (K) the greater capacitance. ground plane.

al Stripline transmission line n created to match the typical 3-ohm drive stage te drivers. In the four layers e top and bottom (cross ductors are a power plane or AC perspective both can nd. The two inner conductors are the gate and source . These signals come from the power controller IC.

onal view of a Dual Stripline ower and ground planes ignal planes that connect to of the MOSFET

10 18

Figure 2. Circuit configuration used for the Dual Stripline test PCB layout with signal and return connections for each of the high- and low-side MOSFETS

24 32

TECH ARTICLE

From a PCB layout viewp should follow under the g adjacent signal layer. Fo gate drive (GH1 and LX1 to implement. However, drive (GL1 and PGND1) c ensure that PGND is not c places, which could redu Dual Stripline configuratio

Figures 3 and 4 show the (Figure 3) and internal Lay of an XRP7714 PCB layou Stripline configuration as p

Avnet Kintex-7 FPG Mini Module Plus

Extending MOSFET Gate Drive Inductors

TECH COLUMN

Figure 3. Layer 3 of the test PCB provides the gate drive signals (blue traces) from the XRP7714 power controller to the external high- and low-side power MOSFETS

Paralleling High Speed eGaN FETs

TECH ARTICLE

Figure 4. Layer 4 provides the high-side LX and low-side PGND MOSFET return signals (blue traces), which should follow the drive signal traces on layer 3 as closely as possible

Importance of Power Standards for Medical Applications

The shift to IEC 60601-1 3rd edition POWERING standards for medical THE SMART DEVICES devices, now in force in Europe, Canada, and the US, OF THE FUTURE Necip Sayiner - CEO of Intersil has signifi cant implications for medical device design.

COVER INTERVIEW Interview with Necip Sayiner - CEO of Intersil

Intersil is an industry-leading power management and IC solutions provider. With analysts predicting the mobile industry in the $40 billion range by 2016, Intersil decided to hone in on how it can serve that market best. The result has been a slew of power saving and sustainable products that will enable the kinds of powerful and efficient mobile devices of the future.

IEC 60601-1

We spoke with Necip Sayiner, CEO of Intersil, about Intersil’s core competencies as a company, and how they are tailoring their products to serve the ever changing demands of the industry.

38

What Is IEC 60601-1

TECH COLUMN

IEC 60601 is a series of technical standards the safety and effectiveness of medical electrical equipment.

Achieving Full Power Without TheCooling primary standard governing medical device design is IEC 60601-1 (medical electrical equipment).

Part 1: general requirements for basic safe essential performance). Often referred to s as “60601,” compliance with the standard become a de facto requirement to bring n medical devices to market in many count

Perfection in Power

Tackling Problems with Innovative Conce LEDs are now widely used in many different areas. They allow for lighting solutions that were simply not possible with conventional lighting equipment. This means, however, that LED drivers need to meet ever more

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Thomas Rechlin Senior FAE for Europe at R Gmunden, Austria


Power Developer

WHEN SHOULD YOU PLAN FOR POWER IN AN FGPA SYSTEM?

RIGHT AT THE BEGINNING. By Chris Ammann, Global Technical Marketing Engineer, Avnet

As FPGAs continue to become increasingly powerful, adequately powering these devices becomes even more critical to unlock their full potential, yet often times the power design is left until nearly the end of the design process. The trend of lower voltages relative to shrinking process geometries is prevalent. Some of today’s devices now run at voltage levels under 1V. Lower voltage requirements for FPGAs and processors create additional challenges, especially at higher currents, that require serious attention when designing the power architecture for a new platform. It’s important to think about and plan for a power system at the outset of the design. Supply placement, passive component selection and PCB design become even more critical as voltage drops across components and even PCB traces and planes can introduce substantial error into your system. It’s not uncommon for each FPGA family to consist of a wide range of products. The smallest FPGA may clock in at less than 100 MHz, and require less than 1 Amp of peak current for core logic, while the largest in the family may need 14 Amps or more for core logic clocked at 300 MHz. FPGAs with lower core voltage needs will require a large amount of current, which must be supplied with a low noise floor and a minimum amount of ripple voltage

4


TECH ARTICLES

Avnet Kintex-7 FPGA Mini Module Plus

5


Power Developer WHY THEN ISN’T POWER TACKLED IMMEDIATELY? FPGA-based board designers may not feel they have sufficient information. They face uncertainty, for example, about actual power requirements of the system since the gatelevel design is usually not finalized before the hardware is generated. They also need to deal with dynamic load requirements, as load may move rapidly from an inactive, low current situation to a full processing state and the extent of these requirements may not be appreciated at the onset of design. Since FPGAs are more flexible than the power supply circuits that power them, it is beneficial to consider a worst-case power system at the beginning of the design process. Once the FPGA family is selected, and the core logic supply voltage is set, tools are in place to determine the current consumption of the core logic on the FPGA manufacturer’s website and maximum current estimates can be found in FPGA power applications guides. Power supply design challenges inherent in all designs boil down to cost, size, noise and efficiency, and the tradeoffs between the four. Power design is all about tradeoffs, there is no one golden solution for all applications. While industrial and medical markets typically

MMP FPGA /SoC MODULE

favor size over cost, wireless tends to favor low noise, handheld and battery applications usually prioritize efficiency, and in consumer apps cost tends to be king. A key part of the design process is to determine the voltage requirements needed and the current requirements of each voltage rail. Xilinx provides assistance by making available power estimation spreadsheets for estimating the power requirements of an FPGA device, based on the required functionality of the FPGA. It is important that designers access and use these spreadsheets to ensure the use of appropriate powersupply and thermal- management components. A variety of power supply manufacturers offer complete power solutions for Xilinx FPGAs and have resources available to aid in device selection. Avnet has worked with several power supply manufacturers to create a series of paper designs for different 7 Series and Zynq devices. These designs were created around realistic power budgets and are intended to provide a starting point for the overall power architecture selection of your system. The Avnet Power Solutions Video

FMC Module (Optional)

MMP Baseboard II Figure 1. MMP Baseboard II

6

MMP Power Module


TECH ARTICLES USB 2.0 Connector

USB 2.0 ULPI PHY

RJ45 Connector

Ethernet PHY

1 GB DDR3

USB Connector

USB-UART

8 KB I 2C EEPROM

32 MB QSPI

XC7Z045 FFG900

Real-Time Clock

Micro SD Card Socket PS Reset

PJTAG Header LVDS OSC @ 200 MHz JX1 Connector 4 GTXs and 66 User I/O

Processing System

PS Clock @ 33 MHz

Programmable Logic

Programmable LVDS Clock 128 MB Flash

Power, GTX, User I/O, and Signals

JX2 Connector 4 GTXs and 66 User I/0

Figure 2. The Xilinx Zynq速-7000 All Programmable SoC Mini-Module Plus

Series is an educational resource available to guide designers through the power-system maze. Covering such topics as power supply testing, component selection, technology overviews and more, the series is a collection of valuable tutorials designed to let you ramp up your designs rapidly. FPGA development boards from Xilinx are designed with digitally controlled power supplies that make regulation adjustments to ensure supply voltages are within spec. The Mini Module Plus development system from Avnet uses a modular power supply that is available from multiple manufacturers. Remote voltage sensing is used on these power modules to achieve greater regulation accuracy at the load. Comprised of a modular MMP baseboard that supports an MMP FPGA/SoC module, an MMP power supply module, and a Low-Pin-Count (LPC) FPGA Mezzanine Card (FMC), the Mini Module Plus system provides flexibility for

FPGA/SoC evaluation and prototyping. Each MMP component is sold separately so that designers can configure their MiniModule Plus System to meet their particular prototyping needs. At the same time, a path exists for easy upgrading or migration through the replacement of the MMP FPGA or SoC module, while keeping the same MMP baseboard and MMP power module. The modular MMP allows designers to prototype and easily move the MMP FPGA/ SoC module or MMP power module to a custom baseboard. By using off-the-shelf MMP FPGA/SoC or MMP power modules, risk is reduced by using a fully tested module. An example is the Xilinx Zynq速-7000 All Programmable SoC Mini- Module Plus, a small system-on-a-module (SOM), with all the necessary functions and interfaces for a Zynq-7000 AP SoC system. The module can be combined with the Mini-Module Plus Baseboard II and a Mini-Module Plus Power

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Power Developer Supply for an out-of-box development system ready for prototyping. The kit includes the Zynq-7000 AP SoC MiniModule Plus with a Zynq-7000 AP SoC XC7Z0451FFG900 FPGA and the Xilinx ISE速 Design Suite: Embedded Edition (device locked to XC7Z045 FPGA).

MMP FPGA /SoC Module

1FFG676 FPGA and a Xilinx ISE速 Design Suite: Logic Edition Device locked to XC7K325T or FMC XC7K410T and bundled with the Kintex-7 MiniModule Module Plus. MMP (Optional)

Power

The Avnet Power modules are available from Module several manufacturers. Each partner designed MMP Baseboard II a common set of design their board to meet requirements, making them interchangeable to the user. Providing solutions from multiple Another example is the Kintex-7 FPGA MiniFigure 1. MMP Baseboard partners allows the customerIIto choose their Module Plus, a small system-on-a-module preferred vendor, as well as choosing the design (SOM), with all necessary functions and feel most comfortable interfaces for a Kintex-7 FPGA system. The The modular MMP allowsimplementation designers they to prototype and easily mo with. Since the intent was to have these power FPGA module is a complete system on a modules with a variety of module boards, the first module, packaging all the MMP necessary functions the FPGA/SoC module or work MMP power to a cust step was creating a worst case power budget needed for an embedded processor system baseboard. By using off-the-shelf MMP FPGA/SoC or MMP pow that could support all of our development board onto a small footprint. After the system, the following modules, risk is reduced byneeds. using a defining fully tested module. table was created to represent the worst case The kit includes one Avnet Kintex-7 Mini Module current draw for each required rail. Plus with a Kintex-7 K325T-1FFG676 or K410T-

An example is the Xilinx Zynq速-7000 All Programmable SoC M Module Plus, a small system-on-a-module (SOM), with all necessary functions and interfaces for a Zynq-7000 AP SoC syste The module can be combined with the Mini-Module Plus Baseboar BPI Crystal 64for MB Flash Kintex-7 and a Mini-Module Plus Power Supply an out-of-box developm @19.2 MHz XC7K325T or system EEPROM ready for prototyping. XC7K410T (16 KB)

USB 3.0 Connector ARM JTAG Header

FFG676

USB 3.0 MAC/PHY

USB 2.0 Connector

USB 2.0 ULPI PHY

256 MB DDR3 8 KB I2C EEPROM

XC7Z045 Programmable FFG900 LVDS Clock

RJ45

Ethernet PHY

LVDS OSC @200 MHz

1 GB DDR3

USB Connector

USB-UART

LVCMOS OSC @50 MHz

8 KB I2C EEPROM

RJ45 Connector Ethernet Connector PHY

XADC Header Power, Micro SD Card Socket

GTX, User I/O, and

JX1 Connector

PS Reset

4 GTXs and 66 User I/O

Signals

Miscellaneous Voltage Regulaors JX2 Processing Connector System 4 GTXs and 66 User 1/0

Programmable Figure 3. The Xilinx Kintex-7 FPGA Mini-Module Plus Block Diagram PJTAG Header LVDS OSC @ 200 MHz JX1 Connector

8

32 MB QSPI

4 GTXs and 66 User I/O

Logic

Real-Time Clock PS Clock @ 33 MHz Programmable LVDS Clock 128 MB Flash

Power, GTX, User I/O, and Configuration Signals

JX2 Connector 4 GTXs and 66 User I/0


ove tom wer

Minithe em. rd II ment

TECH ARTICLES The table only the voltages, currents Kintex-7 Mini Module Plus with a Thedefines kit not includes one Avnet and voltage banks they power, but also the Kintex-7 K325T-1FFG676 or K410T-1FFG676 FPGA and a Xilinx ISEŽ overall tolerance the supplies needed to be designed to. With tolerance requirements Design Suite: Logic Edition Device locked to XC7K325T or XC7K410T down a low as 2.5%, extra design measures bundled with the Kintex-7 Mini-Module Plus. wereand needed to ensure regulation accuracy. In an ideal design scenario, the power supplies would be placed right next to the load they The Avnet Power modulesthat are available from several manufacturers. supply, however in our system architecture placement was not feasible. As a result, remote Each partner designed their board to meet a common set of design sense capability was added, which senses the requirements, making them interchangeable to the user. Providing voltage at your load and makes regulation adjustments to maintain your set point. Remote solutions from multiple partners allows the customer to choose their sense is not trivial and adds its own set of unique challenges, but is one tool available designers preferred vendor, as towell as choosing the design implementation when optimal supply placement isn’t available. they feel most comfortable with. Since the intent was to have these Design files are available for each power module as well so that these designs can be reproduced power modules work with a variety of boards, the first step was in customer applications.

Providing solutions from multiple partners allows the customer to choose their preferred vendor, as well as choosing the design implementation they feel most comfortable with.

creating a worst case power budget that could support all of our development board needs. After defining the system, the following table was created to represent the worst case current draw for each required rail. Voltage Bank

Voltage (V)

Current (A)

Tolerance

1

6

3.00%

1.5/1.35

4

5.00%

1.8

6

5.00%

2

2

3.00%

Vcco

2.5

8

5.00%

Vcco

3.3

8

5.00%

1

6

3.00%

1.2

4

2.50%

Vccint/Vccbram Vcco Vccaux/Vccaux_io/Vccadc/Vcco/ MGTVccaux Vccaux_io

MGTAVcc MGTAVtt/MGTAVTTrcal Figure 4. MMP Power Module requirements table

Figure 4. MMP Power Module requriements table

The table defines not only the voltages, currents and voltage banks they power, but also the overall tolerance the supplies needed to be designed to. With tolerance requirements down a low as 2.5%, extra design measures were needed to ensure regulation accuracy. In an ideal design scenario, the power supplies would be placed right next to the load they supply, however in our system architecture that

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Power Developer

EXTENDING THE MOSFET GATE DRIVE CONDUCTORS by Using a Dual Stripline PCB Layout Configuration

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TECH ARTICLES

M

odern power management devices frequently combine digital control with high performance analog circuitry to provide a multi-channel power conversion solution. Integrating several digital pulse width modulation (DPWM) switching buck (step-down) regulators and their associated FET drivers with other power management, monitoring and protection functions on a single chip significantly simplifies system design, reducing costs and time to market, but interfacing these devices to the external power FETs can sometimes pose additional challenges. The on-chip gate drivers for such PWM regulators are typically optimized to drive both high-side and low-side MOSFETs to provide synchronous rectification operation. Due to their high current and high speed rise and fall times these drivers are normally required to be close to the MOSFETs they are driving. However, with multiple regulators on one chip, this isn’t always possible and in many applications there will be a need to place one or more rails at some distance from the controller. This article will introduce and examine from both a theoretical and practical standpoint a layout design technique that will allow the MOSFETs to be as much as 5 inches from the driver.

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Power Developer THEORY

IMPLEMENTATION

When MOSFETs are moved away from the driver (more than 1 inch) the parasitic capacitance and inductance of the layout can dominate, resulting in inadequate performance of the power system. In order to minimize these parasitic issues, this article describes a layout approach that allows the power stage to be as much as 5 inches from the driver and still work as expected. The basis of the operating theory is that the drive to the MOSFETs is a pulse of current and that if one views the drive conductors as a pulse transmission line with a capacitive termination (gate and Miller capacitance) then these parasitics can be minimized.

Here are some basic guidelines for the design of a Dual Stripline as shown in Fig.1

A Dual Stripline (also called a broadside coupled stripline) was chosen in order that the magnetic field produced from the current pulse that charges and discharges the MOSFET capacitance is cancelled by the proximity effect of the opposing currents. This lowers the trace inductance of the Dual Stripline. In addition radiated noise is lowered since the gate traces are enclosed by the ground plane. Figure 1 shows a Dual Stripline transmission line design that has been created to match the drive capability of a typical 3-ohm drive stage found in on-chip gate drivers. In the four layers shown in Figure 1, the top and bottom (cross hatched area) conductors are a power plane or ground, but from an AC perspective both can be considered ground. The two inner conductors on the signal planes are the gate and source leads to the MOSFET. These signals come from the internal driver of the power controller IC.

Figure 1. Cross sectional view of a Dual Stripline configuration with power and ground planes enclosing the inner signal planes that connect to the gate and source of the MOSFET

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1. Close traces, decreasing the “D� dimension lowers the intrinsic inductance, Lo. 2. Increasing the trace width, W will decrease Lo. 3. Increasing copper thickness, T will increase Lo. 4. Increasing length will not change Zo but will increase the amount of parasitic capacitance and inductance that the driver will see. This will add to the losses in the driver. 5. Designs can accommodate some discontinuities (e.g. vias, unequal traces) to allow for getting a layout routed. These runs are not as critical as many digital signals. 6. The capacitance is affected by the distance to the ground plane, H and thickness of the trace, T. The thinner the dielectric, the higher the capacitance. Also the higher the PCB dielectric constant (K) the greater capacitance.

Figure 2. Circuit configuration used for the Dual Stripline test PCB layout with signal and return connections for each of the high- and low-side MOSFETS


TECH ARTICLES TESTING The Exar XRP7714 is a four-channel step-down digital power controller and one of Exar’s XRP77xx series of programmable power management solutions that integrate high- and low-side gate drivers for each of the PWM channels. As such the XRP7714 was an ideal candidate for testing this Dual Stripline technique for extending the gate driving range. The tests were undertaken using the printed circuit board (PCB) layout shown below, taking account of the circuit configuration and design considerations described.

From a PCB layout viewpoint, each return etch should follow under the gate drive etch on an adjacent signal layer. For the high side MOSFET gate drive (GH1 and LX1) this should be easier to implement. However, for the low side gate drive (GL1 and PGND1) care must be taken to ensure that PGND is not connected in multiple places, which could reduce the benefit of a Dual Stripline configuration. Figures 3 and 4 show the internal Layer 3 layout (Figure 3) and internal Layer 4 layout (Figure 4) of an XRP7714 PCB layout that uses the Dual Stripline configuration as previously discussed.

Figure 3. Layer 3 of the test PCB provides the gate drive signals (blue traces) from the XRP7714 power controller to the external high- and low-side power MOSFETS

Figure 4. Layer 4 provides the high-side LX and low-side PGND MOSFET return signals (blue traces), which should follow the drive signal traces on layer 3 as closely as possible

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Power Developer TEST RESULTS To verify that the Dual Stripline configuration is performing as intended, three separate tests were conducted. The voltage waveform at the phase node (LX) was measured with a 250 MHz bandwidth oscilloscope and with differential probes directly at the pins of the MOSFETs. In these tests, the input voltage was 12 VDC and the output voltage was 3.3 V with a 12 Amp load. Test 1 used a DrMOS type power stage so that the gate driver is optimized for the MOSFET while the parasitic inductance and capacitance are minimized since all of the devices are in the same package. The DrMOS has an internal driver so that the trace length from the controller to the FETs is not a factor. Test 2 used discrete MOSFETs being driven by the XRP7714 drivers with a short distance between the XRP7714 pins and the MOSFET gate pins. Test 3 used the Dual Stripline configuration with the PCB layout shown in Figure 2 and Figure 3 with a distance of 5 inches between the

XRP7714 pins and the MOSFET gate pins. The reduced ringing in Test 1 with the DrMOS is attributable to the lower parasitics associated with close coupling of the gate drivers and power MOSFETs. When comparing the results from tests 2 and 3, it can be seen that phase node performance has not been degraded at all by using the longer gate drive traces. Furthermore, it is evident that this technique even compares reasonably well to the optimal integrated drivers on the DrMOS set up. Lastly, measurements were also made of the gate drive signals for the Dual Stripline configuration to verify that the distance hasn’t prevented the gate driver from exerting proper control over the gate at the point of phase node current commutation. Measurements also showed that the low side gate remains considerably lower than 1.8V when both the high to low and low to high transitions of the phase node occur, ensuring cross conduction cannot occur.

Ringing Test

Configuration

Test 1

DrMOS

5

4

45

40

Test 2

Discrete FET; short distance

6

5

100

50

Test 3

Discrete FET; 5� distance

6

5

100

50

Table 1. Summary of the Test Results

14

Rise Time (ns)

Fall Time (ns) Overshoot (%)

Duration (ns)


TECH ARTICLES CONCLUSION Correct layout is always a vital part of any good switch mode converter design. Experience dictates that adding additional distance between the gate drivers and power MOSFETs in such a design would be a violation of typical design principles. However, this article has shown that when attention is paid to the traces between gate drivers and the FETs, and a few simple Dual Stripline guidelines adhered to, a distance of 5” is achievable with virtually no impact on the overall performance of the converter. This in turn allows designers to take full advantage of the higher level of integration offered by the XRP77xx series of programmable multi-channel controllers without having to sacrifice the geographic flexibility afforded by individual POL solutions.

A BRIEF DISCUSSION ON IMPEDANCE, CAPACITANCE, AND INDUCTANCE CALCULATIONS An industry accepted formula for the characteristic impedance (Zo) and capacitance (Co) of a Broad Side Trace configuration is shown below. The formulas don’t take into account the affect of the outside ground planes. Their affect will further decrease the inductance so they will be beneficial, and the calculated inductance could be thought of as the worst case. This formula is an approximation based on simplifying assumptions as shown and should be used with the understanding that this is only valid over a range of values, and should be used as guidelines as none will give exact results. There are textbook and Web-based impedance calculators available online that do not consider the valid range of parameters, so user beware! It is interesting to note that almost all multi-layer PCBs with ground planes and power planes will introduce a stripline configuration since the signal trace is usually between two ground planes. The unique attribute of the Broad Side Trace and Dual Stripline is that the signal trace and its associated current return trace should be above and below each other as the trace makes its way across the PCB.

H

W

L

Figure 5. Broad Side Trace dimensions used in calculating impedance and capacitance

WHERE:

H = Dielectric thickness between the signal planes d = Dielectric thickness between the signal planes W = Width of the trace T = Thickness of the trace Zo = Characteristic impedance (Ω) Co = Intrinsic capacitance of the trace (pF/unit distance) Lo = Intrinsic inductance of the trace (nH/unit distance) K = Dielectric constant of PCB material

15


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Power Developer

18


TECH COLUMN

Alex Lidow

CEO of Efficient Power Conversion (EPC)

19


Power Developer

The previous columns in this series discussed the benefits of eGaN速 FETs and their potential to improve performance in a variety of applications. In this installment we will discuss the advantages of eGaN FETs in applications requiring higher currents and higher switching speeds. To verify the ability to parallel eGaN FETs, four parallel half bridges in an optimized layout operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A buck converter achieving efficiencies above 96.5% from 35% to 100% load will be demonstrated.

Alex Lidow

CEO of Efficient Power Conversion (EPC)

To read the previous installment, click the image above.

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FIGURE 1: Impact of high frequency loop inductance parasitic imbalance on transistor dynamic current sharing for a VIN=48 V, IOUT=25 A, GaN transistor based buck converter with two EPC2001 devices operating in parallel.

CHALLENGES OF PARALLELING HIGH SPEED GAN DEVICES In a previous How to GaN column, the importance of minimizing common source inductance and high frequency loop inductance were addressed [1]. For paralleling GaN transistors, these parasitics must not only be minimized to achieve the best performance, but also need to be balanced to ensure proper parallel operation. Figure 1 shows the impact of parasitic imbalance in the high frequency loop inductance for two parallel GaN transistors operating at 48 V for various common source inductances. As the difference between the high frequency loop inductance increases between the parallel devices, so does the dynamic current difference. From figure 1 it can also be observed that as the common source inductance decreases current sharing issues become more pronounced. The reason for the magnified current sharing issues at lower common source inductance is the higher switching speeds achieved as parasitic inductance decreases. As the current sharing worsens between parallel devices the electrical and thermal performance also degrades.


TECH COLUMN IMPROVING PARALLEL PERFORMANCE OF eGaN FETS As switching speeds steadily increase and parasitic inductances continue to decrease, improved methods must be developed to improve parallel performance. To effectively parallel high speed GaN devices the parasitic imbalance contributed by the printed circuit board (PCB) layout must be minimized. We will look at two different parallel layouts based on the optimal layout discussed in [1], and assess their ability to provide parallel performance similar to an optimized single transistor design. Each half bridge design contains four devices in parallel for the top switch (T1-4), and synchronous rectifier (SR1-4), and was tested in a buck converter configuration from 48 V to 12 V at a switching frequency of 300 kHz. In total, eight 100 V EPC2001 GaN transistors with a single TI LM5113 gate driver were used to achieve output power up to 480 W and output currents up to 40 A. In the first design, shown in figure 2a, the four GaN transistors are located in close proximity to operate as a “single” power device, with a single high frequency power loop. The drawbacks of this layout are that the high frequency loop inductance will increase as a result of the increased physical loop size, and

2a.

that devices will have imbalanced parasitics as their individual power loops are different. This leads to poor current sharing and thermal issues. The second design, shown in figure 2b, utilizes four distributed high-frequency power loops, located symmetrically around the single LM5113 gate driver. The design provides the lowest overall parasitics for each device pair and, most importantly, the best balancing of the parasitic elements, ensuring proper parallel operation. The voltage waveforms of the synchronous rectifiers switching transitions for the two designs are also shown in figure 2. For the single high frequency power loop design, the switching node waveforms are shown in figure 2a. The voltage transitions for the inner-most and outermost devices show an almost 2 ns switching time difference, which equates to about 25% of the total switching time. This voltage difference demonstrates the parasitic imbalance in this PCB layout. For the symmetrical, four high frequency power loop design, the switch-node waveforms is shown in figure 2b. The voltage transitions for the devices are almost identical, demonstrating this layout’s ability to balance the parasitics well. This balanced layout improves overall performance by offering better electrical and thermal performance.

2b.

FIGURE 2: Four parallel transistor GaN layouts and switching node waveforms with (a) a single high frequency power loop and (b) four distributed high frequency power loops (VIN=48 V, VOUT=12 V, IOUT=30 A, fsw=300 kHz, eGaN FETs: EPC2001).

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Power Developer

3a.

3b.

FIGURE 3: Thermal measurements of parallel GaN layouts with (a) a single high frequency power loop and (b) four distributed high frequency power loops. (VIN=48 V, VOUT=12 V, IOUT=30 A, fsw=300 kHz, L=3.3 ÂľH, eGaN FETs: 100 V EPC2001).

The thermal evaluation of the two designs, shown in figure 3, demonstrates the thermal imbalance of the single high frequency loop design. Figure 3a shows a hot spot developing on the devices handling a greater portion of the current as a result of parasitic imbalance. The top switch closest to the input capacitors, T1, has a maximum temperature more than 10°C higher than the top switch furthest away from the input capacitors, T4. For the four distributed power loop design, shown in figure 3b, there is a very good thermal balance,

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with negligible difference in temperature between devices, and a good distribution of the heat by avoiding clustering of the higher loss top devices on the PCB.


TECH COLUMN

SUMMARY

4a.

4b.

FIGURE 4: (a) Efficiency and (b) thermal comparison for conventional and proposed parallel GaN device designs (VIN=48 V, VOUT=12 V, fsw=300 kHz, L=3.3 uH, eGaN FETs: 100 V EPC2001).

By offering lower individual parasitics and better parasitic balance, the distributed four high frequency loop design has more effective paralleling. This results in better electrical and thermal performance as shown in figure 4. The distributed high frequency loop design offers a 0.2% gain in efficiency at 40 A, shown in figure 4a, and has an almost constant 10째C improvement in the maximum transistor temperature, as shown in the thermal comparison graph shown in figure 4b.

The introduction of high performance GaN devices offers the potential to switch at higher frequencies and efficiency than possible with traditional Si MOSFET technology. This column evaluated the ability to parallel eGaN FETs for higher output current applications by addressing the challenges facing paralleling high speed, low parasitic devices, and demonstrated an improved paralleling technique. For experimental verification of this design method, four parallel half bridges in an optimized layout were operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A buck converter, and achieved efficiencies above 96.5%, from 35% to 100% load. The design method achieved superior electrical and thermal performance compared to conventional paralleling methods and demonstrated that high speed GaN devices can be effectively paralleled for higher current operation. REFERENCES [1] A. Lidow. (2013, August 1). How to GaN: Driving eGaN FETs and Layout Considerations. EEWeb [Online]. Available: http://www.eeweb.com/blog/ alex_lidow/how-to-gan-driving-egan-fetsand-layout-considerations

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Power Developer

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TECH ARTICLES

The Importance of

POWER STANDARDS for Medical Applications

Standards are an integral part of product design and development, and are clearly important in medical applications. However, there is an additional aspect to standards for medical devices: while some technical standards—such as IEEE 802 for Wi-Fi—only define final performance, standards for medical design go much deeper, covering design methodology and verification, safety and risk assessment, implementation, and much more. Here we look at the medical standard IEC 60601-1 and the recent shift to the 3rd edition.

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Power Developer

The shift to IEC 60601-1 3rd edition standards for medical devices, now in force in Europe, Canada, and the US, has signifi cant implications for medical device design.

IEC 60601-1 What Is IEC 60601-1 IEC 60601 is a series of technical standards for the safety and effectiveness of medical electrical equipment. The primary standard governing medical device design is IEC 60601-1 (medical electrical equipment). Part 1: general requirements for basic safety and essential performance). Often referred to simply as “60601,� compliance with the standard has become a de facto requirement to bring new medical devices to market in many countries. Many of today’s products appear simple; yet embed sophisticated circuits and software that are invisible to the user. The IEC 60601-1 standard manages this reality by becoming intimately involved in the product-development process, going beyond performance test and verification. This is done because the product complexity generally yields a nearly uncountable number of potential test cases, permutations, and combinations in both normal and non-normal operating modes, and these cannot be assessed in the final design alone.

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TECH ARTICLES IEC 60601-1 EvolutIon

The Shift to 3rd Edition

The IEC 60601 standard has a long history with a number of revisions. The original IEC 60601-1 was published in 1977, and the 2nd revision was published in 1988. The 3rd edition was published by the IEC in 2005.

The 3rd edition changes this perspective, by requiring that the overall means of protection (MOP) be some combination of one or more means of operator protection (MOOP) and means of patient protection (MOPP).

IEC 60601 Medical Design Standards - 3rd Edition

Because the global shift to IEC 60601-1 3rd edition is still underway, 2nd and 3rd edition standards must stillndcoexist in equipment intended to ship the 2 edItIon internationally, creating an added level of Ac-dc power supplies and dc-dc converters have complexity for device designers who must always played a crucial role in the certification of account for both standards. medical equipment. That's understandable since

The 2nd Edition of power conversion, distribution, and protection.

These can be satisfied with basic safety insulation, use of protective earth ground, and isolation barriers that high-impedance path These can be satisfi ed present with basicasafety insulation, between input and output of course, it may use of protective earth ground, and isolation barriers be ambiguous if a particular circuit or function that present a high-impedance path between input falls-under MOOP categories; the and output of course, it mayor beMOPP ambiguous if a manufacturer needs to assess this and record it in particular circuit or function falls under MOOP or the risk management file. MOPP categories; the manufacturer needs to assess

Physics 101 teaches us that (seen both Ac-dc power supplies andpower dc-dc converters have as current and voltage) can be hazardous if not always played a crucial role in the certification of properly equipment. managed. medical That’s understandable since the power supplythe is guidelines responsible for major aspects In the 2nd edition, applied when the ofdevice power conversion, distribution, and protection. was within the "patient vicinity," defined as a

standard both of the completed The 3rd edition hardware andencompasses software design hardware and software ofsome the completed product, anddesign makes fundamental changes product,compared and makes some fundamental changes to the 2nd edition. compared to the 2nd edition.

the power supply is responsible for major aspects

6-foot radius from the patient. Within this envelope,

Physics 101three teaches us that power (seen both there were categories of increasing severity: asType current and voltage) can be hazardous if not "B" (body) equipment operates within the properly managed. vicinity, but without patient contact; Type "BF" (body

this and record it in the risk management file.

The 3rd edition standard encompasses both

In particular, interaction between the

In particular, interaction between the manufacturer manufacturer and the test lab is much greater. and the test lab is much greater. The medical device The medical device manufacturer uses an ISOmanufacturer uses an ISO-14971 risk analysis and 14971process risk analysis and management to define 1 ofmanagement 4 possible MOP process floating) equipment makes physical contact with to define 1 of 4 possible MOP classifications. ISO-14971 also specifi es a process Inthe thepatient; 2nd edition, the guidelines applied when the classifications. and Type "CF" (cardiac floating) makes ISO-14971 also specifies a process to identify hazards associated with medical devices; device was within the defined as ato identify physical contact with the“patient heart. Thevicinity,” classification hazards associated with medical devices; used to evaluate associated risks, control these 6-foot radiuswhat fromtype theofpatient. Within this envelope, used to evaluate determined levels of isolation, associated risks, control these risks, and monitor the effectiveness of the controls. there were creepage, three categories increasing severity: risks, and insulation, clearance,of and leakage would monitor the effectiveness of the controls. Type “B” (body) equipment operates within the be mandated or allowed.

vicinity, but without patient contact; Type “BF” (body the shIft to 3rd edItIon floating) equipment makes physical contact with rd The 3 edition changes perspective, the patient; and Type this “CF” (cardiac by floating) makes requiring that the overall means of protection (MOP) physical contact with the heart. The classification be some combination of one or more means of FIGURE 2:The The testing procedure has been has madebeen significantly testing procedure made determined what type of levels of isolation, more complex with far greater levels of external review from operator protection (MOOP) and means of patient significantly more complex with far greater insulation, creepage, clearance, and leakage the test lab. protection (MOPP). levels of external review from the test lab. would be mandated or allowed.

N

TEST LAB

DESIGN REVIEW RESULTS ACCEPTABLE?

N Y

TEST PLAN DISCUSSED AND FORMULATED

TESTING TO 60601 SERIES ACCEPTABLE?

TESTING AND REPORTS FOR IEC 6601 SERIES

Y

MANUFACTURER

RISK ANALYSIS FORMULATION AND DEVICE DESIGN

*

ADJUSTMENTS TO RISK ANALYSIS AND DEVICE DESIGN

* Typically the tests of greatest impact are abnormal

RESIDUAL RISK ACCEPTABLE?

Y

RISK MANAGEMENT FILE

N

operation, fault conditions, and essential performance.

page 3

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Power Developer Key Changes to IEC 60601-1 1. “Basic Safety” is now expanded to “Essential Performance.” This is the performance required to avoid unacceptable risk despite the absence of, or degradation of, a function or feature. What determines “acceptable risk” is left to the manufacturer and its documentation and analysis. Therefore, it is critical to a. establish a risk management process; b. establish acceptable levels of risk; and c. demonstrate that the remaining risk is acceptable. 2. The design process is addressed in more depth, especially for software design, since traditional hardware “failure” is not a meaningful concept (yes, software has problems, but it doesn’t fail). 3. The standard is now organized to place greater emphasis on verification and validation of the design. In short, the revised standard places major emphasis on risk assessment and management. It achieves this by focusing on the development process as much as, or even more than, the final product itself. The Risk Management Process (called out by 60601 and described in ISO 14971) includes a risk management file where identifiable fault conditions are identified and assessed.

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GLOBAL IEC 60601-1 3RD EDITION ADOPTION European Union The revised 3rd edition standard was adopted first by the European Union, with the member states passing legislation in 2006. As of the June 1, 2012, the second edition has been “withdrawn” and all new and existing products need to be certified to this new edition, known in Europe as EN60601-1:2006.

North America The timing and applicability of ANSI/AAMI ES60601- 1:2005, which is the harmonized version of IEC 60601-1 3rd edition in the US, is different than the 3rd edition standard in the EU. Originally set to go into effect July 1, 2013, the FDA announced an extension to give US medical device designers a slight reprieve, setting the updated transition date to December 31st, 2013. The US standard also differs from the EU version in that only products that come to market after the transition date need meet the updated edition, existing products do not. Canada’s CAN/CSA C22.2 No. 601.1 3rd edition standard was initially released with an effective date of June 2012, but as in the US, it was delayed, with an updated transition date of April 2013. The Canadian standard also applies only to new products launched after the effective date.


TECH ARTICLES IEC 60601 Medical Design Standards - 3rd Edition

FIGURE 3: To date only the US, Canada and the EU has adopted IEC 60601-1 3rd edition standards.

To date only the US, Canada and the EU has adopted IEC 60601-1 3rd edition standards.

effeCts of Rest of the World rd edItIon IeC 60601-1 3 Some of the requirements of the 2nd edition are

in potential conflict managIng rIsK with the 3rd. Thus, complying withthe latest edition may put a product out

Risk management, now a vital part of the standard, of compliance with 60601-1 2nd edition, and issoamake multifaceted, multistep process.in It regions begins with a product unmarketable risk which composed of risk thatassessment, still adhere to the itself earlierisversion. Countries still mandating 2ndofedition Japan, analysis (identifithe cation hazardsinclude and estimation Australia, New Zealand andand China. of th e effect of each hazard) then proceeds to risk evaluation (deciding if risk control is needed, The 3rd edition of IEC 60601-1 has not yet been recording in and the Risk Management File). adopted results in China no clear timetable exists. Standard techniques such as fault-tree The Chinese GB 9706.1-2007 standard analysis is however an among endorsement of the 2nd IEC 60601-1. are those used, but theedition assessment is not It is, therefore, generally not possible to obtain limited to that approach. successful registration in China with products developed and documented solely to the After the assessment phase, the risk management 3rd edition.

process moves on to risk control. Here, options for managing risk are evaluated, any risk-control As a result,the many vendors are working to meet both versions in the same design, requires measures are implemented, and thewhich residual risk additional effort. is assessed (some risks cannot be eliminated by design changes). There is also risk/benefit analysis, as well as examination of the critical issue of any new risks that may result from the risk-control steps themselves.

The process concludes with an overall evaluation of the totalOF original versus 3RD the remaining EFFECTS IEC risk 60601-1 EDITIONrisk, determination if this is acceptable, and a formal Managing Risk report. risk-management Risk management, now a vital part of the

softWare standard, is a multifaceted, multistep process.

It beginsinwith assessment, which itself is ect Changes therisk 3rd edition IEC 60601-1 will aff composed of risk analysis (identification of hazards the software too. As with any code-driven circuit, it and estimation of the effect of each hazard) will need toproceeds be validated for its basic design qualityif and then to risk evaluation (deciding and thoroughness as well as its response to the Risk risk control is needed, recording results in the Management File). Standard unexpected or unlikely events. techniques such as fault-tree analysis are among those used, but the

effeCt of isIeC assessment not60601-1 limited to that approach. 3rd edItIon on poWer supplIes

the assessment phase, theIEC risk60601-1 management InAfter practice, the transition from process moves on to risk control. Here, options for nd to 3rd editions does not change the basic 2managing the risk are evaluated, any risk-control requirements a power supply. measures areon implemented, andThe the primary residual risk is diff erences between the editions concern more assessed (some risks cannot be eliminated by design changes). There isofalso analysis, asto well as the classification therisk/benefit medical device than examination of the critical issue of any new risks that changes in power system design. may result from the risk-control steps themselves.

means of proteCtIon – moop and mopp The process concludes with an overall evaluation The standard requiresrisk a device two isolation of the total original versus have the remaining risk, barriers as means of protection (MOP)and where the determination if this is acceptable, a formal risk-management report. device may come into contact with a patient.

page 5

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Power Developer Software Changes in the 3rd edition IEC 60601-1 will affect the software too. As with any code-driven circuit, it will need to be validated for its basic design quality and thoroughness as well as its response to the unexpected or unlikely events.

Effect of IEC 60601-1 3rd Edition on Power Supplies

Therefore, there are means of operator protection (MOOP) and means of patient protection (MOPP), with different requirements for insulation, spacing, and isolation. Of course, it may be arguable if a particular circuitry function falls under MOOP or MOPP categories; the manufacturer needs to assess this and record it in the risk management file.

Level of Protection

The changes in power supply classification from 2nd edition to 3rd edition deal with definition not In practice, the transition from IEC 60601-1 performance. For Type B applications, a non2nd to 3rd editions does not change the basic medical- rated supply will be satisfactory, as long requirements on a power supply. The primary as it has reduced leakage currents below 500 μA; differences between the editions concern more this is true for “one MOPP” classification Type BF the classification of the medical device than to applications will be satisfied by a supply that is changes in power system design. rated to IEC 60601-1, which will continue to satisfy “two MOOP” and “one MOPP” classifications. Means of Protection – MOOP and MOPP Type CF requires an IEC 60601-1 qualified supply, plus an additional isolation barrier between the The standard requires a device have two isolation supply and the applied part that touches the barriers as means of protection (MOP) where the patient. Typically, this mandate is met with an device may come into contact with a patient. isolation transformer or a dc-dc converter with 8 rd mm creepage and double insulation; this is true IEC 60601 Medical Design Standards 3 Edition These can be a combination of basic safety for the “two MOPP” classification. See below for a insulation, use of protective earth ground, and summary of these requirements. isolation barriers that present a high-impedance path between input and output. In general, aThese supplycan that incorporates MOOP is less beonly a combination of basic safety expensive than one that also includes MOPP. insulation, use of protective earth ground, and However, demonstrating that the product and isolation barriers that present a high-impedance supply does not need MOPP is difficult, and path between input and output. In general, a supply adding it later is costly.

that only incorporates MOOP is less expensive thanthe one2nd thatand also3rd includes MOPP. However, Both revisions require two mechanisms for guarding each in the event of not demonstrating that the product and supply does aneed failure. For the area of basic electrical safety MOPP is difficult, and adding it later is costly. and avoiding shock hazard, the 3rd edition further divides means of protection Both the 2nd and 3rd revisions requireinto two operator protection and patient protection. This is because mechanisms for guarding each in the event of a the potential hazards seen by each can be quite failure. For area ofhas basic electrical and different; anthe operator access to asafety control rd avoiding hazard, thethe 3 patient edition further divides panel, for shock example, while may be “connected” via probes. means of protection into operator protection and

patient protection. This is because the potential hazards seen by each can be quite different; an operator has access to a control panel, for example, while the patient may be "connected" via probes.

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Therefore, there are means of operator protection (MOOP) and means of patient protection (MOPP), with different requirements for insulation, spacing, and isolation. Of course, it may be arguable if a particular circuitry function falls under MOOP or MOPP categories; the manufacturer needs to assess this and record it in the risk management file.

2nd edItIon requIrements by ClassIfICatIon Classifications

Isolation

Creepage

Insulation

type b

1500 vac

2.5 mm

basic

type bf

3000 vac

5 mm

double

type Cf

4000 vac

8 mm

double

3rd edItIon requIrements by ClassIfICatIon Classifications

Isolation

Creepage

Insulation

one moop

1500 vac

2.5 mm

basic

two moop

3000 vac

5 mm

double

one mopp

1500 vac

4 mm

basic

two mopp

4000 vac

8 mm

double

FIGURE 4: IEC 60601-1 3rd edition requires differing levels of

IEC 60601-1 3rd edition requires differing levels of isolation, insulation, creepage, and leakage depending on the isolation, insulation, creepage, and leakage MOP level. When comparing the requirements to those of the depending on theit becomes MOP level. 2nd edition standard, clearWhen that thecomparing difference is inthe requirements to those of the 2nd edition standard, definition, not performance. it becomes clear that the difference is in definition, performance. In general, not a supply that only incorporates MOOP is

less expensive than one that also includes MOPP. However, demonstrating that the product and supply does not need MOPP is difficult, and adding it later is costly, so it is best to initially go with a supply that meets both criteria.


TECH ARTICLES In general, a supply that only incorporates MOOP is less expensive than one that also includes MOPP. However, demonstrating that the product and supply does not need MOPP is difficult, and adding it later is costly, so it is best to initially go with a supply that meets both criteria. Future Effects of MOOP and MOPP Historically, medical power supplies have been completely analog (hardware circuitry only) with no software at all. While digital power supplies haven’t achieved mass scale adoption outside the server and telecoms industry, this will eventually change, especially since one MOOP applications can already use non-medical power components, such as CUI’s Novum suite of digital dc-dc modules. When the shift eventually happens for two MOOP and two MOPP products, designers will need to undergo static testing (including basic code walkthroughs, code inspections, algorithm analysis); dynamic testing (for data synchronization, task synchronization, and run-time issues etc); and finally formal testing (an academic-like approach using tools such as topology and set theory, to show that all requirements have been met, that the system will be stable, and that algorithms are built correctly and completely).

SUMMARY The IEC 60601-1 standard is complex, and the 3rd edition is far more complicated, convoluted, and confusing than its predecessor. There are related and intertwined standards in addition to IEC 60601, including formal collateral standards, which are directly related “family” members. There are some standards for guidance alone, and some you need to both follow and be formally certified as meeting and complying. There are many areas of conflict, confusion, ambiguity, and “subject to interpretation.” The conflicting elements of the 2nd and 3rd edition standards, coupled with its slow and (to date) incomplete rollout, further complicate matters. Simply shipping a me dical device with basic documentation to a certification lab is no longer adequate. Comprehensive, carefully structured documentation is needed for the design analysis, the design process, and the design rationale with explanations for why certain elements were or were not included or undertaken. In order to help ease the compliance process for medical device designers, CUI offers a comprehensive line of medical power supplies ranging from 15~400 W that have been certified to IEC 60601 2nd edition and 3rd edition two MOPP standards.

The CUI medical power supply family (15~400 W)is certified for IEC 60601-1 2nd edition and 3rd edition two MOPP standards.

http://www.cui.com/medical

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Power Developer

POWERING

THE SMART DEVICES

OF THE FUTURE

Interview with Necip Sayiner - CEO of Intersil Intersil is an industry-leading power management and IC solutions provider. With analysts predicting the mobile industry in the $40 billion range by 2016, Intersil decided to hone in on how it can serve that market best. The result has been a slew of power saving and sustainable products that will enable the kinds of powerful and efficient mobile devices of the future. We spoke with Necip Sayiner, CEO of Intersil, about Intersil’s core competencies as a company, and how they are tailoring their products to serve the ever changing demands of the industry.

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COVER INTERVIEW

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Power Developer Intersil is making a lot of different products but can you tell us about the core products that Intersil is focused on right now? Intersil has recently implemented several strategic changes. When I joined the company one year ago as president and CEO, I decided to focus our efforts on our core capabilities. When you look at Intersil’s core competencies, the first and foremost is power management. It is a technology that has been honed by the company for almost a decade now. A large majority of our investments now are focused on our power management products for the mobile markets, such as ultrabooks, tablets and smartphones. We also target industrial and infrastructure power management applications, including data centers and telecom infrastructure. Furthermore, we are capitalizing on our strong market position in automotive and aerospace to bring additional power products to solve the demanding challenges in those applications and expand our share.

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With Intersil’s focus on its core competencies, what type of feedback do you get from your customers and how much of that feedback is brought into product development?

How are you coming up with the strategy for designing new products?

When I joined the company, I wanted to hear firsthand what our customers thought about our products, so I went to visit them. I didn’t really know what I was going to hear and I was pleasantly surprised. Intersil’s technology was appreciated and well respected. Not only did our customers want to continue using our products, they wanted us to do more for them.

We make sure that sustainability is at the forefront of our designs, which ultimately ends up differentiating our technology from the rest. At Intersil, there is a strong drive for developing products that leverage our core capability and can create a sustainable competitive advantage. A good product investment strategy is not about rushing to market with products that will last only a generation or two; we are interested in technology and products that offer unique value in the application and will allow us to maintain our competitive advantage for a long period of time. This requires a great deal of discipline when determining how to allocate our R&D resources. I have experience developing that discipline in prior roles, and we are already seeing the impact of these changes on the quality of our pipeline.

In the past, the company did not always carefully listen to our customers’ inputs and at times, the distraction of trying to do too many things outside of our core expertise resulted in missing their critical design windows. But these are aspects that can easily be improved upon and are already being addressed. The key takeaway here is that our technology is valued by the most successful and demanding customers in the industry, and they want us to create more products based on that technology. As we’ve restructured and reorganized, our sales teams have received another round of positive feedback from our customers demonstrating we are on the right track. I’m excited about the direction we are moving in because we have the ability to make a big difference helping customers achieve their design goals.


COVER INTERVIEW The power industry is a big competitive space. How does Intersil differentiate itself from other competitors? I would say that we have three major strategic advantages. One would be in the mobile industry. Our mobile devices are serving a range of mobile products from ultrabooks to smartphones to enable longer battery life. We are applying decades of learning to solve one of the most pressing design challenges in these portable devices. As form factors continue to get smaller and functionality increases, the need for battery efficiency only increases, putting this market right in the cross hairs of our core capability. In terms of the industrial and infrastructure markets, our focus is delivering power efficiency and improved power density. Everyone is aware of the explosion of data centers. Customers building and maintaining these large compute farms point to power as their number one challenge. Better power efficiency reduces the cost of running the datacenter and better power density enables more computational power in a smaller footprint, further reducing cost. Intersil is one of very few companies with the digital power management capability to fundamentally improve the power architecture in these systems. Thirdly, we have presence in key end markets such as automotive and aerospace where we have strong brand recognition with market leading products. These tend to be markets characterized by very demanding requirements. Here, too, we can take our core technology, ruggedize it and enable customers to achieve the meaningful incremental improvements needed in these long life cycle products. As far as the overall market is concerned, what do you see as the biggest opportunity for growth in power management?

Power management is already a greater than $10 billion market. We’ve talked about some of the largest opportunities, mobile devices and the build out of wired and wireless infrastructure. We expect to capitalize on the expansion of smart devices both in the home and in the factory creating applications we could not have conceptualized a couple of years ago. The idea of the Internet of Things is beginning to take shape, and the need for low power end points with years of battery life in a small footprint means there will continue to be many new opportunities for Intersil. We also see the electrification of the car as a major growth area over time. The need in hybrid and electric vehicles for battery management and the pervasiveness of electronics in general, both inside the cabin and under the hood, are creating a host of new opportunities to apply leading edge power management capabilities.

“Our technology is valued by the most successful and demanding customers in the industry, and they want us to create more products based on that technology.�

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Power Developer “The idea of the Internet of Things is beginning to take shape, and the need for low-power end points with years of battery life in a small footprint means there will continue to be many new opportunities for Intersil.� What are the current challenges that Intersil has been facing to keep up with the rising demand in the industry? From a technology standpoint, there is much more innovation ahead of us. Every now and then, pundits suggest that good technology is running out of gas or that the industry has reached the fundamental limit of technology. I don’t think we are in any way near the end of innovation. We continue to fuel new ideas and new methodologies, new applications and ultimately new products that indicate the best is yet to come. If you look at things from a business perspective, the rate of growth has slowed for all of us in this industry compared to a decade ago. In some end markets, there are too many R&D dollars spent on chasing small opportunities. A healthy amount of consolidation needs to take place, and the companies that will remain will have the IP and the scale to drive their businesses forward.

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What is the culture like right now in Intersil? Intersil is a company that values engineering and innovation. Intersil has a highly collaborative environment, which is something I value very much. We also try to articulate the core values that we have in the company that will take us to the next 15 to 20 years. Combining the existing ideals of the company with what I believe every successful company requires, we have arrived at 5 core values: commitment, open communication, high-caliber talent, the will to win and commercial success. I am pleased to say that everyone in the company embraces these values. What excites you the most about the future of Intersil? Intersil is a financially healthy company with a purpose and focus. We have a very strong IP portfolio and technology assets, and we are also targeting a $10 billion opportunity in power management. Major industry trends are converging to our areas of strength in power management. There is a lot that the company can take advantage of to become even more strategic to customers and accelerate our growth. We are doing everything we can to deliver on our goal of flawless execution in the direction that we have established.


Intersil offers a comprehensive set of efficient and highly-integrated digital and analog controllers, power modules and switching regulators that simplify power design for a wide variety of

P WERING INDUSTRIAL

industrial applications. ISL8541X: Intersil’s new family of pin-compatible, 3V to 36V synchronous buck regulators simplifies design, improves efficiency and reduces BOM cost. Now with three output current options to choose from, reusing proven circuit or board designs has never been easier. • Output current options: 500mA, 800mA or 1A • Adjustable output voltage range from 0.6V to 95% of VIN • Selectable PFM or forced PWM for superior light load efficiency Go to intersil.com/isl8541x Download Datasheet Read App Note Order Demo Board Watch Video

See Intersil’s leadership power technologies at intersil.com/industrial Power Modules Digital Power Integrated FET Regulators Switching Regulators FPGA Power Hot Plug Voltage Monitors Power Sequencers

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Power Developer

Perfection in P

How to achieve Full Pow

Linear regulators, although widely used, do have a major disadvantage; inefficient. Once the input voltage rises above the drop-out threshold regulator efficiency will continue to drop. Linear regulators waste electric as heat. The losses are related to the current and the voltage dropped a regulator. The larger the voltage drop, the greater the heat generated. This to be managed, usually by costly heatsinking. Switching regulators are reno their efficiency, with well-designed types achieving up to 97% conversion e With high efficiency comes lower losses and less heat generation, whic allows ambient operation to 85째C. Switching regulators save energy, space a

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TECH COLUMN

Power

wer without Cooling

; they are d a linear cal energy across the s heat has owned for efficiency. ch in-turn and costs.

Paul Cheesman

Business Development Manager

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Power Developer

Advantages of efficient switching regulators Linear regulators are often preferred due to their low price, a strong argument at high volumes. But is it a good argument—particularly longer term? Whether a linear regulator is cost effective is not a question of just the component cost, but rather of the energy consumption during the lifetime of operation. As soon as the input voltage widens, the efficiency starts to decline. Low efficiency translates into higher energy losses. Regulating down a voltage of 32V to 5V at 1A generates losses of 27W in a linear regulator. In the case of the Recom switching regulator type R-78C this value is reduced to 0.7W. Operating the unit daily for eight hours during 10 years accrues additional energy costs of round about £165, based on 22.85p kW h, nearly 35 times more than the original buying price of a switching regulator. As consumers become more energy conscious the use of linear regulators is less attractive.

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Fig. 1

However there are more weighty arguments. Energy loss always translates into unwanted heat, which requires additional cooling. Heatsinks cost money, plus indirect costs such as mechanical hand assembly need to be considered. Heat sinks require precious space and add weight. This demonstrates that the extra purchase price for the new R-78C from Recom represents a cost effective solution for the equipment manufacturer, and the end user.


TECH COLUMN Stable high efficiency with varying load The advantage of switching regulators becomes all the more evident the greater the input voltage exceeds the output voltage. Switching regulators also show an optimal efficiency with a difference of only a few volts, but the difference is not substantial. The Recom 15V/1A regulator R-78C15-1.0 has an efficiency of 94% at 42V input and 96% at 18V input, which is just a 2% difference, no comparison to the linear regulator which remains well below 50%.

Energy loss always translates into unwanted heat, which requires additional cooling.

The new RECOM R-78C switching regulator also compares very favorably with other brands. Comparison tests with competitive 5V/1A switching regulators at 32V input and varying load put the R-78C (fig. 2, blue curve) ahead with an efficiency 5-10% better (fig. 2, yellow curve). This may not seem significant, but the effect on losses, particularely in the medium load sector, is substantial with the R-78C generating approx. 40% less losses (fig. 2, red line below). The efficiency is relative constant across the most common operating load spectrum. Even with only 20% load the value exceeds 80%. Fig. 2: With 32V input and 5V output the new R-78C reaches 88% efficiency 10 points higher, with 40% reduced losses.

Whether a linear regulator is cost effective is not a question of just the component cost, but rather of the energy consumption during the lifetime of operation.

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Power Developer Low Voltage AC input, regulated DC output

Fig. 3: The new R-78C switching regulator can be operated with input voltages of up to 42V and can therefore be used in applications with unstable 24VAC.

24V AC-voltage converted into a stable DC voltage Switching regulators commonly available can operate with input voltages up to 34V, optimistically up to 36V. In theory it should be possible to rectify a 24VAC voltage and supply the converter, since the following equation applies:

In practice however we normally deal with an unregulated voltage. If the AC voltage at the rectifier varies by only +/-10% this requires an input voltage range of up to >37VDC. This requirement could not so far be met by any switching regulator. If the AC voltage varies by +/- 20%, input voltages up to 41VDC are required. This was one reason why Recom design engineers increased the input range of the new R-78C family to 42VDC.

24VAC*√2 = 33.9VDC

Perfection in Power

Tackling Problems with Innovative Concepts LEDs are now widely used in many different areas. They allow for lighting solutions that were simply not possible with conventional lighting equipment. This means, however, that LED drivers need to meet ever more complex, application-specific demands.

Thomas Rechlin Senior FAE for Europe at RECOM Engineering Gmunden, Austria

In many cases, two-stage drivers are the best solution. By separating the AC power supply from the DC LED power, they offer new possibilities that are simply not achievable with conventional LED drivers.

To read the previous installment, click on the image above.

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Due to their low noise design, R-78C switching regulators can be used in applications demanding very low noise levels.


TECH ARTICLES Noise levels lower than expected Switching regulators are commonly assumed to be electrically noisy, and are often shunned in critical applications. The new Recom R-78C switching regulators shows that this is no longer the case. Noise levels are between 20 and 40mVpp, depending on the model, and therefore are better by a factor 2 than the best competitive product. This was achieved by careful design, reducing noise peaks with an internal filter and by operating at a very high switching frequency of more than 400kHz. The R-78C switching regulators do not require additional external filters in most applications. By simply applying an external 40kHz low-pass filter, noise peaks can be further reduced down to 5mVpp. Due to their low noise design, R-78C switching regulators can be used in applications demanding very low noise levels.

High power density— no isolation Measuring 11.6x8.6x10.4mm (H x W x D) all R-78C switching regulators are very compact and the power density is close to 15W/cm3. All converters are short circuit and overload protected. They operate in hiccup-mode until the fault is eliminated. The ambient temperature is specified between -40°C and +85°C, whereby derating has to be observed at the upper limit. The thermal overload protection switches the converter off, until a pre-set temperature limit has been reached. Switching regulators have been designed to replace linear regulators and are therefore not isolated. If isolation is required, we recommend considering the wide selection of isolated DC/DC converters from RECOM.

Fig.4: The ripple of the R-78C is significantly lower than of competitive products, thus eliminating the issue of “external filters”. Recom designs and develops its products to achieve maximum life expectancy and assures this by step by step testing in its own environmental laboratory in Gmunden/Austria. R-78C-switching regulators are EN-60950-1 certified and RoHS 6/6 compatible. The MTBF calculated to MIL-HDBK 217F at 25°C is 13.3 million hours. Warranty extends to 3 years.

Conclusion High efficiency, low noise, high power density of 15 watts/cm3 and an input of up to 42V puts this new product at an advantage to standard linear regulators, thus increasing the trend toward “energy saving converters”. Introducing the new R-78C generation by Recom, the inventor of the R-78 switching regulator, is miles ahead of competition and makes it hard for “copy shops”, to match.

To read the previous installment, click the image above.

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