Page 1


INTRODUCTION FROM THE IEEE 67TH ECTC PROGRAM CHAIR MARK POLIKS The 67th Electronic Components and Technology Conference (ECTC) Walt Disney World Swan & Dolphin Resort, Lake Buena Vista, Florida, USA • May 30 - June 2, 2017 On behalf of the Program and Executive Committees, it is my pleasure to invite you to IEEE’s 67th Electronic Components and Technology Conference (ECTC), which will be held at the Walt Disney World Swan & Dolphin Resort, Lake Buena Vista, Florida, from May 30 to June 2, 2017. All ECTC meetings will be taking place in the Walt Disney World Dolphin Resort building. This premier international annual conference, sponsored by the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society, brings together key stakeholders of the global microelectronic packaging industry, such as semiconductor companies, foundry and OSAT service providers, equipment manufacturers, material suppliers, research institutions and universities, all under one roof. More than 1,400 people attended the 66th ECTC in Las Vegas, Nevada, in May 2016. At the 67th ECTC, more than 360 technical papers are scheduled to be presented in 36 oral sessions and five interactive presentation sessions, including one interactive presentation session exclusively featuring papers by student authors. The oral sessions will feature selected papers on key topics such as flip chip packaging, 3D/TSV technologies, wafer level packaging, design for RF performance and signal/power integrity, thermal and mechanical modeling, optoelectronics packaging, materials and reliability. Interactive presentation sessions will showcase papers in a format that encourages more in-depth discussion and interaction with authors about their work. Authors from 22 countries are expected to present their work at the 67th ECTC, covering ongoing technological challenges with established disciplines or emerging topics of interest for our industry, such as additive manufacturing, heterogeneous integration, and flexible and wearable electronics. ECTC will also feature panel and special sessions with industry experts covering a number of important and emerging topic areas. On Tuesday, May 30 at 10 a.m., Vikas Gupta and Pradeep Lall will chair a session on “Material and Package Reliability Needs/Challenges for Harsh Environments.” That same day at 2 p.m., Bing Dang will chair a panel session on “Flexible Hybrid Electronics – Electronics Outside the Box,” where a panel of experts will discuss how innovation in device integration and packaging will bring together thinned silicon die with printed components to deliver electronics that conform to the shape of the human body and vehicles. Tuesday evening will also include the ECTC Panel Session at 7:30 p.m. on “Panel Fan-Out Manufacturing: Why, When, and How?” chaired by CPMT President Jean Trewhella and Young Gon Kim. Continuing to build on the success of the first-ever CPMT Women’s Panel and Reception held at the 65th ECTC, this year’s conference will also feature a panel discussion chaired by Kitty Pearsall on Wednesday, May 31, at 6:30 p.m. on “Emotional Intelligence (EI) – Link to Successful Leadership,” with participation from distinguished women leaders and technologists in our industry. All conference attendees are invited. Also on Wednesday at 7:30 p.m., Luke England will chair the ECTC Plenary Session titled “Packaging for Autonomous Vehicle Electronics,” featuring key technologists sharing their views on 2

the evolutionary requirements for packaging and reliability challenges to support widespread implementation of driver-less vehicles on the road. On Thursday, June 1 at 8 p.m., the CPMT Seminar titled “3D Printing Tools, Technologies and Applications,” will be moderated by Venkatesh Sundaram and Yasumitsu Orii from the High-Density Substrates & Boards Technical Committee of the CPMT Society. Supplementing the technical program, ECTC also offers several Professional Development Courses (PDCs) and Technology Corner exhibits. Co-located with the IEEE ITherm Conference this year, the 67th ECTC will offer 18 PDCs, organized by the PDC Committee chaired by Kitty Pearsall. The PDCs will take place on Tuesday, May 30th and are taught by distinguished experts in their respective fields. The Technology Corner will showcase the latest technologies and products offered by leading companies in the electronic components, materials, packaging and services fields. More than 100 Technology Corner exhibits will be open Wednesday and Thursday starting at 9 a.m. ECTC also offers attendees numerous opportunities for networking and discussion with colleagues during coffee breaks, daily luncheons, and nightly receptions. Whether you are an engineer, a manager, a student, or an executive, ECTC offers something unique for everyone in the microelectronics packaging and components industry. I invite you to make your plans now to join us for the 67th ECTC and be a part of all the exciting technical and professional opportunities. I also take this opportunity to thank our sponsors, exhibitors, authors, speakers, PDC instructors, session chairs, and program committee members, as well as all the volunteers who help make the 67th ECTC a success. I look forward to meeting you in Lake Buena Vista, Florida, from May 30 to June 2, 2017. Mark D. Poliks 67th ECTC Program Chair Binghamton University Phone: +1-607-777-5361 Email: mpoliks@binghamton.edu

Index

ECTC Registration ................................................................. 3, 31, 32 General Information .............................................................................3 Hotel Information ..........................................................................3, 31 2017 ECTC Special Session ................................................................4 2017 Technical Subcommittee Special Session ................................4 2017 ECTC Panel Session....................................................................4 2017 ECTC Plenary Session ...............................................................4 2017 CPMT Seminar.............................................................................5 ECTC Luncheon Keynote Speaker.....................................................5 Luncheons and Receptions .................................................................5 2017 CPMT Women’s Panel and Reception....................................5 Executive and Program Committees .............................................6-7 Professional Development Courses ............................................9-14 Area Attractions ................................................................................ 14 Program Sessions ..........................................................................15-30 2017 Technology Corner Exhibits .................................................. 31 Conference Overview ...................................................................... 35


67th ECTC ADVANCE REGISTRATION Advance Registration Online registration is available at www.ectc.net. For more information on registration rates, terms, and conditions see page 32. Register early … save US$100 or more! All applications received after May 4, 2017 will be considered Door Registrations. Those who register in advance can pick up their registration packets at the ECTC Registration Desk in the Dolphin Convention Center on the Lobby Level in front of Australia 3. Please note that the Swan and Dolphin are two separate buildings, and all ECTC meetings will be taking place in the Walt Disney World Dolphin Resort. On-Site Registration Schedule Registration will be held in the Dolphin Convention Center on the Lobby Level in front of Australia 3. Monday, May 29, 2017 3:00 p.m. to 5:00 p.m. Tuesday, May 30, 2017 6:45 a.m. to 5:00 p.m.*

*6:45 a.m. to 8:00 a.m. ( Morning PDCs & morning ECTC Special Session Only)

Wednesday, May 31, 2017 Thursday, June 1, 2017 Friday, June 2, 2017

6:45 a.m. to 4:00 p.m. 7:30 a.m. to 4:00 p.m. 7:30 a.m. to 12:00 noon

The above schedule for Tuesday will be rigorously enforced to prevent students from being late for their courses.

General Information Conference organizers reserve the right to cancel or change the program without prior notice. Please note that the Walt Disney World Swan and Dolphin Resort are two separate buildings, and ALL ECTC meetings will be taking place in the Walt Disney World Dolphin Resort. While booking your hotel reservation please make sure to specify that you require to be placed in the Walt Disney World DOLPHIN Resort. While these two buildings are located adjacent to each other and share many of the same social / resort function areas, we want to ensure you have a most convenient experience while at ECTC 2017. ITherm 2017 This year ITherm is co-located with ECTC! All ITherm sessions will take place in the SWAN building of the Walt Disney World Swan and Dolphin Resort. ALL ECTC sessions, and the co-location of exhibits, will take place in the DOLPHIN building! Loss Due to Theft Conference management is not responsible for loss or theft of personal belongings. Security for each individual’s belongings is the individual’s responsibility. ECTC Sponsors With 66 years of history and experience behind us, ECTC is recognized as the premier semiconductor packaging conference and offers an unparalleled opportunity to build relationships with more than 1,000 individuals and organizations committed to driving innovation in semiconductor packaging.

We have a limited number of sponsorship opportunities in a variety of packages to help get your message out to attendees. These include Gala, Program, and several other sponsorship options that can be customized to your company’s interest. If you would like to enhance your presence at ECTC and increase your impact with a sponsorship, please take a look at our sponsorship brochure on the website www.ectc.net under “Sponsors.” To sign up for sponsorship or to get more details, please contact Wolfgang Sauter at wolfgang.sauter@globalfoundries.com or +1-802922-3083. Hotel Accommodations Rooms for ECTC attendees have been reserved at the Walt Disney World Dolphin, of the Walt Disney World Swan and Dolphin Resort. The special conference rate is: $189.00 / Run of the House Please note these rooms are on a first come, first served basis. If this specific category is no longer available, attendees will be offered the next best available accommodation. These prices include single or double occupancy in one room. Please note that rooms offering two beds are limited and subject to availability and should be requested at the time of reservations. Room reservations must be made directly with the hotel by Friday, May 5, 2017, at 5pm ET to ensure our preferred conference rate. All reservations made after the cutoff date of Friday, May 5, 2017, at 5pm ET will be accepted on a space and rate available basis. If you need to cancel a reservation, please do so AT LEAST 5 DAYS prior to arrival for a full refund. Each attendee is subject to the terms and polices set by each hotel. Note about Hotel Rooms Attendees should note that only reputable sites should be used to book a hotel room for the 2017 ECTC. Be advised that you may receive emails about booking a hotel room for ECTC 2017 from 3rd party companies. These emails and sites are not to be trusted. The only formal communication ECTC will convey about hotel rooms will come in the form of ECTC e-blasts or ECTC emails from our Executive Committee. ECTC’s only authorized site for reserving a room is through our website (www.ectc.net). You may, however, use other trusted sites that you have personally used in the past to book travel. Please be advised, there are scam artists out there, and if it’s too good to be true, it likely is. Should you have any questions about booking a hotel room please contact ECTC staff at: lrenzi@renziandco.com Transportation Services Enjoy a complimentary water taxi from the resorts’ dock, running to and from Epcot® and Disney’s Hollywood Studios™. Complimentary shuttle buses also transport guests from the hotel entrance to Magic Kingdom® Park, Disney’s Animal Kingdom® Theme Park, Downtown Disney® area, and Disney’s Blizzard Beach Water Park and Disney’s Typhoon Lagoon Water Park. There is, unfortunately, no courtesy transportation between the hotel and the airport. 3


2017 Applied Reliability Special Session

2017 ECTC Panel Session

Material and Package Reliability Needs/Challenges for Harsh Environments

Panel Fan-Out Manufacturing: Why, When, and How?

Tuesday, May 30, 2017, 10:00 a.m. – 11:30 a.m.

Chairs: Jean Trewhella, CPMT President - GLOBALFOUNDRIES and Young Gon Kim - Integrated Device Technology Fan-out packaging has proven to be a versatile solution – cost-effective for low-end applications and high-performance for leading-edge products. They provide flexibility with design rules, number of RDL layers, component sourcing, and even passive component embedding. Hence, fan-out is now taking off and is projected to be the fastest growing packaging approach. It can be done in either a wafer or panel format. Wafer format fan-out packaging processing shares many features with conventional WLCSP. Thus, this infrastructure similarity enabled adoption of this technology with less market resistance than is typically seen with new manufacturing processes. However, panel format processing for fan-out packaging has been evolving with a different path. Large panels can process four wafers or more at one time, which provides significant cost benefits. Unfortunately, panel fan-out introduces multiple challenges, including significant capital investment, unique process issues, and industry standardization. We believe that the significant cost benefits provide motivation to migrate to panel format fan-out packaging. The remaining key question on panel fan-out might be ‘when’, which could be determined by the return on investment (ROI) driven by market demand. This panel session aims to look at various views from fan-out packaging experts: two from wafer format fan-out manufacturers, two doing extensive development on panel fan-out, and one focused on cost-effective solution search for product applications. We expect the discussion to help those who want to develop accurate fan-out packaging technology roadmaps. 1. Douglas Yu, TSMC 2. Tim Olson, DECA 3. Steffen Kroehnert, NANIUM 4. Rolf Aschenbrenner, IZM Fraunhofer 5. Steve Bezuk, Qualcomm Technologies, Inc.

Chairs: Vikas Gupta - Texas Instruments, Inc. and Pradeep Lall - Auburn University The session focuses on the material needs and packaging reliability for a number of extreme environment applications, including aerospace, automotive, downhole, oil & gas, and industrial environments. Consumer products generally reside in benign office environments and have relatively short design lifetimes in the neighborhood of one to two years. Electronics manufactured for extreme environment applications often have longer design life from 25-30 years, in addition to expectation of sustained operation at environment extremes. In this special session, perspectives will be shared by companies from each of the application spaces, in addition to the companies that make materials and components for usage in each of the application spaces. The focus will include the application needs and the material and packaging solution-paths to meeting the survivability and performance requirements. 1. Erick W. Seltmann, Boeing 2. Przemyslaw Jakub Gromala, Bosch 3. Steve Dunford, Schlumberger 4. Anton Z. Miric, Heraeus Deutschland GmbH & Co. KG 5. Emad A. Andarawis, General Electric 6. Varughese Mathew, NXP Semiconductors

2017 ECTC Special Session

2017 ECTC Plenary Session

Flexible Hybrid Electronics – Electronics Outside the Box

Packaging for Autonomous Vehicle Electronics

Tuesday, May 30, 2017, 2:00 p.m. – 3:30 p.m.

Wednesday, May 31, 2017, 7:30 p.m. – 9:00 p.m.

Chair: Bing Dang - IBM Corporation

Chair: Luke England - GLOBALFOUNDRIES The era of autonomous vehicles is nearly upon us. All major vehicle manufacturers currently have programs to develop and bring autonomous vehicles to market, with widespread rollout predicted in the early 2020s. Surrendering control of driving from humans to machines will drive a huge increase in on-board sensors to compensate. Vehicles will need to communicate with one another to allow for streamlined driving on the road. This, in turn, will require an exponential increase in computing power to process the immense amount of data from all of these sources. In addition, vehicle motors will continue to transition from gas to electric, requiring advances in high current electronics to deliver power from the battery to motor. This plenary session will feature key technologists from specific focus areas related to autonomous vehicle electronics. Starting with an industry roadmap and visions, the panel will share their views on the evolutionary requirements for packaging and reliability challenges to support widespread implementation of autonomous vehicles on the road. 1. Application and Market Projections – Venky Sundaram,Georgia Institute of Technology 2. Powertrain Electronics – Brent Richardson, Texas Instruments 3. Sensors – Frank Bertini, Velodyne 4. Data Processing – Dongji Xie, Nvidia 5. Wireless Communication – Raj Pendse, Qualcomm Technologies, Inc.

A rapidly maturing set of materials and manufacturing processes offers the opportunity for a new generation of electronics that leaves behind today’s bulky, rigid, and heavy packaging. Through innovations in device integration and packaging, Flexible Hybrid Electronics (FHE) will bring together thinned or unpackaged silicon die with printed components to deliver electronics that conform to the shape of the human body and vehicles. This panel discussion will address both potential applications in the military and commercial markets, as well as innovative materials and manufacturing solutions that will enable electronics that bend, flex, stretch, and fold. 1. Benjamin Leever, Air Force Research Laboratory, Materials & Manufacturing Directorate 2. James L. Zunino, U.S. Army RDECOM ARDEC 3. Robert Smith, Boeing Research & Technology 4. Girish Wable, Jabil 5. Dale Wilson, American Semiconductor

4

Tuesday, May 30, 2017, 7:30 p.m. – 9:00 p.m.

These sessions are open to all conference attendees.


ECTC Luncheon Keynote Speaker Advanced Packaging Opportunities and Challenges Wednesday, May 31, 2017, 12:00 Noon Presenter: Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development, Intel Corporation Industry reliance on advanced packaging has been accelerating over the last few years. This trend is expected to continue in the future. Heterogeneous integration of multiple chips in a package supports Moore’s Law scaling and is driving many challenges in package interconnect scaling, design environment, optical integration, electrical/thermal performance, and test. Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development at Intel Corporation, will address future challenges and opportunities for advanced multi-chip packaging. Since 2009, Babak has been responsible for Intel’s packaging, assembly process, packaging materials, enabling technology, and test technology development. Prior to leading Assembly and Test Technology Development, Babak led the Corporate Quality Network within Intel’s Technology and Manufacturing Group from 2002 to 2009. He also led a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction, and quality business practices. Previously, Babak managed technology development quality and reliability, and was responsible for silicon technology certification, assembly, test, and board processes. Babak joined Intel in 1984, the same year he received his Ph.D. in solid state electronics from The Ohio State University.

LUNCHEONS Tuesday PDC Luncheon All individuals attending a PDC course are invited to join us for lunch on Tuesday, May 30. Proctors and instructors are welcome, too! Wednesday Conference Luncheon Please be sure not to miss our Wednesday luncheon with guest speaker Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development, Intel Corporation. All conference attendees are welcome! Thursday CPMT Luncheon Our sponsor, the IEEE Components, Packaging and Manufacturing Technology Society, will be sponsoring lunch on Thursday for all conference attendees! Friday Program Chair Luncheon Please attend Friday’s lunch hosted by the 67th ECTC Program Chair. We will honor conference paper award recipients and raffle off a vast array of prizes including a hotel stay, free conference registrations, and many other attractive items!

2017 CPMT Women’s Panel and Reception Emotional Intelligence (EI) – Link to Successful Leadership Wednesday, May 31, 2017, 6:30 p.m. – 7:30 p.m. Chair: Kitty Pearsall - Boss Precision, Inc. CPMT Society President Jean Trewhella and 67th ECTC Senior Past General Chair Beth Keser cordially invite all ECTC attendees to attend our third Women’s Panel and Reception sponsored by CPMT. The three panelists will speak on their experiences and achievements in the microelectronics industry and provide insights into how Emotional Intelligence enabled them to be successful leaders. A Q&A session and reception for panelists and attendees will follow. 1. Joanne Martin, JLM Consulting, LLC and former Vice President, IBM Corporation 2. Rozalia Beica, Global Director New Business Development, The Dow Chemical Company 3. Tanja Braun, Deputy Group Manager, Fraunhofer Institute for Reliability and Microintegration IZM

2017 CPMT Seminar 3D Printing Tools, Technologies and Applications

General Chair’s Speakers Reception

Tuesday, May 30, 2017 – 6:00 p.m. – 7:00 p.m. (by invitation only)

ECTC Student Reception

Tuesday, May 30, 2017 • 5:00 p.m. - 6:00 p.m.

Students, have you ever wondered what career opportunities exist in the industry and how you could use your technical skills and innovative talent? If so, you are invited to attend the ECTC Student Reception, where you will have the opportunity to talk with industry professionals about what helped them be successful in their first job search and reach their current positions. Enjoy good food and network with industry leaders and achievers. Don’t miss the opportunity to interact with people that you might not have the chance to meet otherwise!

Exhibitor Reception

Wednesday, May 31, 2017 • 5:30 p.m. - 6:30 p.m.

67th ECTC Gala Reception

Thursday, June 1, 2017 • 6:30 p.m.

All badged attendees and their guests are invited to attend a reception hosted by our Gala Reception sponsors.

iNEMI Technical & Research Committee Meetings Tuesday, May 30, 2017 • 7:30 a.m. – 5:00 p.m. By Invitation Only

Thursday, June 1, 2017, 8:00 p.m. – 9:30 p.m. Chairs: Venky Sundaram - Georgia Institute of Technology and Yasumitsu Orii - Nagase, Japan Due to the trend towards a globalized, technical and connected society, there is a rising demand for a new breed of technologies enabling low-priced, flexible and newconcept products. Conventional technologies (including silicon based microelectronics) have reached their limits due to their high fabrication costs and environmental issues. Armed with new printing technologies (including screen, gravure, reverse gravure, flexo, offset, ink jet, etc.) and innovative materials, printed electronics has recently emerged as a promising environmentally friendly alternative route to produce electronic/display/energy products at a low cost and with new possibilities of such creative technologies as flexible electronics. 3D printing systems (forming 3D structure) have already become an indispensable tool in a wide variety of industrial fields. 3D printing has now started to impact electronic functions with so-called “functional 3D printing systems.” These systems can form electronic devices such as customized wearable devices or IoT sensor modules on-demand. The system is operated according to 3D CAD data, including electronic circuits and insulation layer position and electronic parts position and then produces a complete device without any assembly processes. However, there are still a lot of technical barriers to overcome for 3D printing to become a mainstream process for manufacturing devices, packages and systems. This seminar will highlight important recent developments in 3D printing tools, technologies and applications and conclude with a brief panel discussion. 1. Manos Tentzeris, Georgia Institute of Technology 2. Humair Mandavia, Zuken SOZO Center 3. Simon Fried, Nano Dimension Ltd. 4. Takeshi Sato, Fuji Machine Mfg. Co., Ltd.

5


2017 Executive Committee Chair Henning Braunisch Intel Corporation braunisch@ieee.org +1-480-552-0844

Vice-General Chair Sam Karikalan Broadcom Limited sam.karikalan@broadcom.com +1-949-926-7296 Program Chair Mark Poliks Binghamton University mpoliks@binghamton.edu +1-607-727-7104 Assistant Program Chair Christopher Bower X-Celeprint Inc. cbower@x-celeprint.com +1-919-522-3230 Jr. Past General Chair ECTC Alan Huffman Micross Advanced Interconnect Technology alan.huffman@micross.com +1-919-248-9216 Sr. Past General Chair ECTC Beth Keser Intel Corporation beth.keser@intel.com Sponsorship Chair Wolfgang Sauter GLOBALFOUNDRIES wolfgang.sauter@globalfoundries,.com +1-802-922-3083 Finance Chair Patrick Thompson Texas Instruments, Inc. patrick.thompson@ti.com +1-214-567-0660 Publications Chair Steve Bezuk Qualcomm Technologies, Inc. sbezuk@qti.qualcomm.com +1-858-218-5143

Advanced Packaging Chair Young-Gon Kim Integrated Device Technology, Inc. young.kim@idt.com +1-408-360-1545 Assistant Chair Luu Nguyen Texas Instruments Inc. luu.nguyen@ti.com +1-669-721-4786 Daniel Baldwin H.B. Fuller Company Bora Baloglu Amkor Technology Rozalia Beica Dow Electronic Materials Jianwei Dong Dow Electronic Materials Luke England GLOBALFOUNDRIES Allyson Hartzell Veryst Engineering Beth Keser Intel Corporation John Knickerbocker IBM Corporation Steffen Kroehnert Nanium S.A. John H. Lau ASM Pacific Technology Markus Leitgeb AT&S Mike Ma SPIL Dean Malta Micross Advanced Interconnect Technology Deborah S. Patterson Principal, Patterson Group

CPMT Representative C. P. Wong Georgia Institute of Technology cp.wong@mse.gatech.edu +1-404-894-8391

Andy Tseng JSR Micro

Keith Newman Hewlett Packard Enterprise

Jan Vardaman Techsearch International

Donna M. Noctor Alcatel-Lucent

Shaw Fong Wong Intel Corporation

S. B. Park Binghamton University

Jin Yang Intel Corporation

Lakshmi N. Ramanathan Microsoft Corporation

Tonglong Zhang Nantong Fujitsu Microelectronics Ltd.

Richard Rao MicroSemi

High-Speed, Wireless & Components Chair P. Markondeya Raj Georgia Institute of Technology raj@ece.gatech.edu +1-404-558-2615

René Rongen NXP Semiconductors Scott Savage Medtronic Microelectronics Center Jeffrey Suhling Auburn University Dongji Xie NVIDIA Corporation

Assistant Chair Kemal Aygun Intel Corporation kemal.aygun@intel.com +1-480-552-1740

Assembly & Manufacturing Technology Chair Wei Koh Pacrim Technology kohmail@gmail.com +1-714-417-9979

Amit P. Agrawal Keyssa Inc.

Assistant Chair Paul Tiner Texas Instruments p-tiner@ti.com +1-469-471-3565

Prem Chahal Michigan State University

Sai Ankireddi Maxim Integrated Products, Inc. Garry Cunningham NGC Mark Gerber Advanced Semiconductor Engineering Inc. USA

Wendem Beyene Rambus Inc. Eric Beyne IMEC

Zhaoqing Chen IBM Corporation Craig Gaw NXP Semiconductor Apostolos Georgiadis Centre Tecnologic de Telecomunicacions de Catalunya (CTTC) Abhilash Goyal Oracle

Rockwell Hsu Cisco Systems, Inc.

Li Jiang Texas Instruments

Lih-Tyng Hwang National Sun Yat-Sen University

Vijay Khanna IBM Corporation

Mahadevan K. Iyer Texas Instruments, Inc.

Chunho Kim Medtronic Corporation

Bruce Kim City University of New York

Yang Liu IBM Corporation

Timothy G. Lenihan TechSearch International

Cheng-Hsiang (Sean) Liu Siliconware Precision Industries Co. Ltd

Sebastian Liau ITRI

Debendra Mallik Intel Corporation

Lianjun Liu Freescale Semiconductor, Inc.

Assistant Chair Deepak Goyal Intel Corporation deepak.goyal@intel.com +1-480-554-5203

Li Ming ASM

Nanju Na Xilinx

Jae-Woong Nah IBM Corporation

Dan Oh Altera Corporation

Babak Arfaei Ford Motor Company

Valerie Oberson IBM Canada Ltee

Andrea Paganini GLOBALFOUNDRIES, Inc.

Sridhar Canumalla Microsoft Corporation

Tom Poulin Aerie Engineering

Luca Roselli University of Perugia

Tim Chaudhry Amkor Technology, Inc.

Shichun Qu Lumileds

Hideki Sasaki Renesas Electronics Corporation

Tz-Cheng Chiu National Cheng Kung University

Shawn Shi Medtronic Corporation

Li-Cheng Shen Quanta Research Institute

Darvin R. Edwards Edwards Enterprises

Tom Swirbel Motorola, Inc.

Manos M. Tentzeris Georgia Institute of Technology

Joseph W. Soucy Draper

Arrangements Chair Lisa Renzi Ragar Renzi & Company, Inc. lrenzi@renziandco.com +1-703-863-2223

Toni Mattila Aalto University

Sa Huang Medtronic Corporation

Treasurer Tom Reynolds T3 Group LLC t.reynolds@ieee.org +1-850-897-7323

Professional Development Course Chair Kitty Pearsall Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287

Sean Too Microsoft

Xiaoxiong (Kevin) Gu IBM Corporation

Raj Pendse Qualcomm Technologies, Inc.

Web Administrator Nancy Stoffel GE Global Research nstoffel1194@gmail.com +1-518-387-4529

Dongming He Qualcomm Technologies, Inc.

Paul Houston Engent

Publicity Chair Eric Perfecto GLOBALFOUNDRIES eric.perfecto@globalfoundries.com +1-845-894-4400

Exhibits Chair Joe Gisler Vector Associates gislerhj.ECTC@mediacombb.net +1-480-288-6660

6

2017 Program Committee

Subhash L. Shinde Notre Dame University

Kuo-Chung Yee TSMC Christophe Zinck Advanced Semiconductor Engineering, Inc. Applied Reliability Chair Vikas Gupta Texas Instruments, Inc. gvikas@ti.com +1-214-567-3160


Emerging Technologies Chair John Cunningham Consultant jeclaser@gmail.com

Kathy Cook Tessera

Diptarka Majumdar Superior Graphite

Fuad Doany IBM Corporation

David Danovitch University of Sherbrooke

Joon-Seok Oh Samsung Electro-Mechanics

Soon Jang ficonTEC USA

Assistant Chair Vaidyanathan Chelakara Ciena Corporation cvaidyan@ciena.com +1-613-670-2472

Rajen Dias Amkor Technology, Inc.

Praveen Pandojirao-S Johnson & Johnson

Harry G. Kellzi Teledyne Microelectronic Technologies

Bernd Ebersberger Intel Corporation

Mark Poliks Binghamton University

Masanobu Okayasu Oclaro Japan, Inc.

Takafumi Fukushima Tohoku University

Dwayne Shirley

Isaac Robin Abothu Siemens Medical Solutions USA Inc. Jai Agrawal Purdue University Ankur Agrawal Intel Corporation Meriem Akin Leibniz Universitaet Hannover Vasudeva P. Atluri Renavitas Technologies Mark Bachman University of California, Irvine

Thomas Gregorich SanDisk Li Li Cisco Systems, Inc. Changqing Liu Loughborough University Wei-Chung Lo ITRI James Lu Rensselaer Polytechnic Institute

Karlheinz Bock Technische Universitat Dresden

Voya Markovich Microelectronic Advanced Hardware Consulting, LLC

Benson Chan Integrated Electronics Engineering Center, Binghamton University

Lou Nicholls Amkor Technology, Inc.

Rabindra N. Das MIT Lincoln Labs Steve Greathouse Plexus Corporation Florian Herrault HRL Laboratories, LLC Yeo Hong VCU Ramakrishna Kotlanka Analog Devices Kevin J. Lee Qorvo Corporation Menglu Li Qualcomm Technologies, Inc. Minhua Lu IBM Corporation Bharat Penmecha Intel Corporation C. S. Premachandran GLOBALFOUNDRIES Jintang Shang Southeast University Nancy Stoffel GE Global Research Maaike M. Visser Taklo SINTEF ICT Jimin Yao Intel Corporation W. Hong Yeo Virginia Commonwealth University Yue Zhang Oracle Interconnections Chair Katsuyuki Sakuma IBM Corporation ksakuma@us.ibm.com +1-914-945-2080

Gilles Poupon CEA-Leti Lei Shan IBM Corporation Ho-Young Son SK Hynix Chuan Seng Tan Nanyang Technological University Matthew Yao GE Energy Management Dingyou Zhang Qualcomm Technologies, Inc. Materials & Processing Chair Bing Dang IBM Corporation dangbing@gmail.com +1-914-945-1568 Assistant Chair Mikel Miller Draper Laboratory mrmiller@draper.com +1-617-258-2844 Tanja Braun Fraunhofer IZM Yu-Hua Chen Unimicron Qianwen Chen IBM Corporation Yung-Yu Hsu Apple Inc. C. Robert Kao National Taiwan University Dong Wook Kim Xilinx, Inc. Chin C. Lee University of California, Irvine Alvin Lee Brewer Science

Ivan Shubin Oracle Lejun Wang Qualcomm Technologies, Inc. Frank Wei Disco Japan Kimberly Yess Brewer Science Myung Jin Yim Intel Corporation Hongbin Yu Arizona State University Tieyu Zheng Microsoft Corporation Modeling & Simulation Chair Kuo-Ning Chiang National Tsinghua University knchiang@pme.nthu.edu.tw +886-3-574-2925

Henning Schroeder Fraunhofer IZM Andrew Shapiro JPL Masato Shishikura Oclaro Japan Hiren Thacker Masao Tokunari IBM Corporation Jean Trewhella GLOBALFOUNDRIES Shogo Ura Kyoto Institute of Technology Stefan Weiss II-VI Laser Enterprise GmbH Feng Yu Huawei Technologies Japan

Assistant Chair Jiantao Zheng Qualcomm Technologies, Inc. jiantaoz@qti.qualcomm.com +1-858-658-5738

Thomas Zahner OSRAM Opto Semiconductors GmbH

Xuejun Fan Lamar University

Interactive Presentations Chair Michael Mayer University of Waterloo mmayer@uwaterloo.ca +1-519-888-4024

Przemyslaw Gromala Robert Bosch GmbH Nancy Iwamote Honeywell

Ping Zhou LDX Optronics, Inc.

Sheng Liu Wuhan University

Assistant Chair John Hunt Advanced Semiconductor Engineering, Inc. john.hunt@aseus.com +1-480-718-8011

Yong Liu ON Semiconductor

Swapan Bhattacharya Engent Inc.

Erdogan Madenci University of Arizona

Rao Bonda Amkor Technology

Pradeep Lall Auburn University

Tony Mak Wentworth Institute of Technology Erkan Oterkus University of Strathclyde Gamal Refai-Ahmed Xilinx Sandeep Sane Intel Corporation Suresh K. Sitaraman Georgia Institute of Technology Wei Wang Qualcomm Technologies, Inc. G. Q. (Kouchi) Zhang Delft University of Technology (TUD) Optoelectronics Chair Takaaki Ishigure Keio University ishigure@appi.keio.ac.jp +81-45-566-1593

Assistant Chair Nathan Lower Rockwell Collins, Inc. nathan.lower@rockwellcollins.com +1-319-295-6687

Yi Li Intel Corporation

Thibault Buisson Yole Développement

Yan Liu Medtronic Inc. USA

Assistant Chair Gordon Elger Technische Hochschule Ingolstadt gordon.elger@thi.de +49-841- 934-8284

William Chen Advanced Semiconductor Engineering, Inc.

Daniel D. Lu Henkel Corporation

Stephane Bernabe CEA LETI

Kwang-Lung Lin National Cheng Kung University

Alex Rosiewicz A2E Partners

Mark Eblen Kyocera America, Inc. Ibrahim Guven Virginia Commonwealth University Nam Pham IBM Corporation Mark Poliks Binghamton University Patrick Thompson Texas Instruments, Inc. Professional Development Courses Chair Kitty Pearsall Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287 Assistant Chair Jeffrey Suhling Auburn University jsuhling@auburn.edu +1-334-844-3332 Vijay Khanna IBM Corporation Lakshmi N. Ramanathan Microsoft Corporation

7


Be Part of The Next Generation

I N T R O D U C T I O N : T h e r m o C u r e   P r o c e s s  

Advantages include: Wear it.

Sense it.

Move it.

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s miniaturization, mobility, and IoT needs.

i) Bonding i) Bonding

ii)ii)Curing Curing

iii) Backside Backside iii) processing processing

iv)Debonding Debonding iv)

v) v)Cleaning Cleaning

Wire Bond

Flip Chip

WLP

2.5D & 3D

Fanout

SiP

BSI.T15140 series • Low-temperature bonding Include:   25°C to ≤ Advantages   100°C BSI.T16117 series •  Low  temperature  bonding  25°C   • Increased throughput •  Increased  throughput   • High-temperature High  temperature  survivability  ≤ survivability ≤ • 350°C •  Increased   adhesion  at  all  interfa • Increased adhesion at all interfaces •  Post  bond  TTV  ≤  5%  of  the  nomi line  thickness   • Post-bond total thickness •  Reduced  baking  &  cleaning  +me variation ≤ 5% of the nominal •  Compa+ble  with  mechanical  or   bond-line thickness debonding   • Reduced baking & cleaning times • Compatible with mechanical or laser debonding

All informa+on  is  CONFIDENTIAL  to  Brewer  Science    &  [company  name].   [DATE]  |  ©  2017  Brewer  Science,  Inc.  

Package it.  @asegroup_global

w w w. b r e w e r s c i e n c e . c o m

 aseglobal.com

© 2017 Brewer Science, Inc.

Looking

?

to improve your Polymer Cure

The answer is YES-VertaCure Automated High Temperature Vacuum Cure Oven Transforming atomic-scale engineering with market-leading deposition, etch, and clean technologies for front-end wafer processing and advanced packaging applications Learn how our innovative solutions can help you achieve success on the wafer

Connect with us

8

www.lamresearch.com

Increase: ROI Product Yield

Decrease: Polymer bake time Outgassing at metallization, from polymer & molding compound

www.yieldengineering.com 1.888.YES.3637


PROFESSIONAL DEVELOPMENT COURSES

Tuesday, May 30, 2017 Kitty Pearsall, Chair Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287 Jeff Suhling, Assistant Chair Auburn University jsuhling@eng.auburn.edu +1-334-844-3332

MORNING COURSES 8:00 a.m. – 12:00 Noon 1. ACHIEVING HIGH RELIABILITY OF LEAD-FREE SOLDER JOINTS – MATERIALS CONSIDERATIONS Course Leader: Ning-Cheng Lee – Indium Corporation Course Objectives: This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in detail. Novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whisker growth will also be discussed. Furthermore, the reliability of through-hole solder joints will be reviewed, and recommendations will be provided, particularly for thick boards. The emphasis of this course is placed on the understanding of how the various factors contribute to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization. Course Outline: 1. Implementation Status 2. Prevailing Materials: Alloys and Finishes 3. Surface Finishes Issues: ENIG, Immersion Ag, and Immersion Sn 4. Mechanical Properties: Shear, Pull, and Creep 5. Intermetallic Compounds: Effect of Cu, Ni, Other Additives, and Heat History 6. Failure Modes: Grain Deterioration, Orientation, Mixed Alloys, and Interfacial Voiding 7. Thermal Cycle Reliability: Effect of Cycling Condition, Surface Finishes, and Reflow Temperature 8. Reliability of Through-Hole Joints: Large and Thick Boards, Partially Filled Through-hole 9. Fragility: Effect of Surface Finishes, Alloys, Reflow, Strain Rate, Aging, Cycling, and IMC 10. Electromigration: Effect of Current Density, Back Stress, and Cu UBM Thickness

11. Corrosion: SAC and Performance of Surface Finishes Under Harsh Conditions 12. Tin Whisker: Causes of Formation, Methods for Control Who Should Attend: Anyone interested in achieving high-reliability leadfree solder joints and wanting to know how to achieve it should take this course. 2. WAFER LEVEL-CHIP SCALE PACKAGING Course Leader: Luu Nguyen – Texas Instruments, Inc. Course Objectives: This course will provide an overview of the Wafer Level-Chip Scale Packaging (WLCSP) technology. The market drivers, end applications, benefits, and challenges facing industry-wide adoption will be discussed. Typical WLCSP configurations (bumpon-pad, bump-on-polymer, fan-in, and fan-out) will be discussed in terms of their construction, manufacturing processes, materials and equipment, and electrical and thermal performance, together with package and board level reliability. Extensions to higher pin count packages and other arenas such as RF sensors and MEMS will be reviewed. Future trends covered will include enhanced lead-free solder balls, large die size, wafer level underfill, thin and ultra-thin WLCSP, RDL (redistribution layer), stacked WLCSP, MCM in “reconstituted wafers,” embedded components, and applications to large format (panel) processing. Since the technology marks the convergence of fab, assembly, and test, discussion will address questions on the industrial supply chain such as: Does it fit best with front-end or back-end processing? Are the current standards for design rules, outline, reliability, and equipment applicable? Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors? Course Outline: 1. Market Drivers for WLCSPs: Handsets, Medical, Automotive, Space, Imaging Sensors, MEMS, HBLEDs 2. Key WLCSP Technologies 3. Equipment and Materials Tool Box 4. Infrastructure Service Providers 5. PCB Pitch Reduction 6. Cost, Benefits, and Drawbacks of WLPs 7. Reliability: Thermal Cycling, Drop, Flex Testing, Electromigration 8. Fan-Out WLP 9. Supply Chain 10. Embedded Die 11. Chip First vs. Chip Last 12. Single Die Embedding vs. SiP Module 13. Challenges and Evolution to Large Format Processing Who Should Attend: The course will be useful to the following groups of engineers: Newcomers to the field who would like to obtain a general overview of WLCSP; R&D practitioners who would like to learn new methods for solving CSP problems; and those considering WLCSP as a potential alternative for their packaging solutions.

3. LED PACKAGING, SYSTEM, AND RELIABILITY CONSIDERATIONS Course Leader: Xuejun Fan – Lamar University Course Objectives: The light emitting diode (LED) has now emerged as a promising technology to replace conventional lighting, such as incandescent bulbs and compact fluorescent lamps, due to its superior energy efficiency, environmental friendliness, and particularly long lifetime (in the range of 25,000 – 100,000 hours). This course will present a comprehensive overview of recent advances in LED packaging, system integration, and reliability issues. Unlike traditional IC failure that is mainly characterized by catastrophic mode, LEDs’ performance is characterized by a dual-degradation mode: light output (lumen maintenance) degradation and color shift. Packaging structure, system integration, and materials play a very important role in LED efficacy and reliability. This course will cover the topics below: Course Outline: 1. LED Introduction 2. LED Basics 3. LED Packaging and System Integration 4. Basics of LEDs’ Photometry and Colorimetry • LED Packaging Evolution • LED Packaging Materials: Chip, Phosphor, Silicone, Reflector, Substrate, and System Integration 5. LED Packaging Materials and Degradation 6. LED Failure Mechanisms 7. LED Testing Standards and Specifications 8. Accelerated Testing and Lifetime Prediction 9. LED Driver and LED Driver Reliability 10. Thermal Management 11. Multi-Physics Modeling 12. Physics of Failure (PoF) Based Health Monitoring 13. System Reliability and Prediction 14. Conclusions Who Should Attend: The course is designed for staff members, technical managers, LED system reliability, design and manufacturing personnel, reliability engineers, and students who are interested in LED packaging, material selection, and LED reliability. The course does not assume prior knowledge in LED areas. 4. FUTURE OF DEVICE AND SYSTEMS PACKAGING: STRATEGIC TECHNOLOGIES, MFG. INFRASTRUCTURE, AND APPLICATIONS Course Leader: Rao Tummala – Georgia Institute of Technology Course Objectives: The semiconductor and systems landscape is changing dramatically. ICs are becoming commodities providing much lower profit margins than ever before, leading to industry consolidation to less than ten manufacturing companies within the next decade, worldwide. In addition, the cost and complexity of

IMPORTANT NOTICE It is extremely important to register in advance to prevent delays at door registration. Course sizes are limited. 9


transistor scaling is growing exponentially. There is no longer a cost reduction as the next node is introduced with higher transistor density. In addition, IC performance is being greatly impacted by interconnect delay and leakage. The driving engines for electronic systems are also changing dramatically to smart, wearable, wireless healthcare, wireless networks and new era of selfdriving and electric cars, requiring an entirely different vision and strategy than transistor scaling alone that has been and continues to be practiced the last 60 years. These systems are small to ultra-small systems, yet must perform dozens of functions that include high-speed digital, high-efficiency power, 5G and millimeter wave, MEMS, and sensors. The new era of automotive electronics, in addition, requires a variety of sensing technologies for self-driving cars such as camera, LiDAR and radar, and ultra-high power for electric cars. All these emerging or nextgeneration computing, communications, consumer and automotive systems pose device, packaging and integration barriers. They require a new role for packaging. Future packaging must address these devices and systems’ barriers by enabling better and cheaper devices and highly-integrated and ultra-miniaturized systems. The advances need to be more than Moore’s (MTM) Law with on-chip transistor integration with 2D and 2.5D MCM, 3D stacked ICs with TSV and SIP. They require a new paradigm in systems packaging, referred to as “System Moore’s” Law (SM) for complete systems. Such a concept requires new system package architecture beyond SIP, 2.5D and 3D with TSV. The course will review the current approach to devices, device packaging and system packaging. These include traditional single and multi-chip packaging as well as the recent focus in embedded and fan-out packaging. This course describes IC and system packaging challenges and potential solutions that lie ahead in strategic technologies, manufacturing infrastructures and applications. Course Outline: 1. Emerging Electronic Systems 2. Current Approach to Devices and Device Packaging 3. Strategic Packaging Technologies to Enable Future Devices • Integration of Homogeneous and Heterogeneous Devices in 2D, 2.5D, and 3D Multi-Chip Packaging which Requires I/O Scaling Similar to BEOL. 4. Strategic Systems Packaging Technologies to Enable Future Systems • Envisioned is a System Scaling Concept that includes Devices by Transistor Scaling but Goes Beyond to include Components and Interconnections. 5. Current vs. Future Packaging Manufacturing Infrastructure • Current: Limited to Wafer-Based with BEOL Tools or Panel-Based Tools with Low I/O Density • Future: Panel-Based BEOL-Like Packaging 6. Emerging and High-Growth Applications 7. Applications of Future Packaging to Emerging Systems Who Should Attend: Senior marketing and R&D executives as well as senior managers who are dealing with strategic issues facing the electronics industry should attend.

10

5. POLYMERS AND NANOCOMPOSITES FOR ELECTRONIC AND PHOTONIC PACKAGING Course Leaders: C. P. Wong – Georgia Institute of Technology and Daniel Lu – Henkel Corporation Course Objectives: Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel no-flow underfills, reworkable underfills for ball grid array (BGA), chip scale packaging (CSP), system in a package (SIP), direct chip attach (DCA), flip-chip (FC), paper-thin IC and 3D packaging, conductive adhesives (both ICA and ACA), embedded passives (high K polymer composites), nano particles and nano functional materials such as CNTs (some with graphenes). It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies. Course Outline: 1. Fundamentals of Polymers and Materials Science and Engineering 2. Material Needs for Next Generation Electronic Packaging 3. Novel Nanocomposites for Flip-Chip Underfill Applications 4. Recent Advances on Nano Lead-Free Alloys for High Performance Components Interconnects 5. Low-Cost High Performance Lead-Free Interconnect Materials and Processes 6. Recent Advances on CNTs as Thermal Interface Materials (TIMs) 7. Lotus Effect Coating for Self-Cleaning Applications 8. Fundamentals of Electrically Conductive Adhesives (ECAs) 9. Recent Advances on Conductive Adhesives 10. Recent Advances on Nano Conductive Adhesives Who Should Attend: Engineers, scientists and managers involved in designing, processing and manufacturing of microelectronic and optoelectronic components and packages, material suppliers, and students and researchers on electronic packaging should attend. 6. INTEGRATED THERMAL PACKAGING AND RELIABILITY OF POWER ELECTRONICS Course Leaders: Patrick McCluskey and Avi Bar-Cohen – University of Maryland Course Objectives: Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, smart grids, and data centers. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and

enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics. Following a quick review of active heat transfer techniques, along with prognostic health management approaches to assess and ensure reliability, this short course will present the latest developments in the materials (e.g. organic, flexible), packaging, assembly, and thermal management of power electronic modules, MEMS, and systems along with modeling and testing techniques. Thermal isolation, glass substrates, heterogeneous integration, and non-traditional module structures will be included. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components. Course Outline: 1. Introduction to Integrated Thermal Packaging for Reliable Power Electronic Systems 2. Simulation and Assessment of Active Thermal Management Techniques: Air, Single Phase Liquid, Two Phase, Phase Change Materials, and Thermal Interface Materials 3. Application of Thermal Management Techniques to Commercial Power Systems/ Data Centers including Embedded Cooling 4. Durability Assessment: Failure Modeling, Simulation, Testing, Prognostics and Health Monitoring 5. Reliability and Thermal Packaging of Active Devices: Si, SiC, GaN and Interconnects 6. Reliability and Thermal Packaging of Switching Modules, including Organic Encapsulates 7. Reliability in Rigid Assembly Packaging: PCB, Solders, and Glass Interposers 8. Flexible Materials, Packaging, and Thermal Management: Flex Circuit, OLED, and Wearables 9. Reliability of 3D Power Packaging including Additive Manufacturing 10. MEMS and Sensor Packaging Who Should Attend: This course is intended for power electronic systems designers and managers who would like to add heat transfer, manufacturability and reliability criteria to their designs for longer life products with improved performance. In addition, it would be useful to thermal, mechanical, and materials engineers active in the power electronic communities who want to see the latest research developments. 7. FUNDAMENTALS OF ELECTRICAL DESIGN AND FABRICATION PROCESSES OF INTERPOSERS, INCLUDING THEIR RDLs Course Leaders: Ivan Ndip and Michael Töpper – Fraunhofer IZM Course Objectives: As a result of their myriad advantages in systemintegration, glass and silicon interposers will continue to play a crucial role in the development of future electronic systems. The fabrication processes and electrical performance of these interposers, including their re-distribution layers (RDLs), will contribute significantly to the cost and performance of the entire system. The objective of this course is to provide and illustrate the fundamentals of the fabrication


processes and electrical design of glass and silicon interposers, including their RDLs. An overview of advanced packaging technologies and the role of interposers will first be given. This will be followed by a thorough discussion of silicon interposers, throughsilicon via (TSV) generation process and tools, as well as glass interposers and options for though-glass vias (TGV) generation and metallization. Major challenges of RDL build-up on thin interposer substrates will be presented and advanced RDL materials and technologies to realize routing down to 3 µm in interposers will be discussed. The fundamentals of efficient electrical design of interposers and RDLs up to millimeter-wave frequencies will be given. Finally, the RF performance of transmission lines and vias in these interposers will be compared. Examples of interposers designed and fabricated at Fraunhofer IZM will also be discussed. Course Outline: 1. Introduction to Advanced Packaging Technologies and the Role of Interposers 2. Silicon Interposers: Illustration of TSV Generation Process and Tools 3. Glass Interposers: Illustration of Technology Options for TGV Generation and Metallization 4. Presentation of Thin Substrate Handling and Temporary Bonding 5. Comparison between Glass, Silicon and Organic-Based Interposers 6. Illustration of RDL Generation and their Role in CSP and FO-WLP 7. Discussion of Major Challenges of RDL BuildUp on Thin Interposer Substrates 8. Advanced RDL Materials/Technologies to Realize Routing Down to 3 µm in Interposers 9. Electrical Design Challenges of Interposers and RDLs: Signal/Power Integrity and EMI Issues 10. New Design Approach for Applications up to Millimeter-Wave Frequencies 11. Explanation of Fundamental Electrical Design Concepts: Impedance, RLCG Parasitics, S-Parameters 12. Electrical Design, Measurement and Comparison of Transmission Lines on RDLs and Interposers 13. Electrical Design, Measurement and Comparison of TSVs and TGVs 14. Examples of Interposers Designed, Fabricated and Characterized at Fraunhofer IZM Who Should Attend: Engineers, researchers, designers, technical managers and graduate students involved in the process of electrical design, layout, processing, fabrication and/ or system-integration of interposers and electronic packages. 8. INTRODUCTION TO MECHANICS BASED QUALITY AND RELIABILITY ASSESSMENT METHODOLOGY Course Leaders: Shubhada Sahasrabudhe and Sandeep Sane – Intel Corporation Course Objectives: This course presents a unique integrated methodology that combines two essential domains, engineering mechanics and reliability statistics, to perform standards-based or knowledge-based risk assessment to meet the dynamic market demand for electronic devices. To ensure that corporate Q&R goals are met, it is vital to have a comprehensive understanding of device usage and complete characterization of physics of failure. This

course discusses key elements of Q&R like use conditions (UC), accelerated life tests, statistical data analysis methods, acceleration factor models, DPM risk assessment at UC, FA tools/techniques, design for reliability and experiment planning. In addition, it provides an overview of the fundamental concepts of solid mechanics such as stress-strain curves, characterization of material behavior, stress analysis methods including finite element analysis (FEA) with specific application to packaging, material characterization metrologies and FEA model validation techniques. The course offers a deep dive into a few key mechanisms such as Si-package interactions, SJR, die cracking, etc. to highlight successful application of this integrated methodology. They highlight benefits of driving proactive product risk assessment at UC and optimizing product design/process/ materials for manufacturability/ quality/reliability. The course will explore the application of this integrated methodology in traditional and new markets like wearables and Internet of Things. Students will perform multiple hands-on exercises throughout the duration of the course to reinforce the fundamental concepts and the value of integrated methodology. Course Outline: 1. Packaging Technology: Trends and Challenges 2. Introduction to Quality and Reliability 3. Overview of Key Components of Reliability Statistics and Accelerated Testing 4. Hands-On Class Exercise 1 5. Introduction to Solid Mechanics 6. Key Components of Solid Mechanics: Stress/ Strain Curves, Failure Theories, FEA 7. Material Characterization Metrologies and Analysis Validation Techniques 8. Key Failure Mechanisms and Failure Analysis Tools/Techniques. 9. Overlapping Areas between Reliability and Mechanics 10. Overview of the Unified Reliability Assessment Methodology Using Mechanics 11. Application of Methodology to Key Organic Package Failures 12. Hands-On Class Exercise 2 13. Summary of Key Learning Elements Who Should Attend: Packaging engineers involved in design, development, production, and reliability testing of semiconductor packages would benefit from the course. 9. THERMO-ELECTRIC COOLERS: CHARACTERIZATION, RELIABILITY, AND MODELING Course Leader: Jaime Sanchez – Intel Corporation Course Objectives: Thermo-electric coolers are devices widely used in the semiconductor industry as the main thermal engines for thermal control during test of integrated circuit devices. They offer the ability to both heat and cool a device under test to mimic worst case platform conditions and defect screening at different temperatures. In this short course, we will review fundamental characterization techniques of thermoelectric coolers that allow the direct measurement of relevant properties such as the effective Seebeck coefficient, electrical resistivity, and thermal impedance. A detailed numerical modeling approach will be discussed that utilizes user-defined functions in Fluent that allows a close representation

of these devices matching experimental conditions. Experimentation and numerical analysis techniques will be discussed that enable the full characterization of a thermal solution based on thermoelectric coolers both in steady and transient state. A comprehensive overview of modeling and experimentation techniques will be provided that capture the dynamic behavior of a thermal solution connected to a closed loop control algorithm: the impact of various approaches of controlling the junction temperature of a device under test under different conditions, as well as the sensitivity of the dynamic response of the full system including the effect of active power management of the device under test. Finally, experimental techniques based on reliability statistics will be covered that have a direct application into predicting the life of a thermo-electric cooler under various test conditions. Course Outline: 1. Introduction • State-of-the-Art in Thermo-Electricity Research • What is Thermo-Electricity • General Industrial Applications 2. TEC Modules Governing Principles • Single Peltier Couple to a TEC Module • Governing Equations and Relationships • Example of TEC Module Selection Based on a Static Cooling Application 3. TEC Module Characterization and Modeling • Experimental Setups and Methodology • Overview of Analytical Approaches • Overview of Transient Characterization 4. Operation of TEC Modules in Dynamic Closed Loop Control • Applications to Test ICs 5. Reliability of TECs • Overview of Failure Modes • Improvements for Test Application 6. Summary and Future Directions 7. References Who Should Attend: This course is intended for students and engineers in the electronics cooling industry specifically, but should be of interest for those working with thermo-electric modules in general. The class will cover experimental and numerical methods.

AFTERNOON COURSES 1:15 p.m. – 5:15 p.m. 10. FLIP CHIP TECHNOLOGIES Course Leaders: Eric Perfecto – GLOBALFOUNDRIES and Shengmin Wen – Synaptics Inc. Course Objectives: This course will cover the fundamentals of flip-chip assembly process that involves wafer bumping, solder joint formation, substrate and/or redistribution selection, and underfill processes. All aspects of bumping technologies, including lead-free solder bumping and highly customized Cu Pillar technologies used in today’s flip-chip are addressed in depth, including the details and comparison of various UBM (electroplating, electroless plating and sputtering) and solder (electroplating, ball drop, IMS, and solder screening) depositions methods. Solder joint formation technologies used in single and multi-die assembly of chip scale packages, wafer-level packages, chip-on-chip, chip-on-wafer, and 2.5D/3D flip chip packages are discussed and demonstrated through

11


industrial’s leading application examples. The course provides a list of items to consider when choosing a particular flip-chip assembly process for a specific application such that a reliably and cost effective solution can be planned out of various methods to bump the wafer and different substrates types (organic laminate, ceramic, and Si substrates). Chip package interaction (CPI), package warpage control, and yield detractors for flip-chip assembly are discussed in detail. Advanced and current trend of flip-chip assembly processes are provided briefly. This course will cover the reliability tests commonly used to qualify the flip-chip assembled packages, the failure types and the analytical tools used to identify defect root cause. A substantial portion of this course will cover Cu Pillar flip-chip technologies. Failure modes, such as barrier consumption, Kirkendall void formation, non-wets, BEOL dielectric cracking, electromigration, etc. will be dispersed within in the related subjects of the whole course. Students are encouraged to bring topics and technical issues from their past, present and future job function for group discussions. A 20-minute group exercise at the end of the class is planned to make sure the students can walk away with the course knowledge that applies to their daily job function. Course Outline: 1. Introduction to Flip-Chip Technologies 2. UBM Metal Selection 3. Flip-Chip Solder Deposition Processes 4. Cu Pillar Bumping 5. C4 and Cu Pillar Fabrication Issues 6. Electromigration 5. Flip-Chip Plastic Ball Grid Array (FCPBGA) Assembly Process Flow 6. Cu Pillar Assembly: Mass Reflow and Thermal Compression 7. Flip-Chip Ball Grid Array (FCBGA) Assembly Process Flow 8. Flip-Chip Technology New Trends: Wafer Level, Panel Level and u-BGA 9. Flip-Chip Si Package Co-Design and ChipPackage Interaction 10. Substrate Technologies, Underfill, Package Warpage Control, and Yield 11. Flip-Chip Reliability Assessment, Failure Modes, Examples, and Modeling Who Should Attend: The targeted audience includes scientists, engineers, and managers currently using flip-chip (with solder or Cu pillar) or those considering moving from wire bonding to flip-chip, as well as reliability, product or applications’ engineers who need a deeper understanding of flip-chip technologies: the advantages, limitations and failure mechanisms. 11. PACKAGE FAILURE ANALYSIS - FAILURE MECHANISMS AND ANALYTICAL TOOLS Course Leaders: Rajen Dias – Amkor Technology and Deepak Goyal – Intel Corporation Course Objectives: The technical course will provide an overview of the failure modes and mechanisms observed in organic semiconductor packages. A brief introduction to the methodology of failure analysis for these packages will be described. The focus of the course will be on package failure mechanisms highlighted by case studies, analytical tools and techniques currently used, and the future direction for analytical tools and

12

techniques required for successful and timely failure analysis of next generation package technologies. A discussion on the strategies for using these techniques and a flow chart for failure analysis will be included.

6. 7. 8.

Course Outline: 1. Package Technology: Trends, Drivers and Challenges 2. Failure Analysis Challenges Offered by Package Technology Roadmaps 3. Introduction to the Methodology of Failure Analysis of Packages 4. Current Analytical Capabilities for Package Fault Isolation and Failure Analysis 5. Strategies to Use these Techniques to Identify Failures and Understand Failure Mechanisms 6. Analytical Capabilities to Support NextGeneration Packaging Technologies 7. Typical Failure Analysis Flow Charts for Opens and Shorts 8. Failure Modes/Mechanisms including Chip/Package Interactions, 1st/2nd Level Interconnections and Package/Board Substrates 9. Failure Analysis Case Studies: Flip-Chip, Wire Bond, 3D Stacked Die, WLFO and MEMS Package Technologies

9.

Who Should Attend: Engineers and technical managers who are involved in package technology development, reliability assessment of packages and failure analysis should attend. 12. 3D IC INTEGRATION AND 3D IC PACKAGING Course Leader: John Lau – ASM Pacific Technology Ltd. Course Objectives: Recent advances in fan-out wafer/panel level packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/ Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration, 3D CIS/IC integration, and 3D MEMS/IC integration will be discussed in this presentation. Emphasis is placed on various FO-WLP formation methods such as chip-first with die-up, chip-first with die-down, and chip-last (RDL-first). Since RDLs (redistribution layers) play an integral part of FO-WLP, various RDL fabrication methods such as Cu damascene, polymer, and PCB will be discussed. A few notes and recommendations on wafer vs. panel, dielectric materials, and molding materials will be provided. Also, TSV-less interposers such as those given by Xilinx/SPIL, Amkor, SPIL/Xilinx, ASE, MediaTek, Intel, ITRI, Shinko, Cisco/eSilicon, Sony’s TSV-less CIS, and Samsung/Hynix (HBM3) will also be discussed. Furthermore, new trends in semiconductor packaging will be presented. Course Outline: 1. FOW/PLP: Chip-First (Die-Up/Down), ChipLast (RDL-First) 2. RDL Fabrications: Polymer, PCB/LDI, Cu Damascene Methods 3. InFO-WLP, TSMC InFO-PoP vs. Samsung ePoP 4. Dielectric and Epoxy Mold Compound 5. Semiconductor and Packaging for IoTs (SiP)

10. 11. 12. 13. 14. 15.

16.

Wafer vs. Panel Carriers, WLSiP and PLSiP TSV Formation Memory Chip Stacking with TSV: Samsung’s DDR4 Hybrid Memory Cube (HMC) with TSV: Intel’s Knights Landing with Micron’s HMC High Bandwidth Memory (HBM) with TSV: AMD/Nvidia’s GPU, Hynix/Samsung’s HBM Memory + Logic with TSV: Samsung’s Widcon 3D IC/MEMS Integration and 3D IC/CIS Integration Embedded 3D Hybrid Integration 2.5D IC Integration: TSMC/Xilinx’s CoWoS (Chip-on-Wafer-on-Substrate) TSV-Less Interposer: Xilinx/SPIL’s SLIT, Amkor’s SLIM, ASE’s FOCoS, Intel’s EMIB, ITRI’s TSH, Shinko’s i-THOP, Cisco’s Organic Interposer, Sony’s CIS, SPIL/Xilinx’s NTI, Samsung’s Organic Interposer, etc. Semiconductor Packaging New Trends

Who Should Attend: If you are involved with any aspect of the electronics/ optoelectronic industry, you should attend this course. Each participant will receive more than 200 pages of handout materials from the lecturer’s books and the papers published by others. 13. FLEXIBLE HYBRID TECHNOLOGIES Course Leader: Pradeep Lall – Auburn University Course Objectives: In this course, manufacture, design, assembly, and accelerated testing of flexible hybrid electronics for applications in some of the emerging areas will be covered. Flexible hybrid electronics opens the possibilities for the development of stretchable, bendable, foldable form-factors in electronics applications which have not been possible with the use of rigid electronics technologies. Flexible electronics may be subjected to strain magnitudes in the neighborhood of 50-150 percent during normal operation. The integration processes and semiconductor packaging architectures for flexible hybrid electronics may differ immensely in comparison with those used for rigid electronics. The manufacture of thin electronic architectures requires the integration of thin-chips, flexible encapsulation, compliant interconnects, and stretchable inks for metallization traces. A number of additive manufacturing processes for the fabrication and assembly of flexible hybrid electronics have become tractable. Processes for handling, pick-and-place operations of thin silicon and compliant interposers through interconnection processes such as reflow requires an understanding of the deformation and warpage processes for development of robust process parameters which will allow for acceptable levels of yields in high-volume manufacture. Modeling of operational stresses in flexible electronics requires the material behavior under loads including constant exposure to human body temperature, saliva, sweat, ambient temperature, humidity, dust, wear and abrasion. The strains imposed on flexible stretchable electronics may far exceed those experienced in rigid electronics requiring the consideration of finite-strain

IMPORTANT NOTICE It is extremely important to register in advance to prevent delays at door registration. Course sizes are limited.


formulation in development of predictive models. The failure mechanisms, failure modes, acceleration factors in flexible electronics under operational loads of stretch, bend, fold and loads resulting from human body proximity are significantly different than rigid electronics. The testing, qualification and quality assurance protocols to meaningfully inform manufacturing processes and ensure reliability and survivability under exposure to sustained harsh environmental operating conditions, may differ in flexible electronics as well. A number of product areas for the application of flexible electronics are tractable in the near-term including Internet-ofThings (IoT), medical wearable electronics, textile woven electronics, robotics, communications, asset monitoring and automotive electronics. Course Outline: 1. Ultra-Thin Chips 2. Die-Attach Materials for Flexible Semiconductor Packaging 3. Compliant Interconnects 4. Flexible Encapsulation Materials 5. Inkjet and Aerosol-Jet Printing Processes 6. Dielectric Materials for Large-Area Flexible Electronics 7. Flexible Substrates 8. Stretchable Inks for Printed Traces 9. Pick-and-Place and Material Handling Processes 10. Additive Technologies in Flexible Electronics 11. Reflow and Printing Processes 12. Accelerated Testing Protocols Who Should Attend: The course is intended to introduce the attendees to the general area of flexible hybrid electronics.. 14. POLYMERS FOR ELECTRONIC PACKAGING Course Leader: Jeffrey Gotro – InnoCentrix, LLC Course Objectives: The course will provide a broad overview of polymers used in semiconductor packaging and the important structure-property-process-performance relationships. We will cover in more depth the chemistries, material properties, and process considerations for adhesives, underfills, coatings and mold compounds. Additionally, we will provide an introduction to common thermal analysis methods (DSC, DMA, TMA, and TGA) used to characterize thermosetting polymers used in semiconductor packaging. Finally, the course will provide an introduction to the rheological performance of polymer-based materials used in packaging semiconductors. In most cases, adhesives, underfills, mold compounds and coatings are applied as a viscous liquid and then cured. The flow properties of these materials are critical to performance in high volume manufacturing. The course will provide an introduction to rheology measurements and examples of rheology issues in semiconductor packaging. Course Outline: 1. Thermosetting Polymers Versus Thermoplastics 2. Temperature Dependence of Physical Properties 3. Themosetting Polymers: Curing, Curing mechanisms, Network Formation 4. Overview of Key Chemistries Used: Epoxies, Acrylates, Polyimides, Bismaleimides 5. Chemistry of Die Attach Adhesives: Paste, Film and Wafer Applied

6.

Chemistry and Physics of Capillary Underfills, Pre-Applied Underfills, Wafer Level Underfills, 7. Polymers used in Wafer Level Packaging, ewLP, and Other Fan-Out Packages 8. Packaging Substrate Materials and Process 9. Encapsulants (Mold Compounds) and Coatings 10. Introduction to Rheological Characterization Methods: Types of Rheometers and Basic Techniques 11. Introduction to the Rheological Properties of Adhesives 12. Key Rheology Properties: Shear Thinning, Viscosity, Rheology Changes during Curing Who Should Attend: Packaging engineers involved in the development, production, and reliability testing of semiconductor packages would benefit from the course. R&D professionals interested in gaining a basic understanding of the structure/property/process/ performance relationships in polymers and polymerbased materials used in electronic packaging will also find this course valuable. 15. EMERGING INTERCONNECT AND SYSTEM INTEGRATION TECHNOLOGIES Course Leader: Muhannad Bakir – Georgia Institute of Technology Course Objectives: Interconnects have emerged as a critical bottleneck to the realization of lower-power and higherperformance electronics. Coupled with this, the need for ever more tightly integrated systems present unique cooling and power delivery challenges for next-generation electronics. This short course will present an overview of emerging technologies to address these need areas and present key modeling results to help guide technology development. The modeling effort presented in the short course will not only help us understand the design considerations of the technologies discussed but will also help benchmark the performance of the various technologies so that optimal systems can be developed. Course Outline: 1. Advances in 2.5D Chip Integration, including Silicon-Bridge Based Approaches 2. 3D Integration Approaches, including Monolithic 3D ICs 3. Photonic Interposer and Package Technologies, including the Modeling of Diffractive Grating Couplers and the Impact of Misalignment 4. Thermal and Power Delivery (Power Supply Noise) Physical Modeling and Learning 5. Advanced Cooling and Thermal Decoupling Technologies in Multi-Die Interconnected Systems, including Microfluidic Cooling 6. Mechanically Flexible Interconnects in Assembly of High-I/O Density Chips 7. Example Bioelectronic Systems Enabled by Advanced Interconnection and Packaging Who Should Attend: This short course will be of value to those working in the areas of interconnects, packaging, 3D technology, and heterogeneous integration.

16. PACKAGE FAILURE MECHANISMS, RELIABILITY, AND SOLUTIONS Course Leader: Darvin Edwards – Edwards Enterprises Course Objectives: This course explores past and present reliability failure modes and mechanisms that plague semiconductor packages. Primary reliability challenges in TSV and FOWLP packaging, as well as major failure mechanisms for FC-BGA, WLCSP, plastic leaded, no lead, and selected MEMS package types will be described. The class will cover reliability concerns such as TSV-chip interactions, micro bump mechanical reliability, electromigration performance, stress induced ILD damage under bumps and wire bonds, Cu vs. Au wire bond reliability challenges, problems associated with delamination in packages, solder joint reliability, system level issues such as drop and bend reliability, and the impact of aging on reliability performance. For each failure mechanism, the failure modes and failure analysis techniques needed to verify the mechanisms will be summarized. Recommended failure analysis fault isolation techniques will be described. This solutions focused course concentrates on process parameters, design techniques and material selections that eliminate the failures and improve reliability to ensure participants can design in reliability and design out failures. The development and characterization of design guidelines that enable reliable products will be described and encouraged. A test structure methodology combined with qualification by similarity will be highlighted as a process for early detection of chip/package reliability risks. Course Outline: 1. Introduction and Description of IC Package Types 2. Failure Analysis Techniques and Fault Isolation Flow 3. Package Failure Mechanisms: FC-BGAs 4. Package Failure Mechanisms: Molded and Leaded Packages 5. Package Failure Mechanisms: WLCSPs 6. Package Failure Mechanisms: Embedded Die/ Fan-Out WLPs 7. Package Failure Mechanisms: TSVs 8. Package Failure Mechanisms: MEMS 9. Materials, Modeling, Design Rules and Reliability 10. Common Test Structures for Failure Mechanism Identification 11. Qualification By Similarity (QBS) 12. Summary Who Should Attend: This class is intended for all who work with IC packaging, package reliability, package development, package design, and package processing where a working knowledge of package failure mechanisms will prove useful. Both beginning engineers and those skilled in the art will benefit from the holistic description of the failure mechanisms and proven solutions. 17. AGEING OF POLYMERS AND THE INFLUENCE ON MICROELECTRONIC PACKAGE RELIABILITY Course Leaders: Tanja Braun and Ole Hölck – Fraunhofer IZM Course Objectives: Many electronic products used in different applications, such as automotive, medical, and some consumer are exposed to extreme loading

13


profiles. High temperatures, random vibrations or humid and or wet environments affect system and materials. Lifetime demands of 10 years and above in combination with these challenging environments requires well known materials and broad knowledge on their behavior over the entire lifetime. Polymers are widely used in microelectronics packaging e.g. as interconnect material, encapsulant or substrate. But polymers age with time, temperature and humidity. Ageing entails a change in properties including mechanical, thermo-mechanical or adhesion characteristics, all of which are key factors for reliable package solutions. Hence, knowledge on materials and their ageing behavior is essential for developing reliable microelectronics packages and systems. Course Outline: 1. Introduction of Polymers used in Microelectronics 2. Important Aspects of Encapsulation Technologies for Reliable Packaging 3. Ageing Mechanisms of Polymers 4. Adhesion and Interface Degradation 5. Test Methods and Selection Criteria for Polymers in Microelectronics Packaging 6. Overview of State-of-the-Art Measurement Equipment 7. Moisture and Temperature Induced Changes in Material Properties 8. Lifetime Simulation by FEM taking Polymer Degradation into Account 9. Failure Mechanisms Related to Polymer Ageing Who Should Attend: The course is targeted for engineers and engineer management in the field of microelectronic package design, development and reliability engineering. The attendees will learn about material selection, polymer ageing and the related influence on package reliability and will gain knowledge on how to build high reliable packages. 18. THERMO-ELECTRICAL CO-DESIGN FOR 3D INTEGRATION Course Leaders: Ankur Srivastava University of Maryland and Avram BarCohen - Raytheon Course Objectives: 3D integration of computational and RF components (in both homogeneous and heterogeneous combinations) provides significant improvements in functional efficiency, device density, and interconnect delays but is expected to lead to higher heat densities, along with decreased thermal management access to individual chips and on-chip hotspots. To fully achieve the inherent advantages of 3D integration it will, thus, be necessary to implement “embedded cooling” approaches and unify the thermal, mechanical, and electrical design of chip stacks and other integrated packaging configurations. Thermo-electrical co-design for 3D integration is the theme of this CPMT Professional Development Course The PDC will begin with a brief review of 3D and 2.5D packaging form factors and the expected areal and volumetric heat extraction rates. It will be shown that conventional “remote cooling” techniques are incapable of meeting these thermal requirements, necessitating the use of “embedded cooling” solutions, including on-chip thermal vias, micro-fluidics, and thermoelectrics. Attention will then turn to creating an integrated co-design environment that will enable designers to perform the electrical-thermal-mechanical trade-offs needed

14

to create computational and RF modules that achieve the highest functional throughput and efficiency. The PDC will close with presentation and discussion of several co-design case studies which demonstrate the added value of an integrated co-design environment. Co-Design for two distinct and significant integrated systems will be discussed: high performance computational modules and integrated Power Amplifier MMICs . For the computational modules we will discuss how greater performance and energy efficiency can be extracted by exploiting the unique interplay between power, performance and reliability for CPUs, ASICs and FPGA. For Power Amplifier MMICs we will discuss co-design techniques for generating greater gain, power-added efficiency (PAE), and output power thru the application of embedded cooling technologies. Course Outline: 1. 3D/2.5D Packaging Trends 2. Embedded Cooling State-of-the-Art 3. Electronic Design Automation 4. Integrated Co-Design Environment 5. Thermo-Electrical Co-Design Case Studies: Computation 6. Thermo-Electrical Co-Design Case Studies: MMICs 7. Review and Lessons Learned

Continuing Education Units The IEEE Components, Packaging and Manufacturing Technology Society (CPMT) is authorized to offer Continuing Education Units (CEUs) by the International Association for Continuing Education and Training (IACET) for all Professional Development Courses (PDCs) that will be presented at the 67th ECTC. CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia, and workshops. Complete details, including voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Course CEUs will be underwritten by the conference, i.e., there are no additional costs for Professional Development Course attendees to obtain CEU credit.

Who Should Attend: The growing use of integrated co-design environments is blurring the line between IC designers and packaging engineers and creating a new class of EDA practitioners. This course will provide an introduction to this emerging EDA domain. The course is tailored to both IC designers and packaging engineers seeking to better understand the interplay between electrical and thermo-mechanical aspects of component design and how to best manage the trade-offs needed to achieve the highest functional throughput and efficiency in computational and RF components.

IMPORTANT NOTICE Morning PD Courses 1 through 9 or afternoon PD Courses 10 through 18 run concurrently. Make sure you indicate specific course numbers you plan to attend when you register online. See page 30 for registration information.

AREA ATTRACTIONS In the heart of the Walt Disney World® Resort, the award-winning Walt Disney World Swan and Dolphin Resort is your gateway to Central Florida’s greatest theme parks and attractions. The resort is located in between Epcot® and Disney’s Hollywood Studios™, and nearby Disney’s Animal Kingdom® Theme Park and Magic Kingdom® Park. Come discover our 17 world-class restaurants and lounges, sophisticated guest rooms with Westin Heavenly Beds® and the luxurious Mandara Spa. Enjoy five pools, two health clubs, tennis, nearby golf, and many special Disney benefits, including complimentary transportation to Walt Disney World theme parks and attractions and the Extra Magic Hours benefit. Just minutes from the Walt Disney World Swan and Dolphin Resort is Downtown Disney’s West Side and Marketplace. Downtown Disney’s West Side showcases top-notch restaurants, a 24-screen AMC Pleasure Island movie theater, and other uncommon shops. Here you’ll also find the exquisite Cirque du Soleil La Nouba live entertainment show and the DisneyQuest Indoor Interactive theme park. Downtown Disney Marketplace provides an appealing place to take a break from Disney theme parks and water parks. Check out the largest Disney character store in the world. Or, for more of a respite, relax and dine at a lakeside restaurant. Should you decide to explore outside the greater Lake Buena Vista area, Orlando boasts other parks and recreation areas tailor made for your pleasure. Favorites include Universal Orlando, SeaWorld, Gatorland, and Winter Park.


Program Sessions: Wednesday, May 31, 8:00-11:40 a.m. Session 1: Fan-Out Packaging Process and Integration

Session 2: TSV Process, Characterization and Applications

Session 3: Flip Chip Assembly

Committee: Advanced Packaging

Committee: Interconnections

Committee: Assembly & Manufacturing Technology

Session Co-Chairs: Beth Keser – Intel Corporation Email: beth.keser@intel.com

Session Co-Chairs: Takafumi Fukushima – Tohoku University Tel: +81-22-795-6978 Email: fukushima@lbc.mech.tohoku.ac.jp

Session Co-Chairs: Valerie Oberson – IBM Canada Ltd. Tel: +1-450-534-7767 Email: voberson@ca.ibm.com

Voya Markovich – Microelectronic Advanced Hardware Consulting, LLC Tel: +1-631-544-4625 Email: vojarm@gmail.com

Mark Gerber – Advanced Semiconductor Engineering Inc. Tel: +1-214-305-2154 Email: mark.gerber@aseus.com

1. 8:00 AM - Development of a Multi-Project Fan-Out Wafer Level Packaging Platform Tanja Braun, Stefan Raatz, Marius van Dijk, Karl-Friedrich Becker, and Rolf Aschenbrenner – Fraunhofer IZM; Markus Wöhrmann, Steve Voges, and Klaus-Dieter Lang – Technical University Berlin; Matthias Wietstruck and Mehmet Kaynak – IHP Microelectronics

1. 8:00 AM - A Cost-Effective Via Last TSV Technology Using Molten Solder Filling for Automobile Application Yuki Ohara, Yuki Inagaki, Masaki Matsui, and Kazushi Asami – DENSO

1. 8:00 AM - Key Properties for Successful Ultra Thin Die Pickup Stefan Behler and Brian Pulis – Besi Switzerland; Teng Wang and Arnita Podpod – IMEC

2. 8:25 AM - SLIM™, High-Density Wafer Level Fan-Out Package Development with Submicron RDL Youngrae Kim, JaeHun Bae, MinHwa Chang, AhRa Jo, Ji Hyun Kim, SangEun Park, David Hiner, Mike Kelly, and WonChul Do – Amkor Technology

2. 8:25 AM - Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers Matthias Wietstruck, Steffen Marschmeyer, Marco Lisker, Andreas Krueger, Dirk Wolansky, Philipp Kulse, Alexander Goeritz, Thomas Voss, Andreas Mai, and Mehmet Kaynak – IHP; Mesut Inac – Technical University Berlin

2. 8:25 AM - Development of Vertical MultiChip Thermal Compression Bonding for High Productivity 3D IC Applications Tae-Wan Kim, Ji-Hwan Hwang, Jong-Oh Kwon, SangSik Park, Tae-Hong Min, Un-Byoung Kang, Jong-Ho Lee, Ho-Geon Song, and Sa-Yoon Kang – Samsung Electronics

3. 8:50 AM - Development of Novel HighDensity System Integration Solutions in FOWLP – Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages Andre Cardoso, Alberto Martins, Hugo Barros, Elisabete Fernandes, Abel Janeiro, and Eoin O’Toole – NANIUM

3. 8:50 AM - Application of a Metallic Cap Layer to Control Cu TSV Extrusion Golareh Jalilvand, Omar Ahmed, Keenan Bosworth, Zhenlin Pei, Cullen Fitzgerald, and Tengfei Jiang – University of Central Florida

3. 8:50 AM - Improvement of C2W Collective Bonding Reliability and UPH Through Innovations in Machine, Materials, and Methods Tomonori Nakamura, Farhan Shafiq, Tetsuya Otani, Osamu Watanabe, Toru Maeda, and Yoshihito Hagiwara – SHINKAWA; Keiji Honjo, Daichi Mori, Outa Egashira, and Daisuke Handa – DEXERIALS

Mike Ma – Amkor Technology Taiwan (ATT) Tel: +886-975-778628 Email: mike.ma@amkor.com

Refreshment Break: 9:15-10:00 a.m. 4. 10:00 AM - The Analysis and Improvement of the Reliability of the Interconnection of Fan-Out Chip on Substrate Device Ying-Chih Lee – Advanced Semiconductor Engineering, Inc.

4. 10:00 AM - Development of TSV Electroplating Process for Via-Last Technology Gilho Hwang and Kalaiselvan Ravanethran – Institute of Microelectronics, A*STAR

4. 10:00 AM - Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks Pascale Gagnon, Christian Bergeron, Richard Langlois, Stéphane Barbeau, Steve Whitehead, Katsuyuki Sakuma, Raphael Robertazzi, and Christy Tyberg – IBM Corporation

5. 10:25 AM - Embedded Silicon Fan-Out: A Low-Cost Wafer Level Packaging Technology Without Molding and De-Bonding Processes Daquan Yu, Zhenrui Huang, Zhiyi Xiao, Li Yang, and Min Xiang – Huatian Technology

5. 10:25 AM - Reliability Evaluation of Copper (Cu) Through-Silicon Via (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA) Jiawei Marvin Chan and Chuan Seng Tan – Nanyang Technological University; Xu Cheng, Kheng Chooi Lee, and Werner Kanert – Infineon Technologies

5. 10:25 AM - Chip Shooter to Enable Fine Pitch Flip Chip Jie Fu, Manuel Aldrete, and Milind Shah – Qualcomm Technologies, Inc.

6. 10:50 AM - Process Development and Material Characteristics of TSV-Less Interconnection Technology for FOWLP Wen-Wei Shen, Yu-Min Lin, Sheng-Tsai Wu, HsiangHung Chang, Tao-Chih Chang, and Ang-Ying Lin – ITRI; Alvin Lee, Jay Su, and Baron Huang – Brewer Science; Kuan-Neng Chen Chen – NCTU

6. 10:50 AM - Vertical Delay Modeling of Copper/Carbon Nanotube Composites in a Tapered Through Silicon Via Madhav Rao – International Institute of Information Technology Bangalore

6. 10:50 AM - Addressing Manufacturability and Reliability Challenges for Complex FlipChip QFN Technology James Raymond Baello and Richard Sumalinog – Texas Instruments, Inc.

7. 11:15 AM - First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High-Frequency Multi-Chip Integration Tailong Shi, Vanessa Smet, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Yoichiro Sato – Asahi Glass Company; Lutz Parthier – SCHOTT; Frank Wei and Cody Lee – DISCO

7. 11:15 AM - Latency, Bandwidth and Power Benefits of the Silicon Interconnect Fabric SivaChandra Jangam, Saptadeep Pal, Adeel Bajwa, Sudhakar Pamarti, Puneet Gupta, and Subramanian Iyer – University of California, Los Angeles

7. 11:15 AM - Fine Pitch Interconnect Rework for Lead-Free Flip Chip Packages Malak Kanso, David Danovitch, and Elodie Nguena – Sherbrooke University; Richard Langlois and Christian Bergeron – IBM Corporation

15


Program Sessions: Wednesday, May 31, 8:00-11:40 a.m. Session 4: Advanced Substrates and Integrated Devices

Session 5: Emerging Sensors and Microsystems Packaging

Session 6: 5G, mmWave and Beyond

Committee: Materials & Processing

Committee: Emerging Technologies

Committee: High-Speed, Wireless & Components

Session Co-Chairs: Tieyu Zheng – Microsoft Corporation Tel: +1-425-722-1141 Email: tizheng@microsoft.com

Session Co-Chairs: Bharat Penmecha – Intel Corporation Tel: +1-480-552-2511 Email: bharat.penmecha@intel.com

Session Co-Chairs: Kemal Aygun – Intel Corporation Tel: +1-480-552-1740 Email: kemal.aygun@intel.com

Dwayne Shirley

Ramakrishna Kotlanka – Analog Devices Tel: +1-781-937-1076 Email: rama.krishna@analog.com

Lih-Tyng Hwang – National Sun Yat-Sen University Tel: +886-7-5252000 ext. 4485 Email: FiftyOhm@mail.nsysu.edu.tw

1. 8:00 AM - Novel Organic Substrates with Enhanced Thermal Conductivity Xiaoliang Zeng, Jiajia Sun, and Rong Sun – Shenzhen Institutes of Advanced Technology; Jianbin Xu and Ching-Ping Wong – Chinese University Hong Kong

1. 8:00 AM - Phototriggerable, Transient Electronics: Component and Device Fabrication Gerald Gourdin, Oluwadamilola Phillips, Jared Schwartz, Anthony Engler, and Paul Kohl – Georgia Institute of Technology

1. 8:00 AM - First Demonstration of 28GHz and 39GHz Transmission Lines and Antennas on Glass Substrates for 5G Modules Atom Watanabe, Muhammad Ali, Bijan Tehrani, Jimmy Hester, Markondeya Pulugurtha, Venky Sundaram, Manos Tentzeris, and Rao Tummala – Georgia Institute of Technology; Hiroyuki Matsuura – NGK Spark Plug; Tomonori Ogawa – Asahi Glass

2. 8:25 AM - Organic-Inorganic Hybrid Dielectrics with Improved HighTemperature Reliability Shreya Dwarakanath, Markondeya Raj Pulugurtha, Vanessa Smet, Collen Leng, Mark D. Losego, and Rao R. Tummala – Georgia Institute of Technology

2. 8:25 AM - Novel High-Temperature Capacitive Pressure Sensor Utilizing SiC Integrated Circuit Twin Ring Oscillators Philip Neudeck, David Spry, Norman Prokop, Michael Krasowski, Glenn Beheim, and Gary Hunter – NASA Glenn Research Center

2. 8:25 AM - Integrated Antenna-in-Package on Low-Cost Organic Substrate for 60 GHz Wireless Communication Applications Cheng-Yu Ho, Ming-Fong Jhong, Po-Chih Pan, ChenChao Wang, Chun-Yen Ting, and Chih-Yi Huang – Advanced Semiconductor Engineering, Inc.

3. 8:50 AM - Development of Solder Resist with Improved Adhesion at HTSL (175°C for 3000 Hours) for Automotive IC Package Nobuhito Itoh – Taiyo Ink

3. 8:50 AM - Atomically Thin Vertical van der Waals Heterostructure for Broadband Photodetection Bo Sun, Tielin Shi, Youni Wu, Jianxin Zhou, Zirong Tang, and Guanglan Liao – Huazhong University of Science & Technology

3. 8:50 AM - Fabrication of Terahertz Components using Aerosol-Jet Printing Christopher Oakley, Amanpreet Kaur, Jennifer Byford, and Premjeet Chahal – Michigan State University

Refreshment Break: 9:15-10:00 a.m.

16

4. 10:00 AM - Bondable Copper Substrates with Silver Solid Solution Coating for HighPower Electronic Applications Yongjun Huo and Chin C. Lee – University of California, Irvine

4. 10:00 AM - Fractal-Structured, Wearable Soft Sensors for Control of a Robotic Wheelchair via Electrooculograms Saswat Mishra, Nicolas Agee, Yongkuk Lee, Dong Sup Lee, and Woon-Hong Yeo – Virginia Commonwealth University; James J. S. Norton – University of Illinois at Urbana-Champaign

4. 10:00 AM – High-Performance ChipPartitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL Che-Wei Hsu, Chung-Hao Tsai, Jeng-Shien Hsieh, Kuo-Chung Yee, Chuei-Tang Wang, and Douglas Yu – Taiwan Semiconductor Manufacturing Company, Ltd.

5. 10:25 AM - On-Chip Solid-State MicroSupercapacitor Muhammad Amin Saleem, Rickard Andersson, and Vincent Desmaris – Smoltek; Bo Song and C. P. Wong – Georgia Institute of Technology

5. 10:25 AM - Micro-Hermetic Packaging Technology for Active Implantable Neural Interfaces Kaustubh Nagarkar, Nancy Stoffel, Eric Davis, and Jeffrey Ashe – GE Global Research; Xiaoxiao Hou and David Borton – Brown University

5. 10:25 AM - Directional Through Glass Via (TGV) Antennas for Wireless Point-toPoint Interconnects in 3D Integration and Packaging Seahee Hwangbo, Hyowon An, Sheng-Po Fang, and Yong-Kyu Yoon – University of Florida; Aric B. Shorey and Abbas M. Kazmi – Corning, Inc.

6. 10:50 AM - Development of CPU Package Embedded with Multi-Layer Thin Film Capacitor for Stabilization of Power Supply Tomoyuki Akahoshi, Daisuke Mizutani, Kei Fukui, Seigo Yamawaki, Hidehiko Fujisaki, Manabu Watanabe, and Masateru Koide – Fujitsu Semiconductor

6. 10:50 AM - Biopackaging of Minimally Invasive Ultrasound Assisted Clot Lysis Device for Stroke Treatment Ramona Damalerio, Ming-Yuan Cheng, Weiguo Chen, Liang Lou, and Songsong Zhang – Institute of Microelectronics, A*STAR

6. 10:50 AM - High Gain mmW Patch Antenna Array on Fanout Structure Jyun-Yuan Jhang, Sam Lin, Ying-Wei Lu, Ming-Fan Tsai, and Mike Ma – Siliconware Precision Industries Co., Ltd.

7. 11:15 AM - Panel-Based Integrated Passive Device for RF Application Ming Hung Chen, Tze Hsin Chiang, Jia Hao Zhang, Hsu Chiang Shih, Sheng Chi Hsieh, Teck Chong Lee, and Chih Pin Hung – Advanced Semiconductor Engineering, Inc.

7. 11:15 AM - A Low-Profile Flow Sensing System for Monitoring of Cerebrospinal Fluid with a New Ventriculoamniotic Shunt Yanfei Chen, Stephanie Greene, Puneeth Shridhar, and Youngjae Chun – University of Pittsburgh; Connor Howe and Woon-Hong Yeo – Virginia Commonwealth University; Emery Stephen – MageeWomens Hospital of UPMC

7. 11:15 AM - Miniature 2.4-GHz Switched Beamformer Module in IPD and Its Application to Very-Low-Profile 1D and 2D Scanning Antenna Arrays Chia-Hao Chen, Wei-Ting Fang, and Yo-Shen Lin – National Central University


Program Sessions: Wednesday, May 31, 1:30-5:10 p.m. Session 7: Fan-Out Packaging Materials and Passives

Session 8: Singulation Process Developments

Session 9: Fine Pitch Flip Chip Process Technologies

Committee: Advanced Packaging

Committee: Assembly & Manufacturing Technology

Committee: Interconnections

Session Co-Chairs: Luke England – GLOBALFOUNDRIES Tel: +1-518-222-1860 Email: luke.england@globalfoundries.com

Session Co-Chairs: Garry Cunningham – Northrop Grumman Corporation Tel: +1-410-765-7859 Email: Garry.Cunningham@ngc.com

Session Co-Chairs: David Danovitch – University of Sherbrooke Tel: +1-450-534-8000 X-1400 Email: David.Danovitch@USherbrooke.ca

Bora Baloglu – Amkor Technology Tel: +1-480-786-7307 Email: bora.baloglu@amkor.com

Li Jiang – Texas Instruments, Inc. Tel: +1-214-479-4537 Email: l-jiang1@ti.com

Li Li – Cisco Systems, Inc. Tel: +1-408-527-0801 Email: LiLi2@cisco.com

1. 1:30 PM - A Novel Multi-Layer Film Type Interconnection Substrate Chih-Kuang Yang – Princo Corporation

1. 1:30 PM - Development of Low Power Stealth Laser for Thick Die As A Solution for Protective Overcoat Damage Jeniffer Aspuria, Jessa Resol, and Roderick Balares – Texas Instruments, Inc.

1. 1:30 PM - Cu-SnAg Interconnects Evaluation for the Assembly at 10µm and 5µm Pitch Divya Taneja, Marion Volpert, Gilles Lasfargues, Boris Bouillard, Aurelie Vandeneynde, Tarik Chaira, Yannick Goiran, and David Henry – CEA-Leti; Fiqiri Hodaj – University Grenople Alps, SIMaP Laboratory

2. 1:55 PM - Ultra-Low Temperature FOWLP Process for the Embedding of Low Thermal Budget Sensors and Components Using SU-8 as Dielectric Raquel Pinto, André Cardoso, Sara Ribeiro, and Carlos Brandão – NANIUM; João Gaspar, Rizwan Gill, Helder Fonseca, and Margaret Costa – INL; Filipe Cardoso and Mariana Antunes – MAGNOMICS

2. 1:55 PM - Laser Multi Beam Full Cut Dicing of Wafer Level Chip-Scale Packages Jeroen van Borkulo, Eric Tan, and Richard van der Stam – ASM Pacific Technologies

2. 1:55 PM - Scaling Cu Pillars to 20µm Pitch and Below: Strategic Role of Surface Finish and Barrier Layers Ting-Chia Huang, Vanessa Smet, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Robin Taylor, Gustavo Ramos, Rick Nichols, and Arnd Kilian – Atotech

3. 2:20 PM - Integrated Copper Heat Slugs and EMI Shields in Panel Laminate Fanout (LFO) and Glass Fanout (GFO) Packages for High-Power RF ICs Venky Sundaram, Bartlet Deprospo, Nahid Gezgin, P. Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Kyle Byers and Sean Garrison – Honeywell; Garth Kraus and Michael Elsbury – Sandia National Laboratories

3. 2:20 PM - Plasma Dicing 300mm Framed Wafers - Analysis of Improvement in Die Strength and Cost Benefits for Thin Die Singulation Richard Barnett, Oliver Ansell, Martin Hanicinec, Janet Hopkins, Joanne Carpenter, William Worster, and Carolyn Short – SPTS Technologies

3. 2:20 PM - Thermal Compression Bonding: Understanding Heat Transfer by in situ Measurement and Modeling Pieter Bex, Teng Wang, Vladimir Cherman, Melina Lofrano, Giovanni Capuz, Erik Sleeckx, and Eric Beyne – IMEC

Refreshment Break: 2:45-3:30 p.m. 4. 3:30 PM - Implementation of Thick Copper Inductor Integrated into Chip Scaled Package Sheng-Bin Yang, C. C. Chen, W. L. Huang, T. L. Yang, C. L. Chang, H.L. Huang, C. C. Chou, C. Y. Ku, C. S. Chen, and Alexander Kalnitsky – Taiwan Semiconductor Manufacturing Company, Ltd.

4. 3:30 PM - Plasma Dicing Fully Integrated Process-Flows Suitable for BEOL Advanced Packaging Fabrications Frank Wei and Tomotaka Tabuchi – Disco Corporation; Thierry Lazerand, Christopher Johnston, Kenneth Mackenzie, and Marco Notarianni – PlasmaTherm, LLC

4. 3:30 PM - A Study on Nano-sized Silica Content and Size Effect in Non Conductive Films (NCFs) for Ultra Fine-Pitch Cu-Pillar/ Sn-Ag Micro-Bump Interconnection HanMin Lee, SeYong Lee, SeMin Cho, YoungHyun Yu, Jong-Ho Park, and Kyung-Wook Paik – Korea Advanced Institute of Science & Technology

5. 3:55 PM - Passive Devices Fabrication on FOWLP and Characterization for RF Applications Chunmei Wang – Institute of Microelectronics, A*STAR

5. 3:55 PM - Stealth Dicing Challenges for MEMS Wafer Applications Ismael Daniel and Sunil Wickramanayaka – Institute of Microelectronics, A*STAR

5. 3:55 PM - Accelerated SLID Bonding for Fine-Pitch Interconnects with Porous Microstructure Jörg Meyer, Iuliana Panchenko, and Steffen Bickel – Technical University Dresden; Wieland Wahrmund and M. Jürgen Wolf – Fraunhofer IZM, ASSID

6. 4:20 PM - Organic versus Inorganic RDL Dielectrics for High-Performance Graphics Applications Curtis Zwenger, WonChul Do, WonGeol Lee, JiHun Yi, WonMyoung Ki, and Mike Kelly – Amkor Technology

6. 4:20 PM - A Novel Pick-Up and Place Process for FOWLP Using Tape Expansion Machine Device Shinya Takyu, Naoya Okamoto, Tadatomo Yamada, Toshiaki Menjo, and Masatomo Nakamura – LINTEC Corporation

6. 4:20 PM – Low-Temperature Ni/Sn/Ni Transient Liquid Phase Bonding for High Temperature Packaging Application by Imposing Temperature Gradient Yi Zhong, Wei Dong, Mingliang Huang, Haitao Ma, and Ning Zhao – Dalian University of Technology; C. P. Wong – Georgia Institute of Technology

7. 4:45 PM - Additive Manufacturing of Magnetic Components for Heterogenous Integration Yi Yan, Lanbing Liu, and Guo-Quan Lu – Virginia Tech; Luu Nguyen and Jim Moss – Texas Instruments, Inc.; Yunhui Mei – Tianjin University

7. 4:45 PM - Investigation of Production Quality and Reliability Risk of ELK Wafer WLCSP Package Pei-Haw Tsao, T.M. Chen, Y. L. Kuo, C. M. Kuo, Steven Hsu, M. J. Lii, and L. H. Chu – Taiwan Semiconductor Manufacturing Company, Ltd.

7. 4:45 PM - Interfacial Reaction and Microstructural Evolution Between Au-Ge Solder and Electroless Ni-W-P Metallisation in High-Temperature Electronics Interconnects Li Liu – Wuhan University of Technology; Jinzi Cui – Auburn University; Jing Wang, Zhaoxia Zhou, and Changqing Liu – Loughborough University; R. Wayne Johnson – Tennessee Tech University

17


Program Sessions: Wednesday, May 31, 1:30-5:10 p.m. Session 10: Harsh Environment Interconnect Reliability

Session 11: Mechanical Modeling and Characterization of Interposers and Interconnections

Session 12: Advanced Optical Components and Modules

Committee: Applied Reliability

Committee: Thermal/Mechanical Simulation & Characterization

Committee: Optoelectronics

Session Co-Chairs: Tim Chaudhry – Amkor Technology, Inc. Tel: +1-949-324-0512 Email: timchaudhry@gmail.com

Session Co-Chairs: Kuo-Ning Chiang – National Tsinghua University Tel: +886-3-574-2925 Email: knchiang@pme.nthu.edu.tw

Session Co-Chairs: Stephane Bernabe – CEA-Leti Tel: +33 4 38 78 05 10 Email: stephane.bernabe@cea.fr

René Rongen – NXP Semiconductors Tel: +31-(0)6-51171461 Email: rene.rongen@nxp.com

Tony Mak – Wentworth Institute of Technology Tel: +1-334-625-8669 Email: t.mak@ieee.org

Shogo Ura – Kyoto Institute of Technology Tel: +81-75-724-7424 Email: ura@kit.ac.jp

1. 1:30 PM - Effect of Processing Variables on the Mechanical Reliability of SnAg/Cu Pillar Solder Joints Mohammed Genanu, Babak Arfaei, and Eric Cotts – Binghamton University; Francis Mutuku and James Wilcox – Universal Instruments; Eric Perfecto – GLOBALFOUNDRIES

1. 1:30 PM - Hybrid Approach to Conduct Failure Prognostics of Automotive Electronic Control Unit Bulong Wu, Dae-Suk Kim, and Bongtae Han – University of Maryland; Alicja Palczynska, Przemyslaw Jakub Gromala, and Alexandru Prisacaru – Robert Bosch

1. 1:30 PM - Thermal Isolation of Photonic Components by Vacuum Gap Technology Rahel Straessle, Antonio La Porta, and Thomas Brunschwiler – IBM Corporation

2. 1:55 PM - Visualization of Microstructural Evolution in Lead-Free Solders During Isothermal Aging Using TimeLapse Imagery Sudan Ahmed, Nianjun Fu, Jeffrey Suhling, and Pradeep Lall – Auburn University

2. 1:55 PM - Semiconductor Power Package Bonding Interconnects Reliability Simulation under Transient Thermal Loads Richard Qian, Aditi Mallik, Roger Stout, and Yong Liu – ON Semiconductor

2. 1:55 PM - A Very High-Density On-Board Optical Module Realizing >1.3 Tb/s/inch² Kazuya Nagashima, Toshinori Uemura, Atsushi Izawa, Yozo Ishikawa, and Hideyuki Nasu – Furukawa Electric

3. 2:20 PM - Failure Mechanism and Kinetics Studies of Electroless Ni-P Dissolution in Pb-Free Solder Joints under Electromigration Pilin Liu, Alan Overson, Chaitra Chavali, and Deepak Goyal – Intel Corporation

3. 2:20 PM - Correlation of Dielectric Film Flex Fatigue Resistance and Package Resin Cracking Failure Joseph Ross, Nicolas Pizzuti, Steven Ostrander, and Kamal Sikka – IBM Corporation

3. 2:20 PM - Design and Demonstration of a Photonic Integrated Glass Interposer for Mid-Board-Optical Engines Marcel Neitz and Sebastian Marx – Technical University Berlin; Markus Wöhrmann and Henning Schröder – Fraunhofer IZM; Ruiyong Zhang and Mohamed Fikry – Amphenol FCI

Refreshment Break: 2:45-3:30 p.m.

18

4. 3:30 PM - Experimental Evaluation of the Adequacy of Accelerated High Temperature Testing for ECUs Qualification in Electromobility Abdalla Youssef and Ingo Birner – BMW; Andreas Middendorf and Klaus-Dieter Lang – Fraunhofer Institute for Reliability and Microintegration

4. 3:30 PM - Development of FE Models and Measurement of Internal Deformations of Fuze Electronics Using X-Ray MicroCT Data with Digital Volume Correlation Pradeep Lall and Nakul Kothari – Auburn University; John Deep and Jason Foley – US Air Force Research Labs; Ryan Lowe – ARA Associates

4. 3:30 PM - Optoelectronic Chip Assembly Process of Optical MCM Masao Tokunari, Koji Masuda, Hsiang-Han Hsu, Takashi Hisada, Shigeru Nakagawa, Richard Langlois, Patrick Jacques, and Paul Fortier – IBM Corporation

5. 3:55 PM - Road Test and Reliability Analysis of Electronic Modules Used in Automobiles Dongji Xie, Joe Hai, Jack Huang, and Manthos Economou – Nvidia Corporation

5. 3:55 PM - Dynamic Stress Measurements of Electronic Devices During Active Operation Markus Feisst, Eike Moeller, Andi Wijaya, and Juergen Wilde – University of Freiburg, IMTEK; Johanna Ocklenburg – Infineon Technologies

5. 3:55 PM - 3D Packaging of Embedded Optoelectronic Die and CMOS IC Based on Wet Etched Silicon Interposer Chenhui Li, Barry Smalbrugge, Teng Li, Ripalta Stabile, and Oded Raz – Eindhoven University of Technology

6. 4:20 PM - Effects of the Inter-Metallic Compounds Microstructure on ElectroMigration of Sn-Bi Solder System kei Murayama, Mitsuhiro Aizawa, and Takashi Kurihara – Shinko Electric

6. 4:20 PM - Smart Packaging: A MicroSensor Array Integrated to a Flip-Chip Package to Investigate the Effect of Humidity in Microelectronic Packages Aurore Quelennec, Umar Shafique, and Dominique Drouin – Université de Sherbrooke; Éric Duchesne – IBM Corporation; Hélène Frémont – Université de Bordeaux

6. 4:20 PM - Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicron Accuracy Yézouma Dieudonné Zonou, Stéphane Bernabe, and Olivier Castany – CEA-Leti; Philippe Arguel – Laboratory for Analysis and Architecture of Systems, CNRS

7. 4:45 PM - Effect of Board and Package Type on Board Level Vibration using Vibrational Spectrum Analysis Jeroen Jalink, Romuald Roucou, Jeroen Zaal, Joachim Lesventes, and Rene Rongen – NXP Semiconductors

7. 4:45 PM - Nondestructive, In Situ Mapping of Die Surface Displacements in Encapsulated IC Chip Packages using X-Ray Diffraction Imaging Techniques Nima E. Gorji, Rajani K. Vijayaraghavan, and Patrick J. McNally – Dublin City University; Brian K. Tanner – Durham University; Andreas N. Danilewsky – Albert Ludwigs University

7. 4:45 PM - Thermal Management Characterization of Microassemblied HighPower Distributed-Feedback Broad Area Lasers Emitting at 975nm Roberto Mostallino, Michel Garcia, Alexandre Larrue, Yannick Robert, Eric Vinet, Michel Lecomte, Olivier Parillaud, and Michel Krakowski – III-V Lab; Yannick Deshayes and Laurent Bechou – University of Bordeaux


Program Sessions: Thursday, June 1, 8:00-11:40 a.m. Session 13: Interconnect Advances in FO & WLP

Session 14: Heterogeneous Integration

Session 15: Flip Chip and Embedding in Substrates

Committee: Interconnections

Committees: Advanced Packaging joint with Assembly & Manufacturing Technology

Committee: Advanced Packaging

Session Co-Chairs: Lei Shan – IBM Corporation Tel: +1-914-945-2304 Email: leis@us.ibm.com

Session Co-Chairs: John Knickerbocker – IBM Corporation Tel: +1-914-945-3306 Email: knickerj@us.ibm.com

Session Co-Chairs: Markus Leitgeb – AT&S Tel: +43-676-8955-4087 Email: m.leitgeb@ats.net

Dingyou Zhang – Qualcomm Technologies, Inc. Tel: +1-858-845-5905 Email: zhangdingyou04@gmail.com

Chunho Kim – Medtronic Corporation Tel: +1-480-377-3664 Email: chunho.kim@medtronic.com

Steffen Kroehnert – Nanium S.A. Tel: +49-171-5639472 Email: steffen.kroehnert@nanium.com

1. 8:00 AM - SLIM™ Advanced Fan-Out Packaging for High Performance Multi-Die Solutions Young Rae Kim and Won Chul Do – Amkor Technololgy

1. 8:00 AM - A Versatile Platform Towards High Reliability Compact Package for Digital Chips Christine Ferrandon, Laetitia Castagné, Brahim Kholti, Guillaume Waltener, Vincent Puyal, Romain Lemaire, Fabrice Casset, Gilles Simon, and Jean-Charles Souriau – CEA-Leti; Lionel Toffanin and Sébastien Petitdidier – ST Microelectronics

1. 8:00 AM - Solder Mobility for High-Yield Self-Aligned Flip-Chip Assembly Yves Martin, Swetha Kamlapurkar, Jae-Woong Nah, Nathan Marchack, and Tymon Barwicz – IBM Corporation

2. 8:25 AM - 28nm CPI (Chip/Package Interactions) in Large Size eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages Yaojian Lin – STATS ChipPAC

2. 8:25 AM - Glass Based 3D-IPD Integrated RF ASIC in WLCSP Teck Chong Lee, Yung-shun Chang, Sheng-Chi Hsieh, Pao-Nan Lee, and Yu-Chang Hsieh – Advanced Semiconductor Engineering, Inc.; Long-Ching Wang – Marvell Semiconductor

2. 8:25 AM - Large Scale Cryogenic Integration Approach for Superconducting High-Performance Computing Rabindra Das, Vladimir Bolkhovsky, Sergey Tolpygo, Pascale Gouker, Leonard Johnson, Eric Dauler, and Mark Gouker – MIT Lincoln Laboratory

3. 8:50 AM - Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array Rey Alvarado, Beth Keser, Tong Cui, and Ahmer Syed – Qualcomm Technologies, Inc.

3. 8:50 AM - Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration Yu-Tao Yang, Ting-Yang Yu, Shu-Chiao Kuo, and Kuan-Neng Chen – National Chiao Tung University; Tai-Yuan Huang, Kai-Ming Yang, Cheng-Ta Ko, Yu-Hua Chen, and Tzyy-Jang Tseng – Unimicron

3. 8:50 AM - Compressible MicroInterconnects (CMIs) for Heterogeneous Microsystem Integration Paul Jo, Muneeb Zia, Joe Gonzalez, and Muhannad Bakir – Georgia Institute of Technology

Refreshment Break: 9:15-10:00 a.m. 4. 10:00 AM - Warpage and Thermal Optimization of Fan-Out Wafer/Panel-Level Packaging John Lau, Ming Li, DeWen Tian, Nelson Fan, Eric Kuah, and Eric Ng – ASM International; Zhang Li and Kim Hwee Tan – Jiangyin Changdian Advanced Packaging Co., Ltd.; Rozalia Beica – Dow Chemical; Yu-Hua Chen – Unimicron

4. 10:00 AM - Heterogeneous Interposer Based Integration of Chips with Copper Pillars and C4 Balls to Achieve High-Speed Interfaces for ADC Application Andy Heinig, Fabina Hopsch, Robert Fischbach, Michael Dittrich, and Robert Trieb – Fraunhofer IIS/ EAS

4. 10:00 AM - Package Design Considerations and Coupling from Embedded Passive Inductors Jian Liu, Janani Chandrasekhar, Andrew Collins, Hui Liu, and Guang Chen – Intel Corporation

5. 10:25 AM - A Novel 3D IC Wafer-level Package for New Wave MEMS Uwe Hansen, Ralf Reichenbach, David Polityko, and Sebastian Schuler-Watkins – Robert Bosch; Che-Hau Huang, Yung-Hui Wang, and Ying-Te Ou – Advanced Semiconductor Engineering, Inc.

5. 10:25 AM - “FlexTrate®” - Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Tak Fukushima, Arsalan Alam, Saptadeep Pal, Zhe Wan, Siva Jangam, Goutham Ezhilarasu, Adeel Bajwa, and Subramanian Iyer – University of California, Los Angeles

5. 10:25 AM - Advanced Embedded Package for Power Devices Naoki Hayashi, Miki Nakashima, Hiroaki Matsubara, Hiroshi Demachi, Shingo Nakamura, Tomoshige Chikai, Fumihiko Taniguchi, Yukari Imaizumi, Yoshihiko Ikemoto, Mitsuru Ooida, and Akito Yoshida – J-Devices

6. 10:50 AM - UBM/RDL Deposition by PVD for FOWLP in High-Volume Production Chris Jones, Stephen Burgess, Tony WIlby, Paul Densley, David Butler, and Carolyn Short – SPTS Technologies

6. 10:50 AM - Metal Contamination Evaluation of Via-Last Cu TSV Process Using Notchless Si Etching and Wet Cleaning of the First Metal Layer Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, and Masahiro Aoyagi – AIST; Hidekazu Kikuchi, Azusa Yanagisawa, and Akio Nakamura – LAPIS Semiconductor

6. 10:50 AM - Development of Large Size CPU Package Structure using Embedded Thin Film Capacitor Package Substrate Masateru Koide, Kenji Fukuzono, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi, Hedehiko Fujisaki, Seigo Yamawaki, and Kei Fukui – Fujitsu Semiconductor

7. 11:15 AM - Reliability of Large Fan-Out Wafer Level Package Based Package-onPackage Srinivasa Rao Vempati, David Ho, Mian Zhi Ding, Ser Choong Chong, Sharon Lim PS, and Tai Chong Chai – Institute of Microelectronics, A*STAR

7. 11:15 AM - A Highly Miniaturized System Integration Approach for an IOT Contactless Power Module Srikrishna Sitaraman, Tony Contreras, Jian Wang, Mingjie Fan, Minjie Chen, Yuming Song, and Terry Bowen – Tyco Electronics

7. 11:15 AM - Laminate Chip Embedding Technology - Impact of Material Choice and Processing for Very Thin Die Packaging Angela Kessler, Andreas Munding, Thorsten Scharf, Boris Plikat, and Klaus Pressel – Infineon Technologies

19


Program Sessions: Thursday, June 1, 8:00-11:40 a.m. Session 16: 3D Materials and Processing

Session 17: Materials and Processes for Flexible and Wearable Devices

Session 18: Warpage, Electromigration and Mechanical Characterization

Committee: Materials & Processing

Committee: Emerging Technologies

Committee: Thermal/Mechanical Simulation & Characterization

Session Co-Chairs: Myung Jin Yim – Intel Corporation Tel: +1-408-728-1393 Email: myungjin.yim@intel.com

Session Co-Chairs: C. S. Premachandran – GLOBALFOUNDRIES Tel: +1-518-305-7317 Email: premachandran.cs@globalfoundries.com

Session Co-Chairs: Xuejun Fan – Lamar University Tel: +1-409-880-7792 Email: xuejun.fan@lamar.edu

Mikel Miller – Draper Laboratory Tel: +1-617-258-2844 Email: mrmiller@draper.com

Ankur Agrawal – Intel Corporation Tel: +1-480-516-2959 Email: ankur.agrawal@intel.com

Jiantao Zheng – Qualcomm Technologies, Inc. Tel: +1-858-658-5738 Email: jiantaoz@qti.qualcomm.com

1. 8:00 AM - Highly Productive 3D Stacking Process Kazutaka Honda, Hitoshi Onozeki, and Shizu Fukuzumi – Hitachi Chemical

1. 8:00 AM - Nanoparticle Based Printed Sensors on Paper for Detecting Chemical and Biological Species Jack Lombardi, Mark Poliks, Ning Kang, Shan Yan, Jing Li, Wei Zhao, Shiyao Shan, Jin Luo, and Chuan-Jian Zhong – Binghamton University; Benjamin Hsiao – Stony Brook University

1. 8:00 AM - Model for Interaction of EMC Formulation with the High Current Reliability of Cu-Al Wirebonds Operating in Harsh Environments Pradeep Lall, Shantanu Deshpande, and Yihua Luo – Auburn University; Luu Nguyen – Texas Instruments, Inc.

2. 8:25 AM - Direct Bonding and Debonding Approach of Ultrathin Glass Substrates for High-Temperature Devices Messaoud Bedjaoui and Sylvain Poulet – CEA-Leti

2. 8:25 AM - Phototriggerable Transient Electronics: Materials and Concepts Oluwadamilola Phillips, Jared Schwartz, Anthony Engler, Gerald Gourdin, and Paul Kohl – Georgia Institute of Technology

2. 8:25 AM - Fan-Out Packages with HighTemperature Mold Compounds Shreya Dwarakanath, P. Markondeya Raj, Scott McCann, Jose Soler, Vanessa Smet, Rao Tummala, and Suresh Sitaraman – Georgia Institute of Technology

3. 8:50 AM - Wafer-Level Vacuum-Packaged Piezoelectric Energy Harvesters Utilizing Two-Step Three-Wafer Bonding Nan Wang, Chengliang Sun, Li Yan Siow, Hong Miao Ji, Darmayuda I Made, Peter Hyun Kee Chang, Qing Xin Zhang, and Yuandong Gu – Institute of Microelectronics, A*STAR

3. 8:50 AM - Synthesis of a Soft Nanocomposite for Flexible, Wearable Bioelectronics Fabrice Fondjo and Jong-Hoon Kim – Washington State University; Michael Teller, Connor Howe, and Woon-Hong Yeo – Virginia Commonwealth University

3. 8:50 AM - Non-Linear Viscoelastic Modeling of Epoxy Based Molding Compound for Large Deformations Encountered in Power Modules Przemyslaw Gromala – Robert Bosch GmbH; HyunSeop Lee and Bongtae Han – University of Maryland

Refreshment Break: 9:15-10:00 a.m.

20

4. 10:00 AM - Advances in Thin Wafer Debonding and Ultrathin 28-nm FinFET Substrate Transfer Alain Phommahaxay, Anne Jourdain, Goedele Potoms, Greet Verbinnen, Erik Sleeckx, and Eric Beyne – IMEC; Alice Guerrero, Dongshun Bai, Kim Yess, and Kim Arnold – Brewer Science

4. 10:00 AM - BiCMOS Integrated Microfluidic Packaging by Wafer Bonding for Lab-on-Chip Applications Mesut Inac – Technical University Berlin; Matthias Wietstruck, Alexander Göritz, Barbaros Cetindogan, Canan Baristiran-Kaynak, Steffen Marschmeyer, Mirko Fraschke, Thomas Voss, Andreas Mai, and Mehmet Kaynak – IHP Microelectronics

4. 10:00 AM - Warpage Modeling and Characterization of the Viscoelastic Relaxation for Cured Molding Process in Fan-Out Packages Shu-Shen Yeh, Po-Yao Lin, Kuang-Chun Lee, JinHua Wang, Wen-Yi Lin, Ming-Chih Yew, Po-Chen Lai, Shyue-Ter Leu, and Shin-Puu Jeng – Taiwan Semiconductor Manufacturing Company, Ltd.

5. 10:25 AM - Thermally Reversible and Crosslinked Polyurethane based on DielsAlder Chemistry for Ultrathin Wafer Temporary Bonding at Low-Temperature Jinhui Li, Qiang Liu, Guoping Zhang, and Rong Sun – Shenzhen Institutes of Advanced Technology; Chingping Wong – Chinese University of Hong Kong

5. 10:25 AM - Enhanced Thermal Performance Polyimide (PI) for Improved Flexible Electronic Application Manuela Loeblein, Siu Hon Tsang, and Edwin Hang Tong Teo – Nanyang Technological University

5. 10:25 AM - Wafer Form Warpage Characterization Based on Composite Factors Including Passivation Films, Re-Distribution Layers, Epoxy Molding Compound Utilized in Innovative Fan-Out Package Cheng-Hsiang Liu, Lu-Yi Chen, Chang-Lun Lu, HungChi Chen, Cheng-Yi Chen, and Shou-Chi Chang – Siliconware Precision Industries Co., Ltd.

6. 10:50 AM - Synchrotron X-ray Microdiffraction Investigation of Scaling Effects on Plasticity and the Correlation to TSV Extrusion Laura Spinella, Jang-hi Im, and Paul Ho – University of Texas, Austin; Tengfei Jiang – University of Central Florida

6. 10:50 AM - Nanolaminated CoNiFe Cores with Dip-Coated Fluoroacrylic Polymer Interlamination Insulation: Fabrication, Electrical Characterization, and Performance Reliability Minsoo Kim and Mark Allen – University of Pennsylvania; Jooncheol Kim – Georgia Institute of Technology

6. 10:50 AM - Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI) Faxing Che, Masaya Kawano, M. Z. Ding, Yong Han, and S. Bhattacharya – Institute of Microelectronics, A*STAR

7. 11:15 AM - Development of HighFrequency Device using Glass or Fused Silica with 3D Integration Yoichiro Sato, Kohei Horiuchi, and Motoshi Ono – Asahi Glass

7. 11:15 AM – Test Protocol for Assessment of Flexible Power Sources in Foldable Wearable Electronics Under Stresses of Daily Motion During Operation Pradeep Lall and Hao Zhang – Auburn University

7. 11:15 AM - Finite Elements for Electromigration Analysis Elena Antonova and David Looman – Ansys, Inc.


Program Sessions: Thursday, June 1, 1:30-5:10 p.m. Session 19: Recent Advances in FOWLP Technology

Session 20: MEMS and Sensor Technologies

Session 21: 3D Cu-Cu and Micro Bump Bonding Technologies

Committee: Materials & Processing

Committee: Advanced Packaging

Committee: Interconnections

Session Co-Chairs: Praveen Pandojirao – Johnson & Johnson Tel: +1-904-443-1691 Email: praveen@its.jnj.com

Session Co-Chairs: Joseph W. Soucy – Draper Laboratory Tel: +1-617-258-2953 Email: jsoucy@draper.com

Session Co-Chairs: Katsuyuki Sakuma – IBM Corporation Tel: +1-914-945-2080 Email: ksakuma@us.ibm.com

Yi Li – Intel Corporation Tel: +1-480-554-1657 Email: yi.li@intel.com

Allyson Hartzell – Veryst Engineering Tel: +1-781-433-0433 x330 Email: AHartzell@veryst.com

Ho-Young Son – SK Hynix Tel: +82-31-630-2858 Email: hoyoung.son@sk.com

1. 1:30 PM - Innovative Excimer Laser Dual Damascene Process for Ultra-Fine Line MultiLayer Routing with 10µm Pitch Micro-Vias for Wafer-Level and Panel-Level Packaging Markus Woehrmann, Robert Gernhardt, Karin Hauck, and Michael Toepper – Fraunhofer IZM; Habib Hichri and Markus Arendt – Suss MicroTec; Klaus-Dieter Lang – Technical University Berlin

1. 1:30 PM - Fabrication of 3D Hybrid Pixel Detector Modules based on TSV Processing and Advanced Flip Chip Assembly of Thin Read Out Chips Kai Zoschke, Hermann Oppermann, Thomas Fritzsch, Mario Rothermund, and Ulf Oestermann – Fraunhofer IZM; Pawel Grybos, Krzysztof Kasiski, Piotr Maj, and Robert Szczygiel – AGH University of Science and Technology; Steve Voges – Technical University Berlin

1. 1:30 PM - Morphology Study of BimodalParticle-Based All-Copper Interconnects Formed at Low Sintering Temperature Luca Del Carro, Jonas Zuercher, and Thomas Brunschwiler – IBM Corporation; Tom Wildsmith – Intrinsiq Materials; Gustavo Ramos – Atotech

2. 1:55 PM - Forming a Vertical Interconnect Structure using Dry Film Processing for FanOut Wafer Level Packaging Yew Wing Leong, Hsiang-Yao Hsiao, David Soon Wee Ho, Boon Long Lau, and Huamao Lin – Institute of Microelectronics, A*STAR

2. 1:55 PM - A Novel Technology for Creating Sensors and Actuators in Processor Packages Feras Eid, Qing Ma, Sasha Oster, Georgios Dogiamis, Thomas Sounart, and Johanna Swan – Intel Corporation

2. 1:55 PM - Enabling Chip-To-Package Cu-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding Ninad Shahane, Kashyap Mohan, Antonia Antoniou, Pulugurtha Raj Markondeya, Vanessa Smet, and Rao Tummala – Georgia Institute of Technology; Gustavo Ramos, Arnd Kilian, and Robin Taylor – Atotech; Frank Wei – Disco Corporation

3. 2:20 PM - Embedded Trace RDL at 2-5µm Width and Space by Excimer Laser, Cu Filling and Surface Planarization for 20-40µm Pitch Interposers Habib Hichri, Markus Arendt, and Lee Seongkuk – Suss MicroTec; Rao Tummala and Venky Sundaram – Georgia Institute of Technology; Frank Wei, Ye Chen, and Cody Lee – Disco; Ognian Dimov, Deepak Arora, and Sanjay Malik – Fujifilm

3. 2:20 PM - Stress Compensating MEMS Sensor Assembly Harald Etschmaier, Anderson Singulani, and Coen Tak – ams AG; Kai Zoschke, Hermann Oppermann, and Danny Jaeger – Fraunhofer IZM

3. 2:20 PM - Low-Temperature and Low-Pressure Cu-Cu Bonding by Pure Cu Nanosolder Paste for Wafer-Level Packaging Junjie Li, Tielin Shi, Xing Yu, Chaoliang Cheng, Jinhu Fan, Guanglan Liao, and Zirong Tang – Huazhong University of Science and Technology

Refreshment Break: 2:45-3:30 p.m. 4. 3:30 PM - Temporary Bonding and Debonding Technologies for Fan-Out Wafer-Level Packaging Qi Wu, Xiao Liu, Kuo Han, Dongshun Bai, and Tony Flaim – Brewer Science

4. 3:30 PM - 3D Monolithic Metal Orifice Plating for Low-Cost MEMS Packaging Ning Ge, Steven Simske, Jarrid Wittkopf, Kevin Dooley, Anita Rogacs, and Helen Holder – Hewlett Packard

4. 3:30 PM - Dual Damascene Compatible, Copper Rich Alloy Based Surface Passivation Mechanism for Achieving Cu-Cu Bonding at 150°C for 3D IC Integration Asisa Kumar Panigrahi, Tamal Ghosh, Siva Rama Krishna Vanjari, and Shiv Govind Singh – Indian Institute of Technology, Hyderabad

5. 3:55 PM - Development and Evaluation of Carrier Glass Substrate for Fan-Out WLP/ PLP Process Kazutaka Hayashi, Shigeki Sawamura, Yu Hanawa, Shuhei Nomura, and Jun Endo – Asahi Glass Co.; Naoya Suzuki and Masaaki Takekoshi – Hitachi Chemical

5. 3:55 PM - A Phase Sensitive Measurement Technique for Fast Recovery of Graphene FET Gas Sensors Yumeng Liu, Takeshi Hayasaka, Yong Cui, Xiaoqian Li, Kaiming Hu, and Liwei Lin – UC Berkeley, BSAC; Vaishno Dasika and Luu Nguyen – Texas Instruments, Inc.

5. 3:55 PM - Thermal and Electrical Performance of Direct Bond Interconnect Technology for 2.5D and 3D Integrated Circuits Akash Agrawal, Shaowu Huang, Guilian Gao, Liang Wang, and Laura Mirkarimi – Invensas Corporation

6. 4:20 PM - Warpage Suppression During FOWLP Fabrication Process Keisuke Nishido, Yuhei Okada, Naoya Suzuki, and Toshihisa Nonaka – Hitachi Chemical

6. 4:20 PM - Comparison of Packaging Concepts for High-Temperature Pressure Sensors at 500°C Nilavazhagan Subbiah, Roderich Zeiser, and Juergen Wilde – University of Freiburg, IMTEK

6. 4:20 PM - Electrical Performance of High-Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly Lucile Arnaud, Arnaud Garnier, Rémi Franiatte, Alain Toffoli, Stéphane Moreau, Franck Bana, Stéphane Moreau, and Séverine Chéramy – CEA-Leti

7. 4:45 PM - Impact of Process Control on UBM/RDL Contact Resistance for NextGeneration Fan-Out Devices Patrik Carazzetti, Frantisek Balon, Mike Hoffmann, Juergen Weichart, Andreas Erhart, and Ewald Strolz – Evatec; Kay Viehweger – Fraunhofer IZM-ASSID

7. 4:45 PM - High Vacuum and High Robustness Al-Ge Bonding for Wafer Level Chip Scale Packaging of MEMS Sensors Jinghui Xu – Institute of Microelectronics, A*STAR

7. 4:45 PM - Morphological Evolution Affected by Surface Diffusion and ReactionInduced Volume Shrinkage in Micro Joints Hong-Wei Yang and C. Robert Kao – National Taiwan University

21


Program Sessions: Thursday, June 1, 1:30-5:10 p.m. Session 22: Solder Joint & Interconnect Reliability, Characterization

Session 23: Additive Manufacturing and Panel-Level Packaging

Session 24: Novel Methods to Assess Reliability

Committee: Thermal/Mechanical Simulation & Characterization and Modeling

Committee: Emerging Technologies

Committee: Applied Reliability

Session Co-Chairs: Yong Liu – ON Semiconductor Tel: +1-207-761-3155 Email: Yong.Liu@onsemi.com

Session Co-Chairs: Florian Herrault – HRL Laboratories, LLC Tel: +1-310-317-5269 Email: fgherrault@hrl.com

Session Co-Chairs: Sridhar Canumalla – Microsoft Corporation Tel: +1-425-538-4060 Email: scanuma@microsoft.com

Erkan Oterkus – University of Strathclyde Tel: +44 (0)141 548 3876 Email: erkan.oterkus@strath.ac.uk

W. Hong Yeo – Virginia Commonwealth University Tel: +1-804-827-3517 Email: whyeo@vcu.edu

Keith Newman – AMD Tel: +1-408-749-5566 Email: keith.newman@amd.com

1. 1:30 PM - Peridynamic Solution of Wetness Equation with Time-Dependent Saturated Concentration in ANSYS Framework Erdogan Madenci and Cagan Diyaroglu – University of Arizona; Selda Oterkus and Erkan Oterkus – University of Strathclyde

1. 1:30 PM - Will Low-Cost 3D Additive Manufactured Packaging Replace the FanOut Wafer Level Packages? Tobias Tiedje, Sebastian Lüngen, Martin Schubert, Marco Luniak, Krzysztof Nieweglowski, and Karlheinz Bock – Technical University Dresden

1. 1:30 PM - Condition Monitoring Algorithm for Piezoresistive Silicon-Based Stress Sensor Data Obtained from Electronic Control Units Alexandru Prisacaru, Alicja Palczynska, and Przemyslaw Jakub Gromala – Robert Bosch GmbH; Bongtae Han – University of Maryland; G. Q. (Kouchi) Zhang – Delft University of Technology

2. 1:55 PM - A Modified Acceleration Factor Empirical Equation for BGA Type Package Min-Hsuan Hsu and Kuo-Ning Chiang – National Tsing Hua University; Chang-Chun Lee – National Chung Hsing University

2. 1:55 PM - 3D Printing as a New Packaging Approach for MEMS and Electronic Devices Gabrielle Aspar, Baptiste Goubault, Olivier Lebaigue, Gilles Simon, Léa Di Cioccio, Olivier Dellea, Yves Brechet, and Jean-Charles Souriau – CEA-Leti; RoseMarie Sauvage – Direction Générale de l’Armement

2. 1:55 PM - Mechanical Characterization of SAC Solder Joints at High Temperature Using Nanoindentation Sudan Ahmed, Md Hasnine, Jeffrey Suhling, and Pradeep Lall – Auburn University

3. 2:20 PM - Effect of Mean Temperature on the Evolution of Strain-Amplitude in SAC Ball-Grid Arrays During Operation Under Thermal Aging and Temperature Excursions Pradeep Lall, Kazi Mirza, and Jeff Suhling – Auburn University; David Locker – U.S. Army Aviation & Missile Research Development & Engineering Center

3. 2:20 PM - 3D Printed High-Frequency Coaxial Transmission Line Based Circuits Michael Craton, Jennifer Byford, Vincens Gjokaj, Premjeet Chahal, and John Papapolymerou – Michigan State University

3. 2:20 PM - New Method to Separate Failure Modes by Transient Thermal Analysis of High-Power LEDs Alexander Hanss, E. Liu, Gordon Elger, Maximilian Schmid, and Dominik Müller – Technische Hochschule Ingolstadt; Udo Karbowski and Robert Derix – Lumileds

Refreshment Break: 2:45-3:30 p.m.

22

4. 3:30 PM - Development and Characterization of Dual Side Molding SiP Module Technology Jin-Yuan Lai, Tang-Yuan Chen, Jin-Feng Yang, Bo-Syun Chen, and Meng-Kai Shih – Advanced Semiconductor Engineering, Inc.

4. 3:30 PM - Design and Demonstration of Highly Miniaturized, Panel Level Glass Package for Low-Cost Gas Sensors Chintan Buch, Daniel Struk, Klaus Wolter, Peter J. Hesketh, Venkatesh Sundaram, and Rao Tummala – Georgia Institute of Technology; Catherine Shearer and James Haley – EMD-Ormet Circuits; Mel Findlay – KWJ Engineering; Marc Papageorge – SPEC Sensors

4. 3:30 PM - Improving Terahertz Signal Travel Distance for Fault Isolation Hemachandar Tanukonda Devarajulu, Mayue Xie, Chengqing Hu, and Deepak Goyal – Intel Corporation; Eiji Kato and Masaichi Hashimoto – Advantest Corporation

5. 3:55 PM - Bump Layout Impact Trends on Chip-Package Interaction Risk in an Advanced Node Chip in Flip Chip Packages Fahad Mirza, Thiagarajan Raman, Scott Pozder, Jae Kyu Cho, C. S. Premachandran, Carole Graas, and Patrick Justison – GLOBALFOUNDRIES

5. 3:55 PM - Miniature Heterogeneous FanOut Packages for High-Performance, LargeFormat Systems Carl Prevatte, Matthew Meitl, Erich Radauscher, David Gomez, Kanchan Ghosal, Salvatore Bonafede, Brook Raymond, Tanya Moore, and Christopher Bower – X-Celeprint; Paul Hines – Micross

5. 3:55 PM - A New Delamination Test Method for Molded Underfill (MUF) Package Junghwa Kim, Ki Hyeok Kwon, Dong Hwan Lee, Sang Kyun Kim, Deokhoon Pack, and Sungil Cho – Samsung Corporation

6. 4:20 PM - Anisotropic and Multiscale Constitutive Framework for the Reliability of Microscale Interconnects Based on Damage Mechanics Zhengfang Qian – Shenzhen University

6. 4:20 PM - Extremely High Temperature and High Pressure (x-HTHP) Endurable SOI Device & Sensor Packaging for Harsh Environment Applications Keng Yuen Au – Institute of Microelectronics, A*STAR

6. 4:20 PM - Measuring Sodium Migration in Mold Compounds using a Sodium Amalgam Electrode as an Infinite Source Stefan Schwab and Michael Nelhiebel – Kompetenzzentrum Automobil - U. Industrieelektronik; Julia Appenroth, Peter Weinberger, and Herbert Hutter – Technische Universität Wien; Sabine Holzer, Michael Bauer, and Stefan Miethaner – Infineon Technologies

7. 4:45 PM - SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer-Level Packages Wei Lin, Quan Pham, Bora Bora Baloglu, and Michael Johnson – Amkor Technololgy

7. 4:45 PM - A Study on the Novel Nylon Anchoring Polymer Layer(APL) Anisotropic Conductive Films(ACFs) for Ultra Fine Pitch Chip-On-Glass(COG) Applications Dal-jin Yoon, Sang-Hoon Lee, and Kyung-Wook Paik – Korea Advanced Institute of Science & Technology

7. 4:45 PM - A New Method for Prediction of Corrosion Processes in Metallization Systems for Substrates and Electrical Contacts Sandy Klengel, Tino Stephan, and Uwe Spohn – Fraunhofer IMWS


Program Sessions: Friday, June 2, 8:00-11:40 a.m. Session 25: Characterization and Reliability of Fan-Out & WLP

Session 26: 3D Integration Processing and Reliability

Session 27: Advances in Thermal Compression and Wirebonding

Committee: Applied Reliability

Committee: Advanced Packaging

Committee: Interconnections

Session Co-Chairs: Lakshmi N. Ramanathan – Microsoft Corporation Tel: +1-425-421-3838 Email: laramana@microsoft.com

Session Co-Chairs: Rozalia Beica –Dow Electronic Materials Tel: +1-508-787-4691 Email: rgbeica@dow.com

Session Co-Chairs: Matthew Yao – GE Energy Management Tel: +1-412-963-3244 Email: matthew.yao@ge.com

Toni Mattila – Aalto University Tel: +358-405009909 Email: toni.mattila@aalto.fi

Dean Malta – Micross Advanced Interconnect Technology Tel: +1-919-248-8405 Email: Dean.Malta@micross.com

William Chen – Advanced Semiconductor Engineering, Inc. Tel: +1-408-250-4290 Email: william.chen@aseus.com

1. 8:00 AM - Paradoxical Role of Sulphur in Molding Compounds: Influence on High Temperature Reliability of Cu-Al Wirebond Interconnects Amar Mavinkurve, Leon Goumans, Bongkoj Bumrungkittikul, Mark-Luke Farrugia, Erik van Olst, Michiel van Soestbergen, and Rene Rongen – NXP Semiconductors

1. 8:00 AM - Sub-Micron Electrical Interconnection for Ultra-High I/O Density Application Chung Jung Wu, Tung Liang Shao, Hsiao Yun Chen, Sheng Tsung Hsiao, Yi Li Hsiao, Chih Hang Tung, and Zhen Hua Yu – Taiwan Semiconductor Manufacturing Company, Ltd.

1. 8:00 AM - Fine Pitch Die-to-Si Interconnect Fabric (Si-IF) Interconnects using Thermal Compression Bonding Adeel Ahmad Bajwa, SivaChandra Jangam, Saptadeep Pal, Niteesh Marathe, Mark Goorsky, Takafumi Fukushima, and Subramanian Iyer – University of California, Los Angeles

2. 8:25 AM - Mechanistic Investigation and Prevention of Al Bond Pad Corrosion in Cu Wire Bonded Device Assembly Oliver Chyan, Nick Ross, Alex Lambert, Seare Berhe, and Muthappan Asokan – University of North Texas; Mahmud Chowdhury, Shawn O’Connor, and Luu Nguyen – Texas Instruments, Inc. 3. 8:50 AM - Use Condition Risk Assessment for Moisture-Related Failures Min Pei, Sibasish Mukherjee, Nitin Uppal, and Milena Vujosevic – Intel Corporation

2. 8:25 AM - Temporary Bonding and Debonding via Hydrogenated Amorphous-Si and Spin-on-Glass for Multichip to Wafer 3D Integration – Process Optimization and an XPS Study Takafumi Fukushima and Mitsumasa Koyanagi – Tohoku University 3. 8:50 AM - Cu/Adhesive Hybrid Bonding at 180°C in H-Containing HCOOH Vapor Ambient for 2.5D/3D Integration Ran He, Masahisa Fujino, Masatake Akaike, and Tadatomo Suga – University of Tokyo; Taiji Sakai and Seiki Sakuyama – Fujitsu Semiconductor

2. 8:25 AM - Reliable Cu-Cu ThermoCompression Bonding by Low Temperature Sintered Cu Nanowires Li Du, Tielin Shi, Zirong Tang, and Guanglan Liao – Huazhong University of Science and Technology

3. 8:50 AM - Effect of Metallic Materials Films on the Properties of Copper/Tin Micro-Bump Thermo-Compression Bonding Yong Guan, Qinghua Zeng, Jing Chen, and Yufeng Jin – Peking University; Shenglin Ma – Xiamen University

Refreshment Break: 9:15-10:00 a.m. 4. 10:00 AM - Drop Impact Reliability Test and Failure Analysis for Large Size HighDensity FOWLP Package on Package Zhaohui Chen – Institute of Microelectronics, A*STAR

4. 10:00 AM - 3D Packaging Challenges for High-End Applications Sukesh Kannan and Luke England – GLOBALFOUNDRIES; Rick Reed, Yong Song, SangHyoun Lee, WangGu Lee, and JinKun Yoo – Amkor Technololgy

4. 10:00 AM - Thermal Bond Reliability of High-Reliability New Palladium-Coated Copper Wire Motoki Eto, Teruo Haibara, Ryo Oishi, and Takashi Yamada – Nippon Micrometal; Tomohiro Uno – Nippon Steel & Sumitomo Metal

5. 10:25 AM - The Comparative Study to Enhance Board Level Reliability Performance of Wafer Level Package at 0.25 mm Pitch Using Micro-Ball Drop and Electroplated Solder Technology Kuei Hsiao Kuo, Yi Sin Ding, Chui Feng Weng, Feng Lung Chien, Katch Wan, Chun Sheng Ho, and Rick Lee – Siliconware Precision Industries Co., Ltd.

5. 10:25 AM - A Novel Method for Air-gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ) and Cross-talk Mingbin Yu – Institute of Microelectronics, A*STAR

5. 10:25 AM - Correlation Study of Pd Metallurgical Distributions and RF Characteristics of Pd Coated/Doped Ag-alloy Wire Bonds Yi-Jung Sung and Lih-Tyng Hwang – National Sun YatSen University; Chang-Yi Feng – NXP Semiconductor

6. 10:50 AM - Quality and Reliability Assessment of Cu Pillar Bumps for Fine Pitch Applications Othmane Jerhaoui, Stephane Moreau, David Bouchu, Gilles Romero, Denis Marseilhan, Thierry Mourier, and Arnaud Garnier – CEA-Leti

6. 10:50 AM - Warpage Tuning Study of Large 2.5D IC Chip Module Chieh-Lung Lai, Hung-Yuan Li, Sam Peng, Terren Lu, Candice Zeng, George Pan, and Stephen Chen – Silicon Precision Industries Co., Ltd.

6. 10:50 AM - Advances in Wire Bonding Technology for 3D Die Stacking and FanOut Wafer Level Package Ivy Qin, Oranna Yauw, Gary Schulze, Aashish Shah, Bob Chylak, and Nelson Wong – Kulicke and Soffa

7. 11:15 AM - Effect of Prolonged Storage up to 1-Year on the High Strain Rate Properties of SAC Lead-Free Alloys at Operating Temperatures up to 200°C Pradeep Lall, Di Zhang, Vikas Yadav, and Jeff Suhling – Auburn University; David Locker – U.S. Army Aviation & Missile Research Development & Engineering Center

7. 11:15 AM - Board Level Reliability Optimization for 3D IC Packages with Extra Large Interposer Laurene Yip, Ganesh Hariharan, Raghu Chaware, Inderjit Singh, and Tom Lee – Xilinx Corporation

7. 11:15 AM - Development of HighTemperature Resistant Packaging of SiC Power Module for Automobile Application Kohei Tatsumi, Tomonori Iizuka, Kazuhito Kamei, and Masakazu Inagaki – Waseda University; Akihiro Imakiire and Masayuki Hikita – Kyushu Institute of Technology; Rikiya Kamimura – FAIS; Nobuaki Sato, Kazuhide Ueno, and Koji Shimizu – Mitsui High-tec

23


Program Sessions: Friday, June 2, 8:00-11:40 a.m. Session 28: Advanced Materials for Reliability Improvement

Session 29: Warpage Control and Substrates

Session 30: RF Components and Module Integration

Committee: Materials & Processing

Committee: Assembly & Manufacturing Technology

Committee: High-Speed, Wireless & Components

Session Co-Chairs: Kwang-Lung Lin – National Cheng Kung University Tel: +886-6-2762709 Email: matkllin@mail.ncku.edu.tw

Session Co-Chairs: Paul Tiner – Texas Instruments, Inc. Tel: +1-469-471-3565 Email: p-tiner@ti.com

Session Co-Chairs: Craig Gaw – NXP Semiconductor Tel: +1-480-413-5920 Email: c.a.gaw@ieee.org

Bing Dang – IBM Corporation Tel: +1-914-945-1568 Email: dangbing@gmail.com

Paul Houston – Engent Tel: +1-770-280-4238 Email: paul.houston@engentaat.com

Wendem Beyene – Rambus Inc. Tel: +1-408-462-8366 Email: wbeyene@rambus.com

1. 8:00 AM – High-Performance Insulating Adhesive Film for High-Frequency Applications Junya Sato, Shin Teraki, Masaki Yoshida, and Hisao Kondo – NAMICS Corporation

1. 8:00 AM - Innovative Advances in Copper Electroplating for IC Substrate Manufacturing Kousik Ganesan, Yang Sun, Chandrashekhar Pendyala, Thomas Heaton, Radek Chalupa, Marcel Wall, Suddhasattwa Nad, Andrew Wentzel, and Rahul Manepalli – Intel Corporation; Amaneh Tasooji – Arizona State University

1. 8:00 AM - Next Generation High-Q Compact Size IPD Diplexer for RF Front End SiP Sheng-Chi Hsieh, Pao-Nan Lee, Chen-Chao Wang, Teck Chong Lee, and Hsu-Chiang Shih – Advanced Semiconductor Engineering, Inc.

2. 8:25 AM - Epoxy/Cyanate Ester Blend Material for Molding Compounds in HighTemperature Operations Chia-Chi Tuan, Fan Wu, Kyoung-Sik Moon, Raj Pulugurtha, Ching-Ping Wong, and Rao Tummala – Georgia Institute of Technology

2. 8:25 AM - Reflow Warpage Induced Interconnect Gaps Between Package and PCB and PoP Top and Bottom Packages Kaiqiang Peng, Wei Xu, Zhenkai Qin, Lei Feng, Linlin Lai, and Wei Hu Koh – Huawei Technologies

2. 8:25 AM - Self-Actuating 3D Printed Packaging for Deployable Antennas Ryan Bahr and Manos Tentzeris – Georgia Institute of Technology

3. 8:50 AM - High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Makoto Shibuya and Luu Nguyen – Texas Instruments, Inc.

3. 8:50 AM - Warpage Tuning Study for Multi-Chip Last Fan-Out Wafer Level Package Hung-Yuan Li, Allen Chen, Sam Peng, George Pan, and Stephen Chen – Siliconware Precision Industries Co., Ltd.

3. 8:50 AM - A Simple and Efficient RF Technique for the TSV Characterization Xiao Sun, Stefaan Van Huylenbroeck, Geert Van der Plas, and Eric Beyne – IMEC; Cesar Roda Neve – M3 Systems

Refreshment Break: 9:15-10:00 a.m.

24

4. 10:00 AM - Enhanced Thermal Conductivity of the Underfill Materials using Insulated Core/Shell Filler Particles for High-Performance Flip Chip Applications Tae-Ryong Kim, Kisu Joo, and Se Young Jeong – Ntrium, Inc.; Boo Taek Lim and Boung Ju Lee – National Nanofab Center; Sung-Soon Choi – Korea Electronics Technology Institute; Myung Jin Yim – Intel Corporation; Euijoon Yoon – Seoul National University

4. 10:00 AM - Warpage Characterization of Glass Interposer Package Development Mengkai Shih, Charles Hsu, Yungshun Chang, Karenyu Chen, and Ian Hu – Advanced Semiconductor Engineering, Inc.

4. 10:00 AM - Smallest Form Factor GPS for Mobile Devices Ebrahim Andideh, Chuck Carpenter, Jason Steighner, Mike Yore, James Tung, Lynda Koerber, David Schnaufer, Bharati Ingle, Suwanna Jittinorasett, and Otto Berger – Qorvo, Inc.

5. 10:25 AM - High Thermal Performance Package with Anisotropic Thermal Conductive Material Ian Hu, Janae Ho, Penny Yang, and C. P. Hung – Advanced Semiconductor Engineering, Inc.

5. 10:25 AM - The Influence of Resin Coverage on Reliability for Solder Joints Formed by One-Pass Reflow using Resin Reinforced Low-Temperature Solder Paste Atsushi Yamaguchi, Yasuo Fukuhara, Andy Behr, Naomichi Ohashi, Yasuhiro Suzuki, and Hirohisa Hino – Panasonic Corporation

5. 10:25 AM - Transparent Antennas for Wireless Systems based on Patterned Indium Tin Oxide and Thin Flexible Glass Mark Poliks, Yi-Lin Sung, Jack Lombardi, Robert Malay, and Charles Westgate – Binghamton University; MingHuang Huang, Sean Garner, Scott Pollard, and Colin Daley – Corning, Inc.

6. 10:50 AM - Reduction of Outgas from Pre-Applied Underfill Materials by Optimizing the Combination of Base Resin and Flux Compound Kohei Higashiguchi, Takenori Takiguchi, Masashi Okaniwa, Katsutoshi Ihara, Tsuyoshi Kida, Shu Yoshida, and Toyoji Oshima – Mitsubishi Gas Chemical

6. 10:50 AM - Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars Vidya Jayaram, Scott McCann, Bhupender Singh, Pulugurtha Markondeya Raj, Ting-Chia Huang, Vanessa Smet, and Rao Tummala – Georgia Institute of Technology; Hiro Matsuura and Yutaka Takagi – NTK/NGK

6. 10:50 AM - Designs and Characterizations of RF 3D Module Based on Si Interposers Kwang-Seong Choi, Leeseul Jeong, Seok Hwan Moon, Yong-Sung Eom, Hyun-Cheol Bae, and Jin Ho Lee – Electronic and Telecommunication Research Institute

7. 11:15 AM - Study of Capillary Underfill Filler Separation in Advanced Flip Chip Packages Marie-Claude Paquet – IBM Corporation; David Danovitch – Université de Sherbrooke

7. 11:15 AM - A Comprehensive Study on Stress and Warpage by Design, Simulation and Fabrication of RDL-First Panel Level Fan-Out Technology for Advanced Package Puru Lin, Cheng-Ta Ko, and Yu-Hua Chen – Unimicron

7. 11:15 AM - An Electronic Nose for Wireless Sensing of Volatiles by Capillary Condensation Saranraj Karuppuswami, Amanpreet Kaur, and Premjeet Chahal – Michigan State University; Nophadon Wiwatcharagoses – Mongkut’s University of Technology


Program Sessions: Friday, June 2, 1:30-5:10 p.m. Session 31: Auto Electronics Packaging and Power Modules

Session 32: Reliability Challenges in 2.5D/3D Interconnect

Session 33: Advanced Bonding and Soldering Technology

Committee: Advanced Packaging

Committees: Interconnections joint with Applied Reliability

Committee: Materials & Processing

Session Co-Chairs: Jianwei Dong – Dow Electronic Materials Tel: +1-508-229-7117 Email: jianweidong@dow.com

Session Co-Chairs: Nathan Lower – Rockwell Collins, Inc. Tel: +1-319-295-6687 Email: nathan.lower@rockwellcollins.com

Session Co-Chairs: Kimberly Yess – Brewer Science Tel: +1-573-201-8669 Email: kyess@brewerscience.com

Christophe Zinck – Advanced Semiconductor Engineering, Inc. Tel: +33-628566802 Email: Christophe.Zinck@aseeu.com

Dongji Xie – NVIDIA Corporation Tel: +1-408-486-8630 Email: dongjix@nvidia.com

Qianwen Chen – IBM Corporation Tel: +1-914-945-1612 Email: chenq@us.ibm.com

1. 1:30 PM - Novel Polymer Substrate-Based 1.2 kV/40 A Double-Sided Intelligent Power Module Xin Zhao, Bo Gao, and Douglas Hopkins – North Carolina State University

1. 1:30 PM - Reliability Challenges in 2.5D and 3D IC Integration Li Li, Paul Ton, and Peng Su – Cisco Systems, Inc.

1. 1:30 PM - Novel Large-Area Attachment for High-Temperature Power Electronics Module Application Chunlei Liu, Fabian Mohn, and Juergen Schuderer – ABB Group

2. 1:55 PM - Advanced Packaging Need for Automotive Dashboard Application Nokibul Islam, MC Hsieh, and KyungOe Kim – STATS ChipPAC

2. 1:55 PM – High-Frequency Electrical Performance and Thermo-Mechanical Reliability of Fine Pitch, Copper Metallised Through Package Vias (TPVs) in Ultra-Thin Glass Substrates Sukhadha Viswanathan, Timothy B. Huang, Atomu Watanabe, P. Markondeya Raj, Fuhan Liu, Venky Sundaram, and Tummala Rao – Georgia Institute of Technology; Tomonori Ogawa – Asahi Glass

2. 1:55 PM - Bismuth-Based Transient Liquid Phase (TLP) Bonding as HighTemperature Lead-Free Solder Alternatives Junghyun Cho, Roozbeh Sheikhi, and Sandeep Mallampati – Binghamton University; Liang Yin and David Shaddock – GE Global Research

3. 2:20 PM - Reliability of eWLB (embedded wafer level BGA) for Automotive Radar Applications Daniel Yap, Kim Sing Wong, and Luc Petit – STMicroelectronics; Yaojian Lin – STATS ChipPAC

3. 2:20 PM - Reliability Evaluations on 3D ID Package Beyond JEDEC Raghunandan Chaware, Laurene Yip, Inderjit Singh, Kenny Ng, and Antai Xu – Xilinx Corporation

3. 2:20 PM - Silver Sinter Paste for SiC Bonding with Improved Mechanical Properties Wolfgang Schmitt and Ly May Chew – Heraeus Group

Refreshment Break: 2:45-3:30 p.m. 4. 3:30 PM - Packaging Innovations for High Voltage (HV) GaN Technology Dibyajat Mishra, Vivek Arora, Luu Nguyen, Shoichi Iriguchi, Hiroyuki Sada, Laura Clemente, Sueann Lim, Hung-Yun Lin, Siva Gurrum, and Alok Lohia – Texas Instruments, Inc.

4. 3:30 PM - Remarkable Suppression of Local Stress in 3D IC by Manganese NitrideBased Filler with Large Negative CTE Hisashi Kino, Takafumi Fukushima, and Tetsu Tanaka – Tohoku University

4. 3:30 PM - Mechanical and Thermal Properties of Joint Materials for WideBand-Gap Semiconductors at High Temperature Minoru Ueshima – Senju Metal Industry Co., Ltd.

5. 3:55 PM - Thin-Film Magnetic Inductors for Integrated Power Management Annamalai Arasu Muthukumaraswamy, King-Jien Chui, Wei Yi Lim, Serine Soh, Jun Yu, Yew Wing Leong, Huamao Lin, and Sunil Wickramanayaka – Institute of Microelectronics, A*STAR

5. 3:55 PM - Electrical Characterization of CMP-Less Via-Last TSV under Reliability Stress Conditions Mingbin Yu – Institute of Microelectronics, A*STAR

5. 3:55 PM - Study of C2W Bonding using Cu Pillar with Side-wall Plated Solder Ling Xie, Sunil Wickramanayaka, Ser Choong Chong, and Nagendra Sekhar Vasarla – Institute of Microelectronics, A*STAR

6. 4:20 PM - Feasibility Investigations on SLM Technology for the Development of Microchannel Cooling in Power Electronic Applications Aarief Syed Khaja and Joerg Franke – Friedrich Alexander University

6. 4:20 PM - A Novel Failure Analysis Technique for Semiconductor Packaging by XeF2 Gas Hongqing Zhang Zhang, Frank Pompeo, and Tom Wassick – IBM Corporation

6. 4:20 PM - Fabrication and Characterization of Nanoporous Metallic Interconnects Using Electrospun Nanofiber Template and Electrochemical Deposition Sheng-Po Fang, Seahee Hwangbo, Hyowon An, and Yong-Kyu Yoon – University of Florida

7. 4:45 PM - Reliability Assessment of POLKilowatt Power Modules Kaustubh Nagarkar, Liang Yin, Arun Gowda, Christopher Kapusta, Paul Gillespie, Tammy Johnson, and Risto Tuominen – General Electric Co.; Shingo Hayashibe, Hitoshi Ito, and Tadashi Arai – Shinko Electric Industries Co., Ltd.

7. 4:45 PM - Strain Quantification of Microbumps at the Intermetallic Rich Zone Huayan Wang, Yuling Niu, and Seungbae Park – Binghamton University

7. 4:45 PM - Ga Liquid Metal Embrittlement for Fine Pitch Interconnect Rework Yolande Elodie Nguena Dongmo, David Danovitch, and Malak Kanso – University of Sherbrooke; Richard Langlois – IBM Corporation

25


Program Sessions: Friday, June 2, 1:30-5:10 p.m. Session 34: Waveguide Devices and Chip-to-Fiber Packaging

Session 35: Thermomechanical and Thermal Characterization

Session 36: Advances in Signal and Power Integrity

Committee: Optoelectronics

Committee: Thermal/Mechanical Simulation & Characterization

Committee: High-Speed, Wireless & Components

Session Co-Chairs: Ping Zhou – LDX Optronics, Inc. Tel: +1-865-981-8822 Email: pzhou@ldxoptronics.com

Session Co-Chairs: Pradeep Lall – Auburn University Tel: +1-334-844-3424 Email: lall@auburn.edu

Session Co-Chairs: Zhaoqing Chen – IBM Corporation Tel: +1-845-435-5595 Email: zhaoqing@us.ibm.com

Hiren Thacker Tel: +1-619-940-7803 Email: hiren@tech301.com

Przemyslaw Gromala – Robert Bosch GmbH Tel: +49-71213539126 Email: Przemyslawjakub.gromala@de.bosch.com

Amit P. Agrawal – Keyssa Inc. Tel: +1-408-666-8452 Email: Ap_agrawal@yahoo.com

1. 1:30 PM - Design, Fabrication and Connectorization of High-Performance Multimode Glass Waveguides for BoardLevel Optical Interconnects Lars Brusberg, Davide Fortusini, Wei Jiang, Aramais Zakharian, Sergey Kuchinsky, Christian Fiebig, Shenping Li, Andrey Kobyakov, and Alan Evans – Corning; Henning Schröder – Fraunhofer IZM

1. 1:30 PM - The Combined Effect of Mechanical Package Stress and Humidity on Chip Corrosion Probability Georg Lorenz and Michél Simon-Najasek – Fraunhofer IMWS; Achim Lindner – TDK-Micronas GbmH

1. 1:30 PM - Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery Amit Jain, Sameer Shekhar, and Yan Li – Intel Corporation

2. 1:55 PM - Axially Tapered Circular Core Polymer Optical Waveguides Enabling Highly Efficient Light Coupling Kenji Katori, Hoshihiko Toda, and Kazuki Yasuhara – Keio University

2. 1:55 PM - Mechanical Characterization of Anodic Bonding using Chevron-Shaped Microchannel David Woodrum and Suresh Sitaraman – Georgia Institute of Technology

2. 1:55 PM - High Voltage and High Temperature Capacitors for Next-Generation Power Modules in Electric Vehicles Robert Spurney, Himani Sharma, Markonodeya Pulugurtha, and Rao Tummala – Georgia Institute of Technology; Naomi Lollis – AVX Corporation; Matt Romig and Saumya Gandhi – Texas Instruments, Inc.; Holger Brumm – H. C. Starck GmbH

3. 2:20 PM - First Demonstration of SingleMode Polymer Optical Waveguides with Circular Cores for Fiber-to-Waveguide Coupling in 3D Glass Photonic Interposer Rui Zhang, Bruce C Chou, Fuhan Liu, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Michael Gallagher and Corey O’Connor – Dow Chemical

3. 2:20 PM - Package-Level Si Micro-Fluid Cooler with Enhanced Jet Array for HighPerformance 3D Systems Yong Han, Boon Long Lau, and Gongyue Tang – Institute of Microelectronics, A*STAR; Seow Meng Low and Jason Goh – BeCe Pte. Ltd.

3. 2:20 PM - Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing Sungjun Chun, Jose Hejase, Junyan Tang, Jean Audet, Dale Becker, Daniel Dreps, Glen Wiedemeier, Megan Nguyen, Lloyd Walls, Francesco Preda, and Daniel Douriet – IBM Corporation

Refreshment Break: 2:45-3:30 p.m.

26

4. 3:30 PM - 3D Optical Coupling Techniques on Polymer Waveguides for Wafer and Board Level Integration Sebastian Lüngen, Sujay Charania, Tobias Tiedje, Krzystof Nieweglowski, Sebastian Killge, Lukas Lorenz, Johann W. Bartha, and Karlheinz Bock – Technical University Dresden

4. 3:30 PM - A Unified and Versatile Model Study for Moisture Diffusion Liangbiao Chen – Lamar University

4. 3:30 PM - Signal and Power Integrity Analysis of High-Speed Links with Si Interposer Wendem Beyene, Nitin Jalilia, Yeon-Chang Halm, Ravi Kollipara, and Joohee Kim – Rambus, Inc.

5. 3:55 PM - Position Dependence of Coupling Efficiency of Grating Coupler in Waveguide Cavity Shogo Ura, Kazuki Mori, Ryo Tsujimoto, and Junichi Inoue – Kyoto Institute of Technology; Kenji Kintaka – National Institute of Advanced Industrial Science and Technology

5. 3:55 PM - Microstructure Simulation and Thermo-Mechanical Behavior Analysis of Copper-Filled Through Silicon Vias Using Coupled Phase Field and Finite Element Methods Shui-Bao Liang, Chang-Bo Ke, Han Jiang, Min-Bo Zhou, and Xin-Ping Zhang – South China University of Technology

5. 3:55 PM - Novel Parallel Resonance Peak Measurement and Modeling Technique for 2-T and 3-T MLCC Capacitors for PDN Application Larry Smith, Javid Mohamed, Jaemin Shin, and Tim Michalka – Qualcomm Technologies, Inc.

6. 4:20 PM - Efficient, Easy-to-Use, Planar Fiber-to-Chip Coupling Process with AnglePolished Fibers Djorn Karnick, Nils Bauditsch, Lars Eisenblätter, Thomas Kühner, Marc Schneider, and Marc Weber – Karlsruhe Institute of Technology (KIT)

6. 4:20 PM - Research on Ionic Wind and Its Cooling Ability Based on Finite Element Method and Experiment Chunlin Xu and Shannan Zhan – Huazhong University of Science & Technology; Huai Zheng and Sheng Liu – Wuhan University

6. 4:20 PM - Eye-Diagram Estimation Methods for Voltage- and ProbabilityDependent PAM-4 Signal on Stacked Through-Silicon Vias Junyong Park, Jonghoon J. Kim, Sumin Choi, and Joungho Kim – Korea Advanced Institute of Science & Technology; Heegon Kim Kim – MST

7. 4:45 PM - Novel, High-Throughput, Fiber-to-Chip Assembly Employing Only Offthe-Shelf Components Nicolas Boyer, Stephan Martel, Swetha Kamlapurkar, Sebastian Engelmann, Paul Fortier, and Tymon Barwicz – IBM Corporation; Alexander Janta-Polczynski – ICM; Jean-Francois Morissette – Université de Sherbrooke

7. 4:45 PM - Systematic Approach to Design High-Power FPGA Package for CurrentCarrying Capability Siow Chek Tan, Jae-Gyung Ahn, Gamal Refai-Ahmed, and Suresh Ramalingam – Xilinx Corporation

7. 4:45 PM - System-Driven On-chip SI/ PI Solutions in Ultra-Low Cost Non-Term 1600+ Mbps LPDDR3/DDR3/DDR4 Chung-Hwa Wu, Hung-Chuan Chen, Yingmin Liao, and Shang-Ping Chen – MediaTek


Interactive Presentations: Wednesday, May 31, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m. Wednesday, May 31, 2017 Session 37: Interactive Presentations 1 9:00 a.m. - 11:00 a.m. Committee: Interactive Presentations Session Co-Chairs: Rao Bonda Amkor Technology Tel: +1-480-786-7749 Email: rao.bonda@amkor.com John Hunt Advanced Semiconductor Engineering, Inc. Tel: +1-480-718-8011 Email: john.hunt@aseus.com Deborah S. Patterson Principal, Patterson Group Tel: +1-480-703-5683 Email: deborah@patterson-group.com Andy Tseng JSR Micro Tel: +1-408-472-7345 Email: atseng@jsrmicro.com Package-Level EMI Shielding Technology with Silver Paste for Various Applications Kisu Joo, Tae-Ryong Kim, Jung Woo Hwang, JinHo Yoon, and Se Young Jeong – Ntrium; Myung Jin Yim – Intel Corporation Effects of Current Stress for LowTemperature Cu/Sn/Cu Solid-StateDiffusion Bonding Jian Cai, Qian Wang, and Zijian Wu – Tsinghua University; Junqiang Wang and Dejun Wang – Dalian University of Technology High Uph Low-Stress Air Jetting Carrier Release for RDL First Fan-Out WLP Hao Tang, Gary Shi, and Chris Luo – Micro Materials; Ming Yin – Zhejiang Microtech; Mike Chang and Sheng-Shu Yang – Industrial Technology Research Institute Chip-Scale Scalar Atomic Magnetometer Operating in Geomagnetic Environment Zhihua Pan and Jintang Shang – Southeast University New Resin Materials for High Power Embedding Michael Guyenot, Christiane Mager, and Roumen Ratchev – Robert Bosch GmbH; Thomas Gottwald – Schweizer Electronic; Sascha Kreuer – Isola GmbH 48×10 Gbps Cost-Effective FPC Based On-Board Optical Transmitter with PGA Connector Teng Li, Gonzalo Guelbenzu de Villota, Chenhui Li, R. Patty Stabile, and Oded Raz – Eindhoven University of Technology A Novel Wafer Level Integration of Liquid-Metal Injection Based TSV and Integrated Passive Devices Tao Zheng, Gaowei Xu, and Le Luo – Shanghai Institute of Microsystem and Information Technology Next-Generation Plating Technologies for FO-Panel Level Packaging Ralph Zoberbier – Atotech

Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for Low-Cost and High-Performance FCBGA Package Nokibul Islam, Vinayak Pandey, and KyungOe Kim – STATS ChipPAC Compression Molding Encapsulants for Wafer-Level Embedded Active Devices (TSV) Ki Hyeok Kwon, Yoonman Lee, Dong Hwan Lee, and Sang Kyun Kim – Samsung SDI; Kunsil Lee, Dong Kwan Kim, and Chul Woo Kim – Samsung Electronics A Density Staggered Cantilever for Micron Length Gravity Probing Qidong Wang – Institute of Microelectronics/ Stanford University

A Unique Temporary Bond Solution Based on a Thermoplastic Material Tacky at Room Temperature and Highly Thermally Resistant Application Extension from 3D-SIC to FOWLP Alain Phommahaxay, Goedele Potoms, Julien Bertheau, Pieter Bex, Teng Wang, Fabrice Duval, Arnita Podpod, and Eric Beyne – IMEC; Atsushi Nakamura and Yoshitaka Kamochi – FUJIFILM 3D Printed Out-of-Plane Antennas for Microwave and Millimeter Wave Applications Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Amanpreet Kuar, Jennifer Byford, Jonathan Frasch, James Lennon, and Premjeet Chahal – Michigan State University

Flip Chip Solder Joint Pad Optimizations for Connectivity SiP Applications Quan Qi and Carlton Hanna – Intel Corporation

Wednesday, May 31, 2017 Session 38: Interactive Presentations 2 2:00 p.m. - 4:00 p.m.

Scalability and Yield in Elastomer Stamp Micro-Transfer-Printing David Gomez, Tanya Moore, Matthew Meitl, Salvatore Bonafede, Carl Prevatte, David Kneeburg, Alin Fecioru, Antonio Trindade, Christopher Bower, and Kanchan Ghosal – X-Celeprint

Committee: Interactive Presentations

Dynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-situ by Using Silicon Piezoresistive Sensor Keiichiro Iwanabe, Kenichi Nakadozono, and Tanemasa Asano – Kyushu University

Patrick Thompson Texas Instruments, Inc. Tel: +1-214-567-0660 Email: patrick.thompson@ti.com

High Transmittance Broadband THz Polarizer using 3D-IC Technologies Nai-Chen Chi, Ting-Yang Yu, Hsin-Cheng Tsai, Chih-Wei Luo, and Kuan-Neng Chen – National Chiao Tung University; Shiang-Yu Wang – Academia Sinica High Accuracy Thermal Compression Bonding Technology for Large-Sized Substrate Noboru Asahi, Toshiyuki Jinda, Yoshihito Mizutani, Koichi Imai, Hikaru Tomita, Mikio Kawakami, Masafumi Senda, and Katsumi Terada – Toray Engineering Real-Time Tunable Color White LED Through Combination of Phosphor Patterns and Adaptive Liquid Lens Huai Zheng – Wuhan University Yield Comparison of Die-First FaceDown and Die-Last Fan-Out Wafer Level Packaging Amy Lujan – SavanSys Solutions, LLC Assembly Challenges for 75x75mm² Large Body FCBGA with Emerging High Thermal Interface Material (TIM) Fletcher (Cheng-Piao) Tung, Max (Chin Yu) Lu, Albert (Chang Yi) Lan, and Steward (Chi An) Pan – Siliconware Precision Industries Co., Ltd. V-DOE Laser Full Cut Dicing of Thin Si IC Wafers Jeroen van Borkulo, Paul Verburg, and Richard van der Stam – ASM Pacific Technologies A New Method for 3D Microstructure Fabrication via Ionic Wind Shangru Zhou, Guoliang Li, Huai Zheng, and Sheng Liu – Wuhan University

Session Co-Chairs: Nam Pham IBM Corporation Tel: +1-512-286-8011 Email: npham@us.ibm.com

Eric Beyne IMEC Tel: +32-16-281-261 Email: eric.beyne@imec.be Richard Rao MicroSemi Tel: +1-805-914-2272 Email: Richard.rao@microsemi.com Exploring Multi-Drop DDR4 Address Bus Design for 4GTS and Higher Speed Data Nanju Na, Juan Wang, Sean Long, Changyi Su, Thomas To, Yong Wang, and Dima Klokotov – Xilinx Corporation Transfer Function Reconfigurable Cavity Bandpass Filter Embedded with Metallic Grid Shang-Yu Hung, Guann-Pyng Li, Mark Bachman, Hsiang-Yu Chan, and Zhihao Zhang – University of California, Irvine Signal Integrity Modelling in Inhomogeneous Waveguide/PCB of Arbitrary Shape Using Broadband Green’s Function Kung-Hau Ding – Air Force Research Laboratory; Tien-Hao Liao and Leung Tsang – University of Michigan RF Characterization and Modeling of 10mm Fine-Pitch Cu-Pillar on a HighDensity Silicon Interposer Hélène Jacquinot – CEA-Leti A Novel Frequency-Modulated Power Delivery Network Design for DRAM Interface in Low-Cost Wirebond Package Sheng-Feng Lee, Chia-Yu Chan, and Shang-Pin Chen – MediatTek Corporation

27


Interactive Presentations: Wednesday, May 31, 2:00 p.m. - 4:00 p.m. and Thursday, June 1, 9:00 a.m. - 11:00 a.m. Compact Thin-Film Broadband Millimeter-Wave Bandpass Filters on Low-Loss Glass Interposers using Evanescent Mode Eighth-Mode Substrate Integrated Waveguide Cavities David Senior – Anaren Microwave; Seahee Hwangbo and Yong-Kyu Yoon – University of Florida; Aric Shorey – Corning; Jungkwun Kim – University of Kansas New Wave Fan-Out Package Design and Electrical Analysis in Mobile Application Tsun-Lung Hsieh, Po-Chih Pan, Chih-Yi Huang, Ming-Fong Jhong, and Chen-Chao Wang – Advanced Semiconductor Engineering, Inc.; YuanHsi Chou – The University of Texas, Austin Multi-Band Harmonic RF Tags for Barcode Applications in a Cluttered Environment Saranraj Karuppuswami, Mohd Ifwat Mohd Ghazali, Amanpreet Kaur, and Premjeet Chahal – Michigan State University TSV-Integrated High-Band AlN Based RF-MEMS Resonator for Mobile and Wireless Applications Nan Wang, Yao Zhu, Chengliang Sun, Mingbin Yu, Geng Li Chua, Srinivas Merugu, Navab Singh, and Yuandong Gu – Institute of Microelectronics, A*Star Equalization Enhancement Approaches for PAM4 Signaling for Next-Generation Speeds Jiayi He, Nana Dikhaminjia, Mikheil Tsiklauri, and James Drewniak – Missouri University of S&T; Bhyrav Mutnury and Arun Chada – Dell, Inc. Data Transfer Performance Analysis and Enhancement of Critical 3D Interconnects in a 3D SIP based on Communication Channel Modeling Methodology Min Miao, Zhensong Li, and Xiaoyang Duan – Beijing Information Science and Technology University; Xiaole Cui and Yufeng Jin – Peking University A New and Effective EMI Shield Method with Nanomagnetic Multilayered Film Composite Ji Hye Lee, Kyong Chul Bae, Yoonman Lee, Junghwa Kim, Dong Hwan Lee, and Sang Kyun Kim – Samsung SDI

Depayne Athia and Michael Mayer – University of Waterloo; Alireza Rezvani, Horst Clauberg, and Ivy Qin – Kulicke and Soffa Low Loss Channel-Shuffling Polymer Waveguides: Design and Fabrication Kohei Abe, Yutaro Oizumi, Yoichi Taira, and Takaaki Ishigure – Keio University A Comprehensive Reliability Assessment of Electronic Packages with Digital Image Correlation Method Yuling Niu, Jing Wang, and Seungbae Park – State University of New York at Binghamton; Van-Lai Pham – State University of New York, Binghamton Resistometric Characterization of the Interface Between Au Wire Bonds to AlCuW Bond Pads Steve Kilgore and Craig Gaw – NXP Semiconductors A Low-Cost and Compact 100G PAM-4 ROSA using TO-Can Package Sae-Kyoung Kang, Jie Hyun Lee, Joon Young Huh, and Joon Ki Lee – Electronics and Telecommunications Research Institute Comparison and Consistency of On-PCB Microstrip Line Modeling by 3D Fullwave and 2D Quasi-Static Approaches for High-Speed Packaging System Signal Integrity Simulations Zhaoqing Chen – IBM Corporation New Analytical Method for Assessing Thermo-Mechanical Stress-Induced Damage to WLCSP Solder Interconnects Tae-Kyu Lee – Portland State University; Weidong Xie, Steven Perng, Cherif Guirguis, and Kola Akinade – Cisco Systems; Edward Ibe and Karl Loh – Zymet, Inc. Real-Time Diagnosis of Wire Degradation based on Digital Signal Analysis Jinwoo Lee and Daeil Kwon – Ulsan National Institute of Science and Technology Thursday, June 1, 2017 Session 39: Interactive Presentations 3 9:00 a.m. - 11:00 a.m. Committee: Interactive Presentations

Investigation on Delamination of Copper/ Epoxy Mold Compound Specimens under Mixed Mode I/III Loading V. N. N. Trilochan Rambhatla and Suresh Sitaraman – Georgia Institute of Technology

Session Co-Chairs: Mark Eblen Kyocera America, Inc. Tel: +1-858-614-2537 Email: mark.eblen@kyocera.com

Design and Optimization of LowTemperature Ultrasonic Bonding of Cu-Sn Micro-Bumps for High-Density Interconnection Applications Qinghua Zeng, Yong Guan, Jing Chen, and Yufeng Jin – Peking University

Swapan Bhattacharya Engent Inc. Tel: +1-770-280-4259 Email: Swapan.bhattacharya@ engentaat.com

Chip-Scale SERF Atomic Magnetometer without Magnetic Shield Ling Lu and Jintang Shang – Southeast University

28

FE Simulation of Joint-to-Joint Variation of Temperature during ThermoCompression Bonding

Tz-Cheng Chiu National Cheng Kung University Tel: +886-6-2757575 Email: tcchiu@mail.ncku.edu.tw

Frank Wei Disco Japan Tel: +81-3-4590-1035 Email: frank_w@disco.co.jp Transmission Properties of HBM Interface on 2.1D System in Package using Organic Interposer Yutaka Uematsu and Nobuyuki Ushifusa – Hitachi; Hitoshi Onozeki – Hitachi Chemical The Use of Single Layer MIS in Modern Assembly Kohan Lin, Albert Lan, Mark Liao, and Boxiang Fang – Siliconware Precision Industries Co., Ltd. Electrical Characterization of MIM Capacitor Embedded in ThroughSubstrate Via (TSV) Ye Lin and Chuan Seng Tan – Nanyang Technological University Diffusion Barrier Effect of Ni-W-P and Ni-Fe UBMs During High-Temperature Storage Li-Yin Gao and Zhi-Quan Liu – Chinese Academy of Sciences; Li Liu, Jing Wang, Zhao-Xia Zhou, and Chang-Qing Liu – Loughborough University High-Reliability Challenges with Cu Wire Bonding for Automotive Devices in the AEC-Q006 JunHo Jeon, SungHo Jeon, SeokHo Na, TaeKyeong Hwang, Kwangmo Lim, and JuHoon Yoon – Amkor Technology Development of Die Attachment Technology for Power IC Module by Introducing Indium into Sintered NanoSilver Joint Chun An Yang and C. Robert Kao – National Taiwan University; Hiroshi Nishikawa – Osaka University Effect of Nickel-Coating Modified CNTs on the Dopant Dispersion and Performance of BGA Solder Joints Huayu Sun and Yan-Cheong Chan – City University of Hong Kong; Xiao Hu – HiSilicon Technologies; Fengshun Wu – Huazhong University of Science and Technology Small Event Probability Analysis of Manufacturing Problems with Numerous Input Variables using Advanced Uncertainty Propagation Analysis Hsiu-Ping Wei and Bongtae Han – University of Maryland Alternative 3D Small Form Factor Methodology of System in Package for IoT and Wearable Devices Application Mike Tsai, Albert Lan, Chi Liang Shih, Terence Huang, Ryan Chiu, S. L. Chung, J. Y. Chen, Frank Chu, Cheng Kai Chang, and Nicholas Kao – Siliconware Precision Industries Co., Ltd. First Demonstration of Photoresist Cleaning for Fine Line RDL Yield Enhancement by an Innovative Ozone Treatment Process for Panel Fan-out and Interposers Atul Gupta, Eric Snyder, Christiane Gottschalk, James Gunn, and Kevin Wenzel – MKS Instruments; Hao Lu, Yuya Suzuki, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology


Interactive Presentations: Thursday, June 1, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m. Assessing the Reliability of HighTemperature Solder Alternatives Maan Z. Kokash, Rajesh S. Sivasubramony, Jorge L. Then Cuevas, Angelo F. Zamudio, Thaer Alghoul, and Peter Borgesen – Binghamton University; Alfred A. Zinn, Randall M. Stoltenberg, Jerome Chang, Y. L. Tseng, and Dan Blass – Lockheed Martin High Performance Silver Alloy Bonding Wire for Memory Devices Tetsuya Oyamada, Tomohiro Uno, and Takashi Yamada – Nippon Steel & Sumitomo Metal; Daizo Oda – Nippon Micrometal Discussions of a Methodology for Determining Void Errors in Wafer Bonding and 3D Structures Mark Plemmons and William Kerr – Evergreen Enhancement Development of Liquid, Granule, and Sheet Type Epoxy Molding Compounds For Fan-Out Wafer Level Package Kenichi Ueno, Kazuhiro Dohi, Kazuyoshi Muranaka, Akira Nakao, and Yuki Ishikawa – Sanyu Rec Low Pressure Solid-State Bonding using Silver Preforms for High Power Device Packaging Jiaqi Wu and Chin C. Lee – University of California, Irvine Fabrication, Characterization and Comparison of FR4-Compatible Composite Magnetic Materials for HighEfficiency Integrated Voltage Regulators with Embedded Magnetic Core MicroInductors Mohamed Bellaredj, Sebastian Mueller, Anto Davis, Paul Kohl, and Madhavan Swaminathan – Georgia Institute of Technology; Yasuhiko Mano – Ibiden The Novel Failure Mechanism of the Polymer Ball Interconnected CBGA Under Board Level Thermal Mechanical Stress Jeffrey Lee and Cheng-Chih Chen – Integrated Service Technology, Inc. Development of Double Side Protection Process with Bump Support Film (BSF) and Backside Coating Tape for WLP Masanori Yamagishi, Keisuke Shinomiya, Tomotaka Morishita, Motoki Nozue, Akinori Sato, and Shinya Takyu – LINTEC Selective Laser Melting as an Alternative for Production of High-Temperature Power Electronic Substrates Aarief Syed Khaja and Joerg Franke – Friedrich Alexander University Design of Miura Folding Based MicroSupercapacitor Arrays with Higher Areal Densities as Foldable and Miniaturized Energy Storage Units Bo Song, Yun Chen, Kyoung-sik Moon, and C. P. Wong – Georgia Institute of Technology Assembly and Reliability Challenges for Next-Generation High-Thermal TIM Materials Chi-An Pan, Chi-Tung Yeh, Wei-Chun Qiu, RongZheng Lin, Liang-Yih Hung, Kong-Toon Ng, C. F. Lin, C. Key Chung, Don-Son Jiang, and C. S. Hsiao – Siliconware Precision Industries Co., Ltd.

Low-Temperature Curable Polyimide Film Properties and WLP Reliability Performance with Various Curing Conditions Steven Chen, Katch Wan, Chen An Chang, and Rick Lee – Siliconware Precision Industries Co., Ltd. Effects of Polymer Rebound on Crack-Free Acrylic based SnBi58 ACFs (Anisotropic Conductive Films) Joints during a Thermal-Compression Bonding Method Shuye Zhang and Kyung-Wook Paik – Korea Advanced Institute of Science and Technology Thursday, June 1, 2017 Session 40: Interactive Presentations 4 2:00 p.m. - 4:00 p.m. Committee: Interactive Presentations Session Co-Chairs: Ibrahim Guven Virginia Commonwealth University Tel: +1-804-827-3652 Email: iguven@vcu.edu Mark Poliks Binghamton University Tel: +1-607-727-7104 Email: mpoliks@binghamton.edu Nancy Iwamoto Honeywell Tel: +1-760-788-7109 Email: nancy.iwamoto@honeywell.com Jai Agrawal Purdue University Tel: +1-408-772-6727 Email: jaipagrawal@gmail.com Pad Cratering Based Failure Criterion for the Life Prediction of Board-Level Cyclic Bending Test Qiming Zhang, Jeffery C. C. Lo, and Shi-Wei Ricky Lee – Hong Kong University of Science and Technology An Accurate Dynamic Thermal Model for Electronic Parts and its Applications in System-Level Thermal Simulations An-Yu Kuo, C. T. Kao, and Xin Ai – Cadence Design Systems; Vijay Pandiyan – Future Facilities Equivalent Thermal Conductivity Model Based Full-Scale Numerical Simulation for Thermal Management in Fan-Out Packages Ningyu Wang, Yudan Pi, Wei Wang, and Yufeng Jin – Peking University Experimental and Finite Element Study about the Influence of Stress on the Electromigration Life of Solder Fei Su, Zheng Zhang, Qingyi Liu, Xiaoxu Pan, and Qizhi Wang – Beijing University of Aeronautics and Astronautics A Bugle Test to Investigate Mechanical Properties of Thin Adhesive Layer Pei Chen, Jinglong Sun, Tian Pan, and Fei Qin – Beijing University of Technology

Local Stress Analysis by Kossel Diffraction Applied on Flip Chip Structure Anne-Laure Lebaudy and Manuel Fendler – CEALeti; Raphaël Pesci – Ecole Nationale Supérieure des Arts et Métiers Study of Annular Copper Filled TSVs of Sensor and Interposer Chips for 3D Integration Cao Li and Peng Fei – Huazhong University of Science & Technology; Sheng Liu and Huai Zheng – Wuhan University On the Process-History Dependence of Package Mechanical Performance Mingji Wang, Lou Nicholls, MiNa Mo, MinJae Lee, Quan Pham, and Yong Song – Amkor Technology Investigations on the Pumping Behaviors of Copper Filler in TSV Fei Su and Xiaoxu Pan – Beijing University of Aeronautics and Astronautics Warpage Prediction Methodology of Extremely Thin Packages Peng Chen, Zhongli Ji, Yangming Liu, Anna Wu, Ning Ye, and Hem Takiar – SanDisk Design and Fabrication of MultiFrequency Antenna using Genetic Algorithms for 5G Applications VIncens Gjokaj, John Doroshewitz, and Premjeet Chahal – Michigan State University Cu-In-Microbumps for Low-Temperature Bonding of Fine-Pitch Interconnects Steffen Bickel, Iuliana Panchenko, Joerg Meyer, and Volker Neumann – Technical University Dresden; Wieland Wahrmund and M. Juergen Wolf – Fraunhofer IZM A Robust, Stretchable, Capacitive Strain Sensor Fabricated from Silver-Polymer Composite and Urethane Adhesive Todd Houghton, Jignesh Vanjaria, Thomas Murphy, and Hongbin Yu – Arizona State University Via-in-Trench: A Revolutionary PanelBased Package RDL Configuration Capable of 200-450 IO/mm/layer, an Innovation for More-than-Moore System Integration Fuhan Liu, Chandrasekharan Nair, Hao Lu, Rui Zhang, Hang Chen, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Atsushi Kubo and Tomoyuki Ando – Tokyo Ohka Kogyo; Kwon Sang Lee – Disco Corporation Simulation Analysis of a Conformal Patch Sensor for Skin Tension and Swelling Detection Ruiqi Lim, Ming-Yuan Cheng, Ramona Damalerio, Weiguo Chen, and Kwan Ling Tan – Institute of Microelectronics, A*Star Effect of Material Properties of Double Layer Non-Conductive Films (D-NCFs) on the Reflow Reliability of Ultra FinePitch Cu-Pillar/Sn-Ag Micro Bump Interconnection SeYong Lee, JiWon Shin, and Kyung-Wook Paik – Korea Advanced Institute of Science and Technology; Woojeong Kim and Taejin Choi – Doosan Corporation

29


Interactive Presentations: Thursday, June 1, 2:00 p.m. - 4:00 p.m and Friday, June 2, 8:30 a.m. - 10:30 a.m. Wafer-Level Micro Alkali Vapor Cells with Anti-Relaxation Coating Compatible with MEMS Packaging for Chip-Scale Atomic Magnetometers Yu JI and Jintang Shang – Southeast University

Electrically Testing Non-underfilled Flip Chip Assemblies- Impacts on Interconnect Integrity Antoine Cloutier and David Danovitch – Université de Sherbrooke; Benoit Foisy – IBM Corporation

Low-Temperature High-Throughput Assembly Technology for Transducer Array in Medical Imaging Applications Hoang-Vu Nguyen, Nu Bich Duyen Do, and Knut Aasmundtveit – University College of Southeast Norway

Effects of Anisotropic Conductive Films (ACFs) Gap Heights on the Bending Reliability of Chip-in-Flex (CIF) Packages for Wearable Electronics Applications Ji-Hye Kim, Tae-Ik Lee, Dal-Jin Yoon, Taek-Soo Kim, and Kyung-Wook Paik – Korea Advanced Institute of Science and Technology

Highly Efficient and Stable Quantum Dot Light Emitting Diodes Optimized by Micro-Packaged Luminescent Microspheres Kai Wang and Xiaowei Sun – Southern University of Science and Technology; Xiaobing Luo – Huazhong University of Science and Technology; Sheng Liu – Wuhan University An Experimental Magnesium Ion Battery Cell Made of Flexible Materials Todd Houghton, Gamal Eltohamy, and Hongbin Yu – Arizona State University Friday, June 2, 2017 Session 41: Student Interactive Presentations 8:30 a.m. - 10:30 a.m. Committee: Interactive Presentations Session Co-Chairs: Yang Liu IBM Corporation Tel: +1-914-945-2142 Email: yang3d@gmail.com Li Ming ASM Tel: Email: mli@asmpt.com Vaidyanathan Chelakara Ciena Corporation Tel: +1-613-670-2472 Email: cvaidyan@ciena.com Suresh K. Sitaraman Georgia Institute of Technology Tel: +1-404-894-3405 Email: suresh.sitaraman@me.gatech. edu Stress Analysis of Flexible Packaging for the Integration of Electronic Components within Woven Textiles Menglong Li, John Tudor, Russel Torah, and Steve Beeby – University of Southampton Signal Integrity Analysis of Silicon/ Glass/Organic Interposers for 2.5D/3D Interconnects Sumin Choi and Joungho Kim – Korea Advanced Institute of Science and Technology; Heegon Kim – Missouri S&T; Kiyeong Kim – Samsung Electronics Company, Ltd. A Study on the Fabrication of Electrical Circuits on Fabrics using Cu Pattern Laminated B-stage Adhesive Films for Electronic Textile Applications Kyung-Wook Paik – Korea Advanced Institute of Science and Technology

30

A Study on the Fine Pitch Flex-onFlex (FOF) Assembly using Flux Added Nanofiber Solder Anisotropic Conductive Films (ACFs) and Thermo-compression Bonding Method Ji-Soo Lee, Ji-Hye Kim, and Kyung-Wook Paik – Korea Advanced Institute of Science and Technology Infrared (IR) Soldering of Metallic Nanowires Jirui Wang, Fan Gao, and Zhiyong Gu – University of Massachusetts Lowell Highly Stretchable Electrical Conductive Composites Fabricated from Conducting Polymer Networks and Silver Nanostructures for Wearable Electronics Bo Song, Kyoung-sik Moon, and C. P. Wong – Georgia Institute of Technology Numerical and Experimental Study of Fan-out Wafer Level Package Strength Cheng Xu and Zhaowei Zhong – Nanyang Technological University; Won Kyoung Choi – STATS ChipPAC, Inc. Effects of Passivation Layer and Electroplating Parameters of Copper Film on Wafer Warpage During Thermal Process Gong Cheng, Heng Li, Weibo Zhang, Gaowei Xu, and Le Luo – Shanghai Institute of Microsystem and Information Technology Development of Mechanical Locking Micro-Anchor Structures for aQFN Package Application Yu-Lung Huang and Wei-Chih Lin – National Sun Yat-Sen University

Toughening Underfills by Stress-Absorbing Core-Shell Fillers Chia-Chi Tuan, Kyoung-Sik Moon, and Ching-Ping Wong – Georgia Institute of Technology Thermal Characteristic of Sn-MWCNT Nanocomposite Solder in LED Package Choong-Jae Lee, Jae-Jung Moon, Kwang-Ho Jung, and Seung-Boo Jung – Sungkyunkwan University An Evaluation of Effects of Molding Compound Properties on Reliability of Ag Wire Components Keisuke Yazawa – Purdue University; Carol Handwerker, John Blendell, Alexander Campbell, Wenhao Chen, Azzedin Jackson, and Matthew Parsons – Purdue Univesity; Peng Su – Juniper Networks A Nonlinear Transmission Line-Based Harmonic RF Tag for Buried Plastic Pipes Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Amanpreet kaur, and Premjeet Chahal – Michigan State University Numerical Analysis and Optimization of Thermal Performance of LED Filament Light Bulb through Phosphors Geometry Jie Liu, Huai Zheng, and Sheng Liu – Wuhan University; Chunlin Xu – Huazhong University of Science and Technology Effective and Efficient Modeling of Differential Vias Using Semi-Empirical Approach Fanghui Ren – Oregon State University; Kevin Cai, Chunchun Sui, Jayaprakash Balachandran, and Bidyut Sen – Cisco Systems, Inc. Design of Low-Profile Integrated Transformer and Inductor for SubstrateEmbedding in 1-5kW Isolated GaN DC-DC Converters Haksun Lee, Vanessa Smet, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology A Stretchable Capacitive Strain Sensor Based on a Novel Polymer Composite Blend Todd Houghton, Jignesh Vanjaria, Thomas Murphy, and Hongbin Yu – Arizona State University

Investigation of Shear Strength and Fracture Behavior for Cu-Sn Full IMCs Solder Joints with Different Proportion of Cu3Sn Peng Yao, Xiaoyan Li, Xiaobo Liang, Yang Li, and Fengyang Jin – Beijing University of Technology

3D Glass Package for Miniaturized Automotive Image Sensing System for Collision Avoidance Daniel Struk, Peter Hesketh, Chintan Buch, Klaus Wolter, and Rao Tummala – Georgia Institute of Technology

Reliability of Cu/NiFe and Cu/ Ni Metaconductor Devices for RF Applications Timothy Clingenpeel and Yong-Kyu Yoon – University of Florida

Temperature Stabilization of Pulsed Devices using IMT Thin Films Michael Fish, Yangang Liang, Xiaohang Zhang, Patrick McCluskey, and Ichiro Takeuchi – University of Maryland

A New Fan-Out Package Structure Utilizing the Self-Alignment Effect of Molten Solder to Improve the Die Shift and Enhance the Thermal Properties Hwan-Pil Park, Jae-Yong Park, Gwancheol Seo, and Young-Ho Kim – Hanyang University

Miniaturization of Planar Packaged Inductor using NiZn and Low-Cost Screen Printing Technique Colin Pardue, Mohamed Bellaredj, Anto Davis, and Madhavan Swaminathan – Georgia Institute of Technology


2017 TECHNOLOGY CORNER EXHIBITS Today’s hi-tech companies are being very selective in choosing the conferences and trade shows where they will exhibit their products and services. Each year more companies have determined that ECTC provides the opportunity to identify superior prospects. The primary reason is that the engineers and managers who attend ECTC hold decisionmaking positions at the world’s leading electronics equipment and component manufacturers. The attendees are attracted by ECTC’s strong technical program. Authors in the field believe that ECTC offers the best forum for presenting their work. Exhibit hours will be from 9:00 AM to Noon and 1:30 to 6:30 PM on Wednesday, May 31, and 9:00 AM to Noon and 1:30 to 4:00 PM on Thursday, June 1. All booths in the exhibit hall have been reserved, with this year having a record number of Exhibitors. Following is a list of exhibitors as of Feb. 1, 2017. The Exhibit Brochure, a current exhibitor list, and a booth layout showing the available booths can be found on the ECTC web site at www. ectc.net under the heading Exhibits. If you need additional information or have questions, call Joe Gisler at +1-480-288-6660, or email gislerhj.ectc@mediacombb.net. 

3D Systems Packaging Research Center (PRC) A T & S Americas Advance Reproductions Corp. AGC AI TECHNOLOGY, Inc. Akrometrix LLC Alpha Novatech Inc. AMICRA Microtechnologies GmbH Amkor Technology, Inc. ASE Group Binghamton Univ. S3IP Cadence Design Systems Inc. Camtek USA Inc. Canon USA CEA-Leti CMP CPS Technologies Corp. CST of America, Inc. CVInc Deca Technologies Disco Hi-Tec America, Inc. Dow Electronic Materials DOWA International Corp. Dynaloy, a subsidiary of Eastman Chemical Company EV Group ficonTEC USA Finetech Flip Chip International Fraunhofer CAM Fraunhoffer Institute for Reliability and Microintegration Fujifilm Electronic Materials Co. GLOBALFOUNDRIES HD Microsystems Henkel Electronic Materials LLC Heraeus Materials Technology

HOW TO REGISTER FOR ECTC By Internet: Submit your registration electronically via www.ectc.net. Your registration must be received by the cutoff date, May 4, 2017, to qualify for the early registration discounts. You may contact our registration staff at lrenzi@renziandco.com for additional information. Payment can be made by Visa, MasterCard, or American Express.

Hitachi Chemical Co. Huntsman Advanced Materials i3 Electronics IBM Canada IEN Georgia Tech INSIDIX Interconnect Systems, Inc. Invensas JSR Micro, Inc. Kulicke & Soffa Pte. Ltd Kyocera America, Inc. Lasetec Lintec of America LPKF Laser Malico Inc. Mentor Graphics Micross Advanced Interconnect Tech. Mini-Systems, Inc. (MSI) Mitsui Chemicals America MRSI Systems Inc. Nagase & Co., Ltd. NAMICS Technologies, Inc. NANIUM, S. A. Neu Dynamics Nikon Metrology, Inc. Nitto Inc. Nordson DAGE NTK Technologies Ntrium Inc. Ormet Circuits, Inc. PAC TECH USA Palomar Technologies Panasonic Corp, Automotove and Industrial Panasonic Factory Solutions of America Plasma-Therm LLC Promex Industries Inc. PURE TECHNOLOGIES

QualiTau Quik-Pak Royce Instruments, LLC Samtec Inc. Sanyu Rec SavanSys Solutions LLC Schott North America Semiconductor Equipment Corporation Senju Comtek Corp. SET - Smart Equipment Technology Shenmao America Shin-Etsu MicroSi, Inc. Shinkawa USA Shinko Electric America Sonoscan SPTS Technologies STATS ChipPAC Taiyo Ink Tatsuta Wire and Cable TechSearch International, Inc. Tecnisco Ltd. Teikoku Taping Systems ThreeBond International Tohoku Microtec Co. Tokyo Ohka Kogyo Co., Ltd. Toray International America, Inc. Towa USA Corp. Tresky AG Unisem Group Unity SC XYZTEC Yield Engineering Yole Developpement Zuken Inc. Zymet, Inc.

Hotel Reservations 1) Contact The Walt Disney World Swan and Dolphin Resort at +1- 888-828-8850. (Reference the ECTC Conference to receive the conference rate of $189/night. In addition, please request your room be reserved in the Walt Disney World Dolphin Resort as the Swan and Dolphin are two separate buildings.) Walt Disney World Swan and Dolphin Resort, 1500 Epcot Resorts Boulevard, Lake Buena Vista, FL 32830 or … 2) Log onto www.ectc.net and click on the Location tab near the top of the page to find a special online hotel registration link. The reservation cutoff is Friday, May 5, 2017. All reservations made after the cutoff date of Friday, May 5, 2017, at 5pm ET will be accepted on a space and rate available basis. Note about Hotel Rooms Attendees should note that only reputable sites should be used to book a hotel room for the 2017 ECTC. Be advised that you may receive emails about booking a hotel room for ECTC 2017 from 3rd party companies. These emails and sites are not to be trusted. The only formal communication ECTC will convey about hotel rooms will come in the form of ECTC e-blasts or ECTC emails from our Executive Committee. ECTC’s only authorized site for reserving a room is through our website (www.ectc.net). You may, however, use other trusted sites that you have personally used in the past to book travel. Please be advised, there are scam artists out there, and if it’s too good to be true, it likely is. Should you have any questions about booking a hotel room, please contact ECTC staff at: lrenzi@renziandco.com

31


67th Electronic Components & Technology Conference 2017 ECTC CONFERENCE REGISTRATION INFORMATION Conference Registration

Advance Registration

Door Registration

US$730

US$835

IEEE Member

Attendee (full ECTC conference)

Attendee (Joint ECTC + ITHERM conferences)

$945

$1100

Attendee One-Day Registration

$550

$550

Speaker or Chair (full ECTC conference)

$605

$730

Speaker or Chair One-Day Registration

$415

$415

Non-IEEE Member

Attendee (full ECTC conference)

$920

$1025

Attendee (Joint ECTC + ITHERM conferences)

$1050

$1310

Attendee One-Day Registration

$550

$550

Speaker or Chair (full ECTC conference)

$605

$730

Speaker or Chair One-Day Registration

$415

$415

Student

Attendee or Speaker (full conference)

$315

$315

Access to Exhibits Only (not attending conference)

$25

$25

Exhibit Booth Attendant Professional Development Courses (PDCs) Note: all PDCs include a luncheon

$0

$0

Exhibits

IEEE Member

Full PDC (both a.m. and p.m.)

$605

$710

Single PDC (a.m. or p.m.)

$420

$500

Non-IEEE Member

Full PDC (both a.m. and p.m.)

$655

$710

Single PDC (a.m. or p.m.)

$470

$500

Student

Full PDC (both a.m. and p.m.) or Single PDC

$130

$130

Extra Proceedings

$100

$100

Extra Luncheon Tickets

$65

$65

Cancellation Fee

$50

$50

Other Registration Options

Please log onto www.ectc.net/registration to register for the 2017 ECTC. There will be no refunds or cancellations after May 4, 2017. Please note that a $50 cancellation fee will be in effect for all cancellations made on or prior to May 4, 2017. Substitutions can be made at any time. For additional information about registration or ECTC please contact us at: Renzi & Company, Inc. • Phone: +1-703-863-2223 • Email: renziandco2@gmail.com *If you join IEEE BEFORE you register for the 2017 ECTC, you can save on registration fees and get free add-on membership to the Components, Packaging and Manufacturing Technology (CPMT) Society for one year! To take advantage of this offer, simply go to: http://www.ieee.org/go/CPMT_professional At destination, create your IEEE web account. Once complete, proceed to the Shopping Cart and enter CPMT2017FREE in the promotion code box. Click “Apply” and the Shopping Cart will be updated to show the discount. Use your new IEEE membership ID number to register for ECTC at the discounted IEEE Member Rate. *Non-IEEE members can join IEEE and save $100 or more on ECTC registration and receive CPMT Society membership free for 2017. IEEE members can join the CPMT Society free for the remainder of 2017 with ECTC registration.

32


CONFERENCE SPONSORS

Gold Gala Sponsors www.amkor.com

www.cadence.com

www.decatechnologies.com

www.dowelectronicmaterials.com

www.lintec-usa.com/

www.nanium.com

www.pactech.com

www.spts.com

www.unity-sc.com/en/

Silver Gala Sponsors

www.appliedmaterials.com

www.ibm.com

www.micron.com

www.spil.com.tw

www.suss.com

www.veeco.com/technologiesandproducts/ precisionsurfaceprocessingsystems

www.zeiss.com/microscopy/int/solutions/ manufacturing-assembly.html

Special & Program Sponsors

www.aseglobal.com

www.brewerscience.com

www.lamresearch.com

www.yieldengineering.com

33


CONFERENCE SPONSORS Wednesday Luncheon Sponsor

Friday Luncheon Sponsor

Badge Lanyard Sponsor

www.aseglobal.com

www.statschippac.com

www.hdmicrosystems.com

Tote Bags Sponsor

Intel Student Paper Sponsor

www.emd-performance-materials.com

www.intel.com

Internet Sponsor

Thumb Drive Sponsor

www.camtek.com

www.spil.com.tw

Refreshment Break Sponsors

www.agcem.com

www.atotech.com

www.fujifilmusa.com

www.jsrmicro.com

www.microsoft.com

www.qualcomm.com

www.rudolphtech.com

www.inemi.org

www.namics.co.jp/e/

www.tok.co.jp/eng

Media Sponsors Official Media Sponsor

www.chipscalereview.com

Additional Media Sponsors

www.i-micronews.com

34

www.3dincites.infoneedle.com

www.circuitassembly.com

www.electronics-cooling.com

www.electronics protectionmagazine.com

www.magneticsmagazine.com

www.memsjournal.com

www.meptec.com

www.semiconductor packagingnews.com

www.electroiq.com


CONFERENCE OVERVIEW May 30, 2017 Morning Professional Development Courses 8:00 a.m. - 12:00 Noon

1. Achieving High Reliability of Lead-Free Solder Joints – Materials Considerations 2. Wafer Level-Chip Scale Packaging 3. LED Packaging, System, and Reliability Considerations 4. Future of Device and Systems Packaging: Strategic Technologies, Manufacturing Infrastructure, and Applications 5. Polymers and Nanocomposites for Electronic and Photonic Packaging 6. Integrated Thermal Packaging and Reliability of Power Electronics 7. Fundamentals of Electrical Design and Fabrication Processes of Interposers, including their RDLs 8. Introduction to Mechanics Based Quality and Reliability Assessment Methodology 9. Thermo-Electric Coolers: Characterization, Reliability, and Modeling

Afternoon Professional Development Courses 1:15 p.m. - 5:15 p.m.

10. Flip Chip Technologies 11. Package Failure Analysis - Failure Mechanisms and Analytical Tools 12. 3D IC Integration and 3D IC Packaging 13. Flexible Hybrid Technologies 14. Polymers for Electronic Packaging 15. Emerging Interconnect and System Integration Technologies 16. Package Failure Mechanisms, Reliability, and Solutions 17. Ageing of Polymers and the Influence on Microelectronic Package Reliability 18. Thermo-Electrical Co-Design for 3D Integration

Technical Subcommittee Special Session 10:00 a.m. - 11:30 a.m. “Material and Package Reliability Needs/Challenges for Harsh Environments” ECTC Special Session 2:00 p.m. - 3:30 p.m. “Flexible Hybrid Electronics – Electronics Outside the Box”

ECTC Panel Session 7:30 p.m. - 9:00 p.m. “Panel Fan-Out Manufacturing: Why, When, and How?” May 31, 2017 Technical Sessions 8:00 a.m. - 11:40 a.m. 1. Fan-Out Packaging Process and Integration 2. TSV Process, Characterization and Applications 3. Flip Chip Assembly 4. Advanced Substrates and Integrated Devices 5. Emerging Sensors and Microsystems Packaging 6. 5G, mmWave and Beyond

Interactive Presentation Sessions 37 & 38 9:00 a.m. - 11:00 a.m. 2:00 p.m. - 4:00 p.m.

CPMT Women’s Panel and Reception 6:30 p.m. - 7:30 p.m. “Emotional Intelligence (EI) Link to Successful Leadership” ECTC Plenary Session 7:30 p.m. - 9:00 p.m. “Packaging for Autonomous Vehicle Electronics” June 1, 2017 Technical Sessions 8:00 a.m. - 11:40 a.m.

13. Interconnect Advances in FO & WLP 14. Heterogeneous Integration 15. Flip Chip and Embedding in Substrates 16. 3D Materials and Processing 17. Materials and Processes for Flexible and Wearable Devices 18. Warpage, Electromigration and Mechanical Characterization

Technical Sessions 1:30 p.m. - 5:10 p.m. 7. Fan-Out Packaging Materials and Passives 8. Singulation Process Developments 9. Fine Pitch Flip Chip Process Technologies 10. Harsh Environment Interconnect Reliability 11. Mechanical Modeling and Characterization of Interposers and Interconnections 12. Advanced Optical Components and Modules

Interactive Presentation Sessions 39 & 40 9:00 a.m. - 11:00 a.m. 2:00 p.m. - 4:00 p.m. Technical Sessions 1:30 p.m. - 5:10 p.m.

CPMT Seminar 8:00 p.m. - 9:30 p.m. “3D Printing Tools, Technologies and Applications” June 2, 2017 Technical Sessions 8:00 a.m. - 11:40 a.m. 25. Characterization and Reliability of Fan-Out & WLP 26. 3D Integration Processing and Reliability 27. Advances in Thermal Compression and Wirebonding 28. Advanced Materials for Reliability Improvement 29. Warpage Control and Substrates 30. RF Components and Module Integration

Student Interactive Presentations Session 41 8:30 a.m. - 10:30 a.m. Technical Sessions 1:30 p.m. - 5:10 p.m.

19. Recent Advances in FOWLP Technology 20. MEMS and Sensor Technologies 21. 3D Cu-Cu and Micro Bump Bonding Technologies 22. Solder Joint & Interconnect Reliability, Characterization and Modeling 23. Additive Manufacturing and Panel-Level Packaging 24. Novel Methods to Assess Reliability

31. Auto Electronics Packaging and Power Modules 32. Reliability Challenges in 2.5D/3D Interconnect 33. Advanced Bonding and Soldering Technology 34. Waveguide Devices and Chipto-Fiber Packaging 35. Thermomechanical and Thermal Characterization 36. Advances in Signal and Power Integrity

Session Summary by Interest Area 3D/TSV Topics S2, S16, S21, S26, S32

Interconnections S2, S9, S13, S21, S27, S32

Advanced Packaging S1, S7, S14, S15, S20, S26, S31

Materials & Processing S4, S16, S19, S28, S33

Applied Reliability S10, S24, S25, S32

Thermal/Mechanical Simulation & Characterization S11, S18, S22, S35

Assembly & Manufacturing Technology S3, S8, S14, S29 Emerging Technologies S5, S17, S23 High-Speed, Wireless & Components S6, S30, S36

Optoelectronics S12, S34 Interactive Presentations S37, S38, S39, S40, S41

35


FIRST CLASS U.S. POSTAGE

PAID

RALEIGH, NC PERMIT NO. 2172

IEEE CPMT 445 Hoes Lane, Piscataway, NJ 08854-4141 USA Mailroom: If the person on this label is no longer employed at your company, please route this information brochure to his/her replacement or department manager. Route to:_______________________________________ _______________________________________ Attn: Engineers, scientists and technical managers

Sponsored by:

Official Media Sponsor:

Media Sponsors:

Advance Registration until May 4, 2017 – Hotel Reservations until May 5, 2017 For more information, visit: www.ectc.net

Mark Your Calendar for ECTC 2018

67th ECTC Advance Program  
Read more
Read more
Similar to
Popular now
Just for you