Name: Solution COMP228 ID: Midterm Answer All Questions in the Spaces Provided
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Identify the layer of abstraction to which the following components belong. Cache: control Sequential Circuit: logic Program Counter: machine control ALU: Control Unit: control
Moore’s law affects most but not all of the following aspects of a computer system. Identify those that it does not affect. Explain why. (i) clock rate, (ii) memory size, (iii) disk size, (iv) ISA, (v) control layer details, (vi) parallel processing. Answer: Clock rate, memory size increases because of scaling (miniaturization of transistor). ISA is affected with increases in word size and memory size, and the complexity of instructions. Control layer (implementation) of the ISA employs more parallel processing and buffering, as cost of transistors is correspondingly reduced. Disk size is not directly affected by the Moore’s law but by the disk technology itself.
Explain the role of a bus arbiter and the main disadvantages of daisy-chained arbitration. Answer: A bus arbiter is responsible to arbitrate among all competing bus masters by selecting every time a single master to use the bus (when it becomes available). Daisy-chained arbitration has two drawbacks: the acknowledge signal propagates down the chain sequentially and may take more time, and a fixed priority is assigned among the devices in the chain, potentially leaving those down the chain suffering from starvation or unresponsiveness.
There are three distinct factors that affect the execution time of a program. What are they? Identify at which layers of computer abstraction these factors arise. Answer: (i) number of instructions executed: depends on ISA and programming/translation skills. (ii) average number of cycles per instruction: depends on the control layer implementation details (how much parallelism and hence time needed in executing an instruction). (iii) clock rate: depends on technology and control layer implementation (how much work needs to be done in a clock cycle).
Consider a 24-bit computer with two registers, A and B. Suppose A = FFFFF0 and B = 202020 (in hex).
Perform A – B (in hex or binary). Indicate the C and O flags generated. Answer: FFFFF0 + DFDFE0 DFDFD0 C = 1, O = 0 What is the decimal equivalent of the 2’s complement stored in A? Answer: FFFFF0 = - (000010) = - 16 = - 24
If we perform A = A + A (replacing the content of A by A + A), what is the maximum number of times that we can repeat doing this without generating an overflow? Explain why. Answer: Every time A is added to itself, its value is doubled. Suppose we repeat this k times. The value of A becomes – (24 ) * 2k . With 24 bits, the most negative (smallest) integer that can be stored is – 223. So k + 4 ≤ 23 or k ≤ 19.
Can the content in B be ASCII characters? Explain why. Answer: Yes, since the most significant bit of each byte is 0. Indeed, B contains three ASCII ‘space’.
Suppose the Hamming SEC code is used in the system. Give the resulting encoded word for the data in B. Identify the parity bits clearly in your answer. Answer: Noticing 202020 contains three 1-bits at encoded word bit positions 10 (01010), 19 (10011) and 27 (11011). 1
The rest of the data bits are all 0.
1 0 2 1
Draw the Karnaugh map or truth table of the following Boolean function f with three input variables <A, B, C>. The function f is true (i.e. 1) if and only if the integer corresponding to <A, B, C> is even. For example, <0, 0, 0> = 0, and <0, 1, 0> = 2 are even integers. Answer: BC A 00 01 11 10 0 1 0 0 1 1
Implement the function f in 3(a) using a minimum number of NAND gates. Show the circuit/logic diagram. f = C’ It does not require any logic gate for implementation.
Consider the following sequential circuit:
The combinational function f = AB’ + A’B. [A’ denotes not-A] Suppose the initial state <Q1, Q2, Q3> is <0, 0, 0>. What is the next state that can follow if B = 0? If B = 1? Hence draw the state diagram of the circuit assuming the initial state is <0, 0, 0>. [Note: you should allow input B to be either 0 or 1 in the analysis.] [The max mark of this problem is changed from 6 to 4] Answer: B = 0: <0,0,0> Æ <0,0,0> B = 1: <0,0,0> Æ <1,0,0> 0
0 <1,1,0> 0 <1,0,1>
1 1 0
4. The standard 1-address instruction format contains two fields: opcode and address, as shown below. opcode x bits
address y bits
For an ISA that contains 200 distinct opcodes and a memory size as large as 16M locations, determine the minimum values of x and y. Answer: Opcode needs 8 bits (28 = 256) Address needs 24 bits
If the word size (number of bytes per memory location) is equal to the size of an instruction (in bytes), determine the word size. Answer: Word size = 8 + 24 bits = 4 bytes
The memory system is implemented using RAM chips each of size 4M x 1 byte. Determine the number of RAM chips needed in the implementation. Draw a diagram showing the 2-D layout of these chips. Be sure to include the address decoding and chip selection parts. Answer: 16M x 4 bytes / 4M x 1 byte leading to 4 x 4 array of 16 chips Diagram should show: 24 address bits, two of which are used to pass through a 2-to-4 decoder whose outputs are used to select the four columns of chips. Each row of chips provides 1 byte of data. Each access involves all 4 rows.
If the memory if 4-way (low-order) interleaved, and the processor wishes to access memory locations 0, 2, 4, 6, â€Ś.1022. How many memory banks can be simultaneously accessed? Answer: 2 (location 0 at bank 0 and location 2 at bank 2, subsequently, this repeats for both banks for location 4, 6 and so on).
Name: Solution (d) Can the content in B be ASCII characters? Explain why. Answer: Yes, since the most significant bit of each byte is 0. Ind...