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SUMMARY OF ACADEMIC PROJECTS (SPRING 2009-FALL 2009)

SETIAWAN SOEKAMTOPUTRA

MASTER OF SCIENCE IN COMPUTER ENGINEERING CANDIDATE ILLINOIS INSTITUTE OF TECHNOLOGY EXPECTED DECEMBER 2010

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CONTENTS • 32‐bit Pipelined CPU with Multiplier Accumulator and Pipeline Optimization • Simple MC68000-based Monitor Program • High-Performance Pipelined MIPS Processor Design • Mesh-like Network on Chip Prototype Design • Ring-like Network on Chip Prototype Design • Small Office Network Design Prototype • Ongoing Projects (Spring 2010)

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32‐BIT PIPELINED CPU WITH MULTIPLIER ACCUMULATOR AND PIPELINE OPTIMIZATION • Class: VLSI Design • instructor: Prof. Ken Choi

• Requirements/Specifications • Modify existing multiplier functional unit into multiplier with accumulator unit in an existing CPU design • Apply pipeline to optimize the new functional unit

• Hardware Description Language • Verilog

• Tools • Synopsys Design Compiler • Cadence’s SimVision and SOC Encounter • Mentor Graphic’s Modelsim 3


32‐BIT PIPELINED CPU WITH MULTIPLIER ACCUMULATOR AND PIPELINE OPTIMIZATION (cont’d) • Block Diagram of the functional unit

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32‐BIT PIPELINED CPU WITH MULTIPLIER ACCUMULATOR AND PIPELINE OPTIMIZATION (cont’d) • Provided: • Multiplier accumulator block diagram • Simple CPU design written in verilog • All required tools

• Implementation • Construct fore-mentioned unit in verilog and modify the design to fit new unit • Apply numbers of registers for pipelining

• Design functionality Test • Verify in sumulation that function F= (-10)* 5 + (-60)*2 + (-60)*8 outputs the correct result

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32‐BIT PIPELINED CPU WITH MULTIPLIER ACCUMULATOR AND PIPELINE OPTIMIZATION (cont’d) • Results

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32‐BIT PIPELINED CPU WITH MULTIPLIER ACCUMULATOR AND PIPELINE OPTIMIZATION (cont’d) • Additional Analysis Result • Finding the maximum frequency • Expected maximum frequency of the design: 58 MHz • Frequency vs. area vs. power consumption

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SIMPLE MC68000-BASED MONITOR PROGRAM • Class: Microprocessor • instructor: Dr. Jafar Saniie

• Requirements/Specifications • Construct a simple monitor program for MC68000 processor that allows user to execute common memory and register accesses, basic exception handlers.

• Language • 68000 assembly language

• Tools • Easy68k Editor/Assembler/Simulator

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SIMPLE MC68000-BASED MONITOR PROGRAM (cont’d) • Monitor program flowchart

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SIMPLE MC68000-BASED MONITOR PROGRAM (cont’d) • Monitor program system diagram

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SIMPLE MC68000-BASED MONITOR PROGRAM (cont’d) • Results (partial of 17 commands made) Register display

Memory display

Command interpreter

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HIGH-PERFORMANCE PIPELINED MIPS PROCESSOR DESIGN • Class: Computer Architecture • instructor: Prof. Jia Wang

• Requirements/Specifications • Design a MIPS processor with pipeline, data forwarding, and hazard handling capabilities

• Language • VHDL

• Tools • Modelsim PE 6.5 • MARS 3.6 MIPS Simulator

• Provided: • Data memory unit design • Testbench code 12


HIGH-PERFORMANCE PIPELINED MIPS PROCESSOR DESIGN (cont’d) • MIPS Architecture

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HIGH-PERFORMANCE PIPELINED MIPS PROCESSOR DESIGN (cont’d) • Test program

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HIGH-PERFORMANCE PIPELINED MIPS PROCESSOR DESIGN (cont’d) • Result

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MESH-LIKE NETWORK ON CHIP PROTOTYPE DESIGN • Class: Hardware/Software Co-design (Project 2) • instructor: Prof. Jia Wang

• Requirements/Specifications • Build a simple mesh-like NoC architecture • Verify the correctness of node-to-node communication

• Language • SystemC

• Tools • Microsoft Visual C++

• Provided: • Ring-like NoC architecture design codes

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MESH-LIKE NETWORK ON CHIP PROTOTYPE DESIGN (cont’d) • Simple NoC Architecture

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MESH-LIKE NETWORK ON CHIP PROTOTYPE DESIGN (cont’d) • Results • Generated packets

• Result shows packets are delivered

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MESH-LIKE NETWORK ON CHIP PROTOTYPE DESIGN (cont’d) • Results • Delays due to the fact that only one packet is delivered to processing element PE at a time

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RING-LIKE NETWORK ON CHIP PROTOTYPE DESIGN • Class: Hardware/Software Co-design (Project 1) • instructor: Prof. Jia Wang

• Requirements/Specifications • Extend two-node ring NoC architecture design into three nodes • Create new function for the new node

• Language • SystemC

• Tools • Microsoft Visual C++

• Provided: • Two-node Ring-like NoC architecture design codes 20


RING-LIKE NETWORK ON CHIP PROTOTYPE DESIGN (cont’d) • Three-node NoC System Diagram

• Third node function (called PE_dumpbox) • It receives all packets that cannot be processed by the destination processing unit due to overloading in the network 21


RING-LIKE NETWORK ON CHIP PROTOTYPE DESIGN (cont’d) • Results • Overload in Router 1 network buffer

• 3rd processing unit PE_dumpbox receives packet

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SMALL OFFICE NETWORK DESIGN PROTOTYPE • Class: Intro to Computer Networks • instructor: Dr. Tricha Anjali

• Requirements/Specifications • Propose a prototype of 2-story small office computer network capable of serving 20 users with three department LANs, four servers and wireless Internet

• Language • N/A

• Tools • Microsoft Visio

• Provided: • None 23


SMALL OFFICE NETWORK DESIGN PROTOTYPE (cont’d) • Proposed configurations • IP address allocation

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SMALL OFFICE NETWORK DESIGN PROTOTYPE (cont’d) • Proposed configurations • Design Topology

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SMALL OFFICE NETWORK DESIGN PROTOTYPE (cont’d) • Office Layout

2nd floor

1st

floor

Colored arrows show how cables are managed 26


ONGOING PROJECTS Spring 2010

Running Opensparc T1 architecture on an FPGA Instructors: Prof. Jafar Saniie and Prof. Erdal Oruklu

Peer-to-Peer Distributed System Design Instructor: Prof Zhiling Lan


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[ECE-IIT-Chicago] Summary of My Academic Projects  

Created by: Setiawan Soekamtoputra M.S. in Computer Engineering Candidate Illinois Institute of Technology, Chicago, IL