Abstracts Gate Level Power Reduction in Deeply Scaled CMOS Technology (ENGR 498.19) Henrique Ribeiro Flores Instructor: Kyuwon Ken Choi, Ph.D. The recent advances on electronic devices have made necessary the power consumption to bedecreased, since power storage solutions tend to be more expensive. Then the objective of thisproject is to minimize the total power of CMOS (Complementary Metal-Oxide SemiconductorCircuits). This is done through the search for the optimum value for the following parameters ofthe transistor: Power Supply (Vdd), Threshold Voltage (Vth) and Transistor Width (W), for eachgate that meets the maximum delay condition while achieving minimum power dissipation. Thisstrategy is based on the observation that power consumption and delay are monotonic functions ofVdd, Vth and W individually, other parameters being fixed.
Gate Level Power Reduction in Deeply Scaled CMOS Technology (ENGR 498.19) Karlson Tellicio Bezerra Instructor: Kyuwon Ken Choi, Ph.D. The objective of this project is to minimize the total power consumption of CMOS (Complementary Metal-Oxide Semiconductor Circuits). This is done through the search for the optimum value for the following parameters of the transistor: Power Supply, Threshold Voltage and Transistor Width. We have applied an algorithm in some circuits to analyze its delays within the many signal paths. The result was an average decrease of around 30% in the total power. Also we could notice a small increase in the final delay.
Leakage Power Reduction at Circuit Level (ENGR 498.19) Gustavo Jose Bernardes Dos Santos Instructor: Kyuwon Ken Choi, Ph.D.
Hardware, Software & Communications R&D
This project is part of the Design Issues in Mobile Applications research as a way to apply the knowledge acquired during the term and the lab sections previously studied. With this knowledge, this project goal is to evaluate two ways to reduce power consumption at circuit level. The development of new technologies is challenged to advance in fast pace. Each new generation of microprocessor requires better performance, higher clock speeds, and smaller process technologies. However, it comes with a high cost in power consumption, turning it into a primary concern for new microprocessor designs. In order to reduce power consumption, there are techniques that can be implemented in the system, register-transfer, gate, circuit, and technology levels of the VLSI design. In the circuit level, one can apply techniques to reduce both the dynamic and static power. The dynamic power is consumed when the system is in operation, switching the signal. On the other hand, static power is consumed when the system is in steady state. This last one occurs due to the leakage current through the transistor in idle mode and it is the object of study of this work that compare some techniques to reduce the leakage power consumption at circuit level.
Leakage Power Reduction by Forced Stack & Power Gating at Circuit Level for Mobile Applications (ENGR 498.19) Diego Henrique Carvalho Andrade Instructor: Kyuwon Ken Choi, Ph.D. The development of new technology is required to advance. However, advances in performance, speed, and size come with a high power consumption. Scaling down demands to decrease threshold voltage and results in an exponential increase in leakage power consumption. One alternative for achieving lower power consumption is to apply techniques for reducing static power consumption at the circuit level. We analyze the Forced Stack method and MTCMOS Power Gating method for diminishing the sub threshold leakage current and the leakage power. The techniques evaluated achieve the goal, however, there is a trade-off between power consumption and delay to be considered.
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