CONFERENCE REPORT I ISLC
Figure 1. Intel’s hybrid III-V/silicon laser process begins by taking a silicon wafer with a silicon-dioxide layer and defining a waveguide and a grating using deep-UV lithography. Oxygen plasma activation of the wafer follows, along with the bonding of InP chiplets to silicon. The bulk InP is removed to leave behind just the active region, before a III-V mesa is etched and the laser contacts added. The final step involves passivating regions of the mesa with hydrogen-ion implantation to leave a current channel in the centre that overlaps with the optical mode.
explained that the company’s 100 Gbit/s to 400 Gbit/s transceivers are now being produced in high volume for ethernet-compliant products. These transceivers are based on front-plate pluggable optics and operate at an energy efficiency of 30 pJ/bit. “In these products, the optics is still very far away from the central Ethernet switch,” remarked Huang. “In 2020, we had a demonstration of so-called copackaged optics, in which a photonic engine capable of 1.6 terabits-per second is co-packaged with the switch core,” remarked Huang. This is said to bring the optics much closer to the photonics. With this architecture, optical engines could run at a total data rate of up to 3.2 Tbit/s, while drawing less than 15 pJ/bit. Looking further ahead, Intel anticipates a time when photonics will be united with the package where the processor sits, using an optimised optical interface. This architecture will operate at a total data rate that could be as high as 16 Tbit/s, and have an energy efficiency well below 5 pJ/bit. “In order to reach the bandwidth density and energy efficiency needed to make this happen, we utilise wavelength-division multiplexing,” revealed Huang. This approach, similar to that employed in long-haul links, exploits the resonance of silicon micro-ring modulators to select specific wavelengths. At the receiver, a similar approach can be employed to separate the various wavelengths transmitted down the fibre and extract encoded data.
Intel produces its laser by forming a waveguide and a grating on a 300 mm silicon wafer with a silicondioxide layer, and then adding an InP chiplet that is subsequently processed (see Figure 1 for details). To define the laser’s emission wavelength, Intel adjusts the dimensions of the grating. For the 8 channels deployed in the latest generation of technology, there is a 200 GHz spacing, equating to a difference in the grating period between adjacent laser channels of just 0.2 nm. “This is difficult, but something that is achievable with our deep UVlithography,” remarked Huang. He and his co-workers have provided a proof-ofconcept transmitter. “Only a single indium-phosphide chiplet is used to fabricate all eight lasers, and each laser can be controlled individually,” explained Huang. An 8-channel transmitter is formed by combining the output from the eight lasers with three stages of multimode interferometer, formed in silicon. This is a relatively easy way to combine eight channels into four, then two, and finally just one. However, it does incur a power penalty of around 3 dB at each stage. With this approach, the team have fabricated a transmitter with 8 wavelengths spaced apart by 200 GHz ± 13 GHz, centred at around 1305 nm. Driving each laser sequentially with 80 mA produces lasing peaks with a side-mode suppression ratio (SMSR) of 54 dB and an output power of around 1 mW. “When we turn on all eight laser together, we see a number of side peaks on either side of the eight main WWW.COMPOUNDSEMICONDUCTOR.NET
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