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Introduction to SoC Design Lab

Shao-Yi Chien (簡韶逸) Assistant Professor Graduate Institute of Electronics Engineering National Taiwan University SOC Consortium Course Material

Overview of SoC Lab Program ‰ 多數教材繼承自交通大學任建葳教授開設之IP Core Design

‰ 九一年(試教期):由台大吳安宇教授主導,編製教材ver.0版, 邀請3所大學試用。目前執行計畫之學校為:國立台灣大學電機 系、國立交通大學電子系、國立成功大學電機系。 ‰ 九二年(推廣期):編製一份完整教材,稱作第1版ver.1。 ‰ 九三年(增修期):由於SoC設計技術發展很快,為了因應此變 化,我們將作教材之增加或修訂,完成之教材第2版,稱作 ver.2,並將此完備之教材推廣至全國具SoC設計實力之大專院 校。 ‰ 九三年(穩定推廣期):第3版教材,供申請教授使用 ‰ 九六年(更新平台):採用Socle CDK新平台,發展教材ver. 4a

SLD Consortium Course Material


Platforms of Ver. 1 – Ver. 3 ‰ ARM Integrator

‰ ARM Versatile

SLD Consortium Course Material


New Features in Ver. 4a (1) ‰New platform – 低價高整合度實驗平台:虹晶科技CDK MEM. Exp. JTAG

64M Bytes SDRAM

Nor Flash


FPGA Download Port

ADC Connector

Audio In/out MAC

LA Miter USB A/B Cheetah Connectivity SoC SOC

IO Ext. Slot



LCD Connector Power adapter Mini PCI


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New Features in Ver. 4a (2) ‰One new lab module – IP Verification with EASY Verilog platform – Debug the design in Verilog environment

SLD Consortium Course Material


Course Outline in NTU (Fall 2007) ‰ Course Introduction ‰ ARM Instruction sets and Program ‰ ARM Processor Architecture ‰ AMBA ‰ Lab1: Code Development ‰ Lab2: Debugging and Evaluation ‰ Lab3: JTAG & Multi-ICE ‰ Lab4: Core Peripheral ‰ Lab5: Standard IO ‰ Lab6: On-Chip Bus ‰ Lab7: ASIC Logic on FPGA ‰ Lab8: Case Study-1 ‰ Lab9: Case Study-2 ‰ Final Project SLD Consortium Course Material


Lab 1: Code Development ‰ Goal

‰ Steps

– How to create an application using ARM Developer Suite (ADS) – How to change between ARM state and Thumb state when writing code for different instruction sets

‰ Principles – Processor’s organization – ARM/Thumb Procedure Call Standard (ATPCS)

‰ Guidance

– Basic software development (tool chain) flow – ARM/Thumb Interworking

‰ Requirements and Exercises – See next slide

‰ Discussion – The advantages and disadvantages of ARM and Thumb instruction sets.

– Flow diagram of this Lab – Preconfigured project stationery files SLD Consortium Course Material


Lab 1: Code Development (cont’) ‰ARM/Thumb Interworking – Exercise 1: C/C++ for “Hello” program • Caller: Thumb • Callee: ARM

– Exercise 2: Assembly for “SWAP” program, w/wo veneers • Caller: Thumb • Callee: ARM

– Exercise 3: Mixed language for “SWAP” program, ATPCS for parameters passing • Caller: Thumb in Assembly • Callee: ARM in C/C++

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Lab 2: Debugging and Evaluation ‰Goal – A variety of debugging tasks and software quality evaluation • Debugging skills – Set breakpoints and watchpoints – Locate, examine and change the contents of variables, registers and memory

• Skills to evaluate software quality – Memory requirement of the program – Profiling: Build up a picture of the percentage of time spent in each procedure. – Evaluate software performance prior to implement on hardware

– Thought in this Lab the debugger target is ARMulator, but the skills can be applied to Multi-ICE/Angel with the ARM development board(s). SLD Consortium Course Material


Lab 2: Debugging and Evaluation (cont’) ‰ Principles – The Dhrystone Benchmark – CPU’s organization

‰ Guidance – Steps only

‰ Steps – Debugging skills – Memory requirement and Profiling – Virtual prototyping – Efficient C programming

‰ Requirements and Exercises – Optimize 8x8 inverse discrete cosine transform (IDCT) according to ARM’s architecture. – Deliverables

‰ Discussion – Explain the approaches you apply to minimize the code size and enhance the performance of the lotto program according to ARM’s architecture. – Select or modify the algorithms of the code segments used in your program to fit to ARM's architecture.

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Lab 3: JTAG and MultiICE ‰ Steps

‰ Goal – Learn how to start-up the Multi-ICE server and debug program.

‰ Principle – Debugger introduction – ARM eXtended Debugger (AXD) – What is Multi-ICE and its function

‰ Guidance – Steps only

– The same as Lab2 except you do the debugging tasks with Multi-ICE. You will learn how to start-up the Multi-ICE server and debug program.

‰ Requirements and Exercises – Write a lotto program that generates N sets of number.

‰ Discussion – What’s different between ARMulator and MultiICE that we do the debugging task.

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Lab 4: Core Peripherals ‰ Goal

‰ Steps

– Understand the HW/SW coordination

– The same to that of code development

• Memory-mapped device • Operation mechanism of polling and Timer/Interrupt • (HAL)

– Understand available resource of CDK • semihosting

‰ Requirements and Exercises – Use timer to count the total data transfer time of several data references to SSRAM and SDRAM.

‰ Discussion

‰ Principles – Semihosting – Interrupt handler – Architecture of Timer and Interrupter controller

– Compare the performance between using SSRAM and SDRAM.

‰ Guidance – Introduction to Important functions used in interrupt handler SLD Consortium Course Material


Lab 5: Standard I/O ‰ Goal – introduce students to control IO and learn the principle of polling, interrupt, and semihosting through this Lab.

‰ Requirements and Exercises – Modify the LCD example.

‰ Principle – How to access I/O via the existing library function call.

‰ Guidance – Micro Hardware Abstraction Layer – How CPU access input devices

‰ Steps – This program controls the LCD on CDK SLD Consortium Course Material


Lab 6: On-Chip Bus ‰ Requirements and Exercises

‰ Goal – To introduce the interface design with EASY platform. Study the communication between FPGA on logic module and ARM processor on core module. We will introduce the AMBA in detail.

– Employ EASY Verilog platform to trace the hardware code and software code, indicate that software how to communicate with hardware using the AMBA interface.

‰ Principle – Overview of the AMBA specification – Introducing the AMBA AHB – AMBA AHB signal list – The ARM-based system overview

‰ Guide – We use a simple example on AMBA platform to make student understanding AMBA.

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Lab 7: ASIC Logic ‰ Requirements and Exercises

‰ Goal – HW/SW Co-verification using Rapid Prototyping

‰ Principles

– RGB-to-YUV converting hardware module

‰ Discussion

– Basics and work flow for prototyping with CDK – Target platform: AMBA AHB subsystem

‰ Guidance – Overview of examples used in the Steps

‰ Steps – Understand the files for the example designs and FPGA tool – Steps for synthesis with Xilinx ISE

– In example 1, explain the differences between the Flash version and the FPGA one. – In example 1, explain how to move data from DRAM to registers in MYIP and how program access these registers. – In example2, draw the interconnect among the functional units and explain the relationships of those interconnect and functional units in AHB sub-system – Compare the differences of polling and interrupt mechanism

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Lab 8,9: Case design ‰ Goal

‰ Steps

– Study how to use the ARMbased platform to implement JPEG encoding/decoding system. In this chapter, we will describe the JPEG algorithm in detail.

‰ Principle – Detail of design method and corresponding algorithm

‰ Guidance

– We divide our program into two parts: • Hardware • Software

‰ Requirements and Exercises – Try to understand the communication between the software part and hardware part.

– In this section, we will introduce the JPEG software file (.jpg) in detail. We will introduce the hardware module. SLD Consortium Course Material


Final Project Goal ‰ Help students to practice SoC design methodology – – – –

For students with C/C++ and Verilog coding background Without requirement of embedded OS device driver experience Based on SoCLE CDK Combined design skills learned in basic labs.

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Project Requirements ‰ Design an ARM Platform-based HW/SW co-design JPEG/BMP System – Driver design and AMBA wrapper design

‰ JPEG-to-BMP and BMP-to-JPEG file conversion – From console, use keyboard for user input

‰ ‰ ‰ ‰

Display image file on LCD RGBÆYCbCr accelerator IP on AHB 1D-DCT/IDCT accelerator IP on AHB Digital frame functions

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Design 1 ‰ Basic Requirement Part – Utilize LCD to Show the Decoded Image – Add RGB ↔ YCbCr Hardware Accelerator – Add DCT Hardware Accelerator

‰ Bonus Part – – – –

IDCT Hardware Accelerator Thumbnails Touch Panel Creative Design • Auto Full-screen Resize • Rotate with panel touching

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Feature of Design 1 ‰Thumbnail preview list ‰Touch-to-view ‰Touch-to-preview list ‰Auto-scale to fit screen ‰Touch-rotation

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Demo Video