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AIR UNIVERSITY Spring 2011 Faculty of Engineering Department of Electrical Engineering Course Information Course Title: FPGA based Design Lab (Yes) Credit hrs: 03+01=04 Prerequisites For this Course: Digital Logic Design, This Course is Prerequisite For: None Instructor: Syeda Narjis Fatima e-mail: narjis@mail.au.edu.pk Office: China Block, Room PF06 Office Phone Ext: 467 Text Book: • Verilog HDL - Guide to Digital Design & Synthesis Second Edition By Samir Palnitker Reference Book(s):  Digital Integrated Circuits: A Design Perspective By J. Rabaey, A. Chandrakasan, B. Nikolic.  Contemporary Logic Design By Randy Katz, Gaetano Borriello, • Digital Design Third Edition By M. Morris Mano • Engineering Digital Design Second Edition By Richard F. Tinder • The Design Warriors Guide to FPGA Design First Edition By Clive ‘Max’ Maxfield • Computer Architecture - A Quantitative Approach Second Edition By David A. Patterson

Rationale: The use of FPGAs for industrial and programmable system-on-a chip applications has become ubiquitous over the past few decades. With its advent a few decades ago, FPGA industry is increasingly extending benefits to numerous commercial, industrial and academic application fields. FPGAs play an integral role in major application areas including signal processing, aerospace, computer vision, cryptography, medical imaging, bioinformatics, defense systems and high performance computing. Thus it is essential that electrical engineers have an understanding of FPGA based systems, both hardware and software. This course develops the fundamental theory of FPGA based design supplemented by practical laboratory sections of the course to allow a thorough understanding of the design procedure and provides hands on experience to students as a basis to handling of complex industrial digital systems.

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Course Objectives: The learning outcome specified for students taking the course is that "at the end of this course you will be able to design simple FPGA based system for real applications." In addition to this specific objective, all courses should develop engineers professionally. To achieve these outcomes the following objectives are specified for the laboratory component of the course: 1. To provide practical experience with FPGA; 2. To expose the students to design work where there is no single correct solution, rather competing objectives; and 3. To encourage cooperative team work and develop communication skills. The semester begins with lectures and problem sets, to introduce fundamental topics before students embark on lab assignments and ultimately, a digital design project. The students design and implement a final digital project of their choice, in areas such as games, music, digital filters, wireless communications, image/video, graphics, signal processing etc. The course relies on extensive use of Verilog® for describing and implementing digital logic designs on state-of-the-art FPGA. The nature of the design process requires students to develop a design which represents the 'best solution' given a set of specifications and the limitations set in the design requirements. Such a task requires, amongst other skills, an understanding of the applied principles of embedded digital systems. While students will be provided with relevant theoretical knowledge through lectures and texts, the ability to apply such principles in real settings along with the required knowledge to achieve this level of learning outcome is the desired target of the course. The objective is therefore to provide practical experience in such an application of knowledge as a basis for understanding, design and implementation of complex digital systems for any targeted FPGA or any ASIC technology. The course will cover: •

High Level Design Methodology using Verilog HDL

Digital Design of High Speed Computational unit

Time Shared and Pipelined Architectures

Finite State machine Design

Algorithmic State machine Design

Fixed/ Floating Point Processor Design

Design targeted for FPGA or ASIC

Class/laboratory schedule: Three 50-minute lectures per week and three 3-hour laboratories during the semester.

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Software Usage: Xilinx ISE software will be employed as the software platform for FPGA programming. Simulation analysis will be based on ModelSim. Details of additional softwares will be furnished as per requirement.

Design Project: For the design project the students form groups on their own. Each group is assigned a project out of a pool. Each project is designed to be easily divided into a number of subtasks, and it is expected that each group would partition the project and assign tasks to each member. With these projects the students are exposed to a substantial design problem, and to solve it they need to work cooperatively within their team. At the end of the project each group is to submit a report. Students form groups and are assigned their project a few weeks into the semester. It is expected that they would have group meetings to brainstorm for possible solutions, and then assign tasks to each team member. Basic decisions about the hardware allocation will need to be made early by the team, then individuals will be assigned tasks such as algorithm development, coding, and documentation. The report has to document the hardware and software algorithms for the solution proposed by the students, and then provide details of the implementation and testing. This report is assessed on both the technical content and written communication skills of the group.

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Lecture Plan: Week

Topic

1

Revision of Digital Logic Design, Combinational & Sequential Circuits

2

Introduction to Verilog HDL

3

Computer Architecture Basics Digital Design of High Speed Computational unit

4

(Types of Adders) Digital Design of High Speed Computational unit

5

(Adders, Subtractors & Shifters) Digital Design of High Speed Computational unit

6

7

(Unsigned & Signed Multipliers) Digital Design of High Speed Computational unit (Signed & Constant Multipliers) Paper Review Task Assignment Finite State machine Design

8

(Moore & Mealy Model)

9

Algorithmic State machine Design & Micro-coded State Machine

10

Midterm Architecture Coding in FPGA (Summary)

11

Paper Review Task Assignment

12

Architecture Coding in FPGA (Summary) & Sports Week

13

Modular Design in FPGA

14

Floating Point Architecture Design

15

Time Shared and Pipelined Architectures

16

Time Shared and Pipelined Architectures

17

Revision, Presentations and Demonstration

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Laboratory Plan: Week

Topic

1

Introduction to Synthesizable Hardware Design in Verilog HDL Basic Design implementation in FPGA

2

Introduction to Design in Xilinx Design of 4-bit Carry Look Ahead Adder

3

Introduction to Design & Simulation in ModelSim

4

Universal Shift Register implementation

5

4 X 4 Signed Multiplier 4- bit Signed-Signed Wallace Tree Reduced Multiplier

6

Constant Multiplier

7

Finite State Machine Design (Moore & Mealy Model)

8

Algorithmic State Machine Design (Micro-coded Model )

9

Project Assignment

10

Xilinx Synthesis for FPGA, Layout & Floor plan

11

Modular Design

12

Term Project

13

Term Project

Grading and General Course Policies: Labs

25% (Lab 15%, Term Project 10%)

Assignments

7%

Quizzes

8%

Research Exercise

10%

Mids

15%

Finals

35%

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course outline