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INTERVIEW EEWeb.com

Issue 61 August 28, 2012

Brad Cleveland CEO Proto Labs

Electrical Engineering Community Visit www.eeweb.com

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Experts Exchanging Ideas Every Day. VISIT DIGIKEY.COM/TECHXCHANGE TODAY! Digi-Key is an authorized distributor for all supplier partners. New products added daily. Š 2012 Digi-Key Corporation, 701 Brooks Ave. South, Thief River Falls, MN 56701, USA


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TABLE OF CONTENTS

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Brad Cleveland PROTO LABS

Interview with Brad Cleveland - CEO

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Featured Products

Time-Interleaved ADCs for Digital Communication Receivers

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BY ELETTRA VENOSA, DR. MIKKO WALTARI, DR. FRED HARRIS & MIKE KAPPES WITH IQ-ANALOG

The effects of timing and gain mismatches on the sampled signal in M-channel TI-ADCs and a unique digital solution found nowhere else on the market.

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Fab Power BY MEENU SARIN WITH VLSI Despite the growth among the top fabless companies, the power of fabs is increasing in today’s semiconductor ecosystem.

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RTZ - Return to Zero Comic

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Brad Cleveland Proto Labs Proto Labs is the world’s fastest provider of CNC machined and injection molded parts. Their goal is to provide new product designers with the easiest, fastest and least-expensive way to obtain low volumes of parts based on their 3D CAD design. We spoke with the CEO of Proto Labs, Brad Cleveland, about the key to their success, the Protomold process and the future of the company.

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INTERVIEW Tell us a little about your background. How did you get started with physics and where did this interest take you? I received an undergraduate degree in math and physics, but when I was in college I got really into building interfaces for computers and mechanical devices, which was a whole new world within itself. One of my professors left to work at Honeywell and that connection resulted in my first job. My responsibilities there were really similar to what I was doing in college: writing software and developing electronic interfaces between computer systems. I was also ripping apart circuit boards and rewiring things, so I had a pretty aggressive introduction to hands-on electrical engineering in my early days. After Honeywell, I was fortunate to join a cutting-edge systems house called MTS Systems Corporation, also in Minneapolis. There I was working primarily on robotics systems and writing software for large-scale machinery. After a couple of years at MTS, I transitioned into a project engineer role and began organizing mechanical, software and electrical engineers to help develop and build custom manufacturing systems. For the next eight years, I traveled the world selling really interesting projects, like laser inspection systems and NASA flight simulators. While collaborating on a titanium manufacturing system that was ultimately sold to the Navy, I met a Johns Hopkins physicist who eventually became my business partner in a subsidiary that we operated for four years. Shortly after that I happened to be flipping through the local newspaper and saw a “want ad” from a company called Protomold, and the rest, as

they say, is history. I started as the CEO in November of 2001 of what would soon become Proto Labs and have held the position since. I was the tenth employee at the time, and we currently have a staff of 560. Tell us a little bit about the company overall. What different types of prototyping do you do? Proto Labs is the world’s fastest provider of CNC machined and injection-molded parts. We’ve created proprietary software that runs on high-performance compute clusters to dramatically accelerate standard manufacturing processes. The high speed, low cost, and unmatched scale with which we can deliver prototype and shortrun production parts is redefining manufacturing.

The reason our services are so fast is that we have developed proprietary software that automates standard manufacturing processes. We currently have two services available. If a product developer anywhere in the world wants to create a prototype, they can have parts made with our CNC machining service, a process that begins when they upload a 3D CAD model to our website. We routinely take orders for one part, which is

pretty unique in CNC machining because typically you have to undergo hours of programming and fixture design before making parts. We’ve automated the majority of that process, enabling us to make hundreds and hundreds of different parts every day. Our second (and original) service is called Protomold, which is a quick-turn custom plastic injection molding service. CNC machining deals with plastics and metal, and Protomold follows a similar process with plastic. You can upload a 3D CAD model and we’ll send back a quote within minutes. If you move ahead with the order, we immediately begin manufacturing the mold and ship parts to you as fast as the next business day. We do have some limitations with the size and geometry of the part, but if it’s a part that we can make, there’s nobody else faster or more costeffective for prototype or short-run parts. Can you elaborate a little more on the software that you use and the technology behind it? The reason our services are so fast is that we have developed proprietary software that automates standard manufacturing processes. It allows us to the save the time spent on programming and building fixtures that might take days in a standard environment. When a product developer uploads a model and asks for a quote, the software completely programs the machine in real time to manufacture that part. The software runs on a parallel processing environment that we also developed to handle all of the analysis automatically. That’s why we are able to go from quote to cutting materials faster than anybody Visit www.eeweb.com

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EEWeb PULSE actually breakthrough cheap because typically you’d have to pay someone to develop fixtures and program the equipment, but again, our automation makes it more cost effective. The price really depends

else. We’ve invested around 100 years’ worth of man-hours into this software, and we have been doing it over a 12-year period during which we have been producing parts for customers and constantly updating the software to improve the process. Do you operate 24 hours a day since you get prototypes out that fast? We do operate at all times. We have manufacturing facilities in the United States and in England, which supports all of the European Union, and we also have a facility in Japan. In the U.S., we have about 300,000 square feet of manufacturing space in four different plants and almost

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all of them operate 24/7. In Europe, we have around 130,000 square feet of manufacturing space to cover both services, and that facility runs 24 hours a day, 5 days a week to meet demand. In Japan, the plant has 30,000 square feet and operates around 18 hours a day, 5 days a week. We have these different locations so that we can provide our services to clients worldwide and still maintain our reliable and quick prototyping services, which is the basis of our core business model. What is the range of prices for your services? For our CNC Machining service, the least expensive single part price will be about $100. That’s

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We’ve invested around 100 years’ worth of man-hours into this software, and we have been doing it over a 12-year period during which we have been producing parts for customers and constantly updating the software to improve the process. on the size and complexity of the part. The average price to create a mold and have 25 parts delivered is about $4,000. However, once you get that mold made, we can continue to make parts for you at a few dollars apiece, or less depending on the size and materials. Where are you based? We are in the Minneapolis/St. Paul area. Our headquarters are in a Western suburb called Maple Plain. Our European manufacturing facilities are located in Telford,


INTERVIEW England and we have sales and customer service facilities in Germany, France and Italy in addition to the manufacturing plant in Japan.

winning team. We actually have a VP of Culture on staff, tasked specifically with creating a nurturing and productive workplace in which people enjoy doing their jobs.

What’s the culture like at Proto Labs? We strive for a culture that is as entrepreneurial as possible, meaning that we’re all in this together and our objective is to profitably grow this company forever. We aim to maintain an environment where people are appreciated and have the opportunity to contribute to a

What’s in store for Proto Labs for the next few years? We’ve had a strategy in place for a number of years, made up of several objectives. One of the objectives is to keep searching for new customers, driven by expansion of our marketing activities. We’ve established ourselves in the U.S., Europe and Japan and it’s unlikely that we’ll stop

there. The second growth factor is to constantly broaden the parts that we can handle, meaning the complexity of parts and additional materials that we support. We have a lot of things going on in that respect as well. The third growth factor is that we have the ability to add new manufacturing capabilities beyond the CNC machining and Protomold. You can expect to see all of these developments to continue over the next five years. ■

Proto Labs headquarters in Maple Plain, MN

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Time-Interlea ADCs for Dig Communicati Receivers

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aved gital ion

TECH ARTICLE

Dr. Elettra Venosa EE PHD - IQ-Analog, SDSU

Co-Authors: Dr. Mikko Waltari, IQ-Analog Dr. fred harris, SDSU Mike Kappes, IQ-Analog

Time-interleaving (TI) is the most effective way to overcome the constraints imposed by hardware technology which limit the maximum sampling frequency in analog-to-digital converters (ADCs) by reducing implementation costs and lowering power consumption. Low power consumption, lower implementation cost, high sampling frequency and fine resolution are highly desired characteristics with multipurpose DSP-based communication receivers. Unfortunately when ADCs are used in a time-interleaved fashion, timing and gain mismatches between the channels are introduced. These mismatches have a strong adverse effect on the performance of these systems. In this white paper we describe the effects of timing and gain mismatches on the sampled signal in the general case of M-channel time-interleaved analog-to-digital converters (TI-ADCs) and propose a solution for the two-channel TI-ADC case. The proposed solution is quite general and also unique from the other solutions currently present on the market in that it works in communication scenarios when sub-sampling of intermediate frequency (IF) carriers is applied. This low-rate sampling approach is becoming popular in communication receivers because it promises lower workload and power consumption. Our solution is implemented completely in the digital domain, operates in the background while the TI-ADC is sampling, and allows for the full correction of mismatches without sacrificing resolution.

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ADC BASICS Analog-to-digital converters translate analog quantities, which are characteristic to most phenomena in the “real world,� to the digital domain, used in information processing, computing, data transmission, and control systems. The relationship between inputs and outputs of an ideal ADC is shown in Figure 1. The analog signal, x(t), is at first, processed through a sampler that takes its values at fixed periodic, uniformly distributed, discrete time instants with resolution dictated by the sampling frequency fs=1/Ts. Then the discrete time samples are quantized and coded in bit words. The quantizer performs the transformation of the continuous values to fixed discrete values by applying the transfer function shown in Figure 2. Slightly different curves (non symmetric around zero or having non-uniformly distributed steps) can describe the quantization process when it is required by the design. The quantized values are later coded in digital N-bit words. fs x(t)

ADC

bits

ADC Ts=1/fs

Analog Input

Digital Output

are slightly perturbed and the ADCs do not realize a perfectly uniform amplitude quantization. The nature of the hardware devices involved in the sampling process (sampler and clock generator) also causes loss of precision of the output sampled data. This imprecision, which has two components (random and deterministic), is well modeled by timing jitter and timing offset errors. These two phenomena are quite different hence they have to be described by using different models and compensated using different methods. In particular, while timing jitter presents a random nature and can be correlated or uncorrelated (colored timing jitter and white timing jitter), timing offset is a deterministic delay. The correlated timing jitter, as well as the timing offset, have more significant effects when the frequency of the input signal is high. Usually, even if they are very small when compared to the overall sampling period, they will have destructive effects which compromise high precision applications. At high sampling frequencies the constraints on precision become, in fact, even more stringent. Our goal is to increase the sampling frequency of the conversion process without impacting the ADC performance and implementation cost. A good solution for this is a time-interleaved architecture. A timeinterleaved ADC represents an effective way to increase the overall sampling frequency of the system by using multiple lower sample rate ADCs.

QUANTIZER

Unfortunately, when two or more analog-to-digital converters are time-interleaved, the conversion process n t suffers from the timing and gain mismatches between Ts the channels. All known solutions for correcting these Figure 1: Analog-to-Digital Converter. The Analog-to-Digital mismatches are ineffective when the input signal has Conversion Process is Usually Modeled as a Sequence of Two a band-pass nature which incidentally is the most Steps: Uniform Sampling and Uniform Quantization common scenario for digital communication receivers. In reality, the digitization of an analog signal, is far bits from being the ideal process just described. The quantizer in fact introduces errors which are due to the approximation in representing analog, continuous values with a finite set of 2N discrete values. All the analog signal values included in a certain, fixed interval are associated with the same discrete output value (look at the curve in Figure 2). This approximation imposes -V V Analog Values uncertainty on the quantizer output values which is usually modeled as a, zero mean, uncorrelated noise which is named quantization noise. This noise can be reduced (for example by increasing the number of bits) but it can never be completely avoided. Note that in practice, because of inaccuracies and mismatches in the ADC implementation, the quantizer thresholds Figure 2: Transfer Function of Uniform Quantizer x(t)

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x[nTs]

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The current identification and correction architectures for TI-ADCs also do not address when the desired signal spectral copy is not in the first Nyquist zone but instead resides on higher order Nyquist zones. Band-pass sampling on higher order Nyquist zones is commonly used in communication scenarios in which the involved signals have a sparse nature in the frequency domain. In the following section, we explain briefly the effects of gain and timing mismatches on the TI-ADC input signal and later we present our solution for identifying and correcting the artifacts resulting from those mismatches in a two-channel TI-ADC case. TIME-INTERLEAVED ARCHITECTURE Several architectures of ADC’s exist (subranging, folding, pipeline, successive approximation register, etc) which are suitable for high sample rate, high precision applications. In each case there is a clear tradeoff of power and speed which restricts the range of applications the architecture can service. It is possible to eliminate this compromise through the use of time interleaving multiple ADC cores. (Mn+0)Ts+r0Ts

ADC0 (Mn+1)Ts+r1Ts

ADC1

x(t)

(Mn+2)Ts+r2Ts

MUX

x(n)

ADC2

TECH ARTICLE

bandwidth required for the anti-alias filter [1]. However, for each arm it is not required to verify Nyquist sampling criteria hence, each TI-ADC channel, samples the analog signal at 1/M of the overall sampling frequency, fs. The starting point (initial time) of each sampler is delayed by mTs/M. This time shift turns into a phase shift in the frequency domain. In the ideal case the phase shifts on each channel are such that the undesired aliased signal replicas destructively sum together when the samples from each channel are interleaved by the multiplexer while only the desired replicas constructively sum together. When two or more analog-to-digital converters are timeinterleaved, the conversion process suffers from timing and gain mismatches between the channels which corrupt the multiplexing process. THE CHANNEL MISMATCHES There are two main sources of trouble in TI-ADCs: the timing offsets, r0, and the gain offsets, g0. The timing offset is the difference between the ideal time instant, in which the ADC is supposed to sample the input signal, and the real time instant in which the ADC samples the input signal. The gain offset is a multiplicative gain which is applied to the amplitude of the input signal. These parameters result from inevitable fabrication process imperfections as well as more systematic circuit layout and parasitic differences. They are normally very small and, when the ADC is used in a standalone fashion, they do not affect its performance. However they become considerable issues in time-interleaved architectures. These problems are caused by differences between the individual ADCs used in the time-interleaved system and are commonly referred to as channel mismatch errors. The channel mismatch errors give rise to distortion.

(Mn+M-1)Ts+rM-1Ts

fs ≥ BW + Δf (1)

When used in a two-channel time-interleaved architecture, two ADCs operate in parallel with a Ts time offset of their 2Ts time interval sampling clock. When multiplexed properly, the overall sampling frequency of the system is doubled. In an ideal two-channel TIADC, the aliasing terms formed by the individual ADCs, operating at half rate, are cancelled by the interleaving process. This cancellation occurs because the aliased spectral component of the time offset ADC has the opposite phase of the same spectral component of the non-time offset ADC. In the absence of time offset and gain mismatch the sum of their spectra would cancel the undesired alias components.

where BW is the signal bandwidth and Δf is the extra

Because of gain and timing phase mismatches the

ADCM-1

Figure 3: Model of a M-Channel Time Interleaved Analog-toDigital Converter

Figure 3 shows the block diagram of a M-channel TI-ADC architecture. In the interleaved fashion, two or more ADCs are placed in parallel and their samples are time-interleaved by a multiplexer. The overall sampling frequency of the system must verify Nyquist sampling theorem which states

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X(jΩ)

-Ωs

-Ωs 2

Ωs 2

Ωs

Ω

Ωs 2

Ωs

Ω

Ωs 2

Ωs

Ω

X(jΩ)

-Ωs

-Ωs 2 X(jΩ)

-Ωs

-Ωs 2

X(jΩ)

-Ωs 2

Ω’s Ω 2 Figure 4: Pictorial View of the Effects of Time and Gain Mismatches in a Two-Channel TI-ADC

undesired spectral components from the interleaved time series replicas do not sum to zero. The sample instants of the two ADCs are, in fact, affected by a constant delay, Δtm with m = 0, 1, which results in an undesired frequency dependent phase offset of their aliased spectra which prevents them from being cancelled perfectly at the output of the time multiplexer. The gain mismatch contributes a frequency independent imperfect cancellation of the spectral components at the output of the TI-ADC system.

MISMATCHES IDENTIFICATION & CORRECTION

The effects of gain and time mismatches in a two channel TI-ADC are illustrated in Figure 4 while Figure 5 and Figure 6 show, using Matlab simulations, the effect of timing and gain mismatches on the output spectra of a two-channel TI-ADC. The ideal TI-ADC case, shown in Figure 5, shows perfect cancellation of the aliased replica occurs because of the absence of mismatches. The real case, shown in Figure 6, shows the effects of timing and gain mismatches which cause the imperfect cancellation of the aliased signal replicas from the second Nyquist zone which are clearly visible on the desired spectrum. In both the plots we used a combination of sine waves as a sample spectrum in order to show clearly, on the desired spectrum, the aliased replicas derived from the mismatches.

• Background techniques, also known as blind, for which no information is required about the input signal (except perhaps some knowledge about the presence or absence of signal activity in certain frequency bands) in order to estimate the mismatches.

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Our goal is to correct the effects of timing and gain offset in the sampled data domain. In order to do this, we must first estimate them. Estimation methods are divided into two categories: • Foreground techniques, also known as non-blind, that inject a known test or probe signal to estimate the mismatches by measuring the TI-ADC output responses to the probe.

The first approach has the disadvantage that normal TI-ADC operations are suspended during the probe but in the second approach the calibration process does not interrupt normal TI-ADC operations. There are many papers present in the literature that use either blind or non-blind estimation and correction methods in a two-channel TI-ADC [2], [4]. In [2], the authors estimate time mismatches by means of an

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TECH ARTICLE

estimation and correction structures in the above cited papers are derived assuming the input signal has a lowpass nature.

Interpolated Signal - First Nyquist Zone - Frequency Domain 0

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The solution we propose is completely independent of the signal spectrum and of the selected overall TI-ADC sampling frequency, hence it works also in the case of band-pass signals for which sparse sampling (subsampling) is applied.

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Figure 5: Spectrum of the Output Signal of an Ideal Two-Channel TI-ADC Two-Channel TI-ADC Output Spectrum 0 -10

Log Magnitude [dB]

-20 -30 -40 -50 -60 -70 -80 -90 -100 -0.5

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Figure 7 shows the block diagram of a two-channel TI-ADC followed by an estimation and compensation structure for both, gain and timing mismatches which operates in the digital domain. The identification and compensation component is detailed in Figure 8. The architecture is based on the structures derived in [2] and [3]. It is based on the assumptions that the timing offsets are small relative to the overall sampling period, Ts, and their average value is zero. We will present several important modifications to this structure that allow us to correct channel mismatches when low-rate sampling is applied to sparse signals.

Figure 6: Spectrum of the Output Signal of a Real Two-Channel TI-ADC

adaptive approach based on the least-mean-square (LMS) algorithm. The input signal spectrum is assumed to be low-pass and slightly oversampled. This last hypothesis creates a mismatch band containing only undesired alias components. The total demonstrated improvement of aliased to non aliased spectral level ratio achieved by this technique is approximately 26dB. The structure presented in [2] has been generalized to the M-channel TI-ADC case in a more recent paper [3]. In [4] the authors present an adaptive filtering structure that uses three fixed FIR filters and two adaptive gain and delay parameters to perform the calibration. The assumptions on the input signal are the same as in [2] that it is a slightly oversampled low-pass signal. This structure achieves <26dB of improvement. All the g0

x

g1

x

(2n+0)Ts+r0Ts

ADC0

(2n+1)Ts+r1Ts

MUX

Identification & Compensation

ADC1

Figure 7: Proposed Solution Scheme for the Two-Channel TI-ADC

Balanced Output

+

Normalized Frequency

ˆ e[n]

HP Filter

+ –

Error

+ x

HP Filter

x Derivative Filter

ˆ g[n] C

x

+

ˆ g[n] C cos(πn)

x

x

ˆ r[n] C HP Filter

x ˆ r[n] C

LMS Algorithm

-120 -60

Figure 8: Commonly Used Identification and Correction Structure for a Two-Channel TI-ADX

Note that the basic observation that underlies the existing structure, depicted in Figure 8, is that by oversampling the input signal x(t) with a TI-ADC in which no mismatches occur, we should be able to observe some spectral regions where no signal energy is present. However, because of gain and time offsets between the two channels, a certain amount of undesired energy appears in these bands (called mismatching bandwidths). By filtering and minimizing the amplitude of the signal spectrum in the mismatching bandwidths it is possible to adaptively identify and correct both the mismatches and for this purpose the LMS algorithm is a natural option. The assumption of the low-pass nature Visit www.eeweb.com

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of the input signal, along with the knowledge of the sampling frequency, allows us to predict the position of the mismatching bandwidths and to design high-pass filters to isolate, monitor, and correctly process these spectral regions. P(f)

∆f

0

fIF

fs 2

fs

f

Figure 9: Graphical Example of Signal Spectrum After Sampling

We recall here that in a common digital receiver, with only one analog-to-digital converter, the sampling frequency is selected in order to satisfy the equality in Eq. (1) where Δf is called oversampling factor. Note that it represents the gap between the two signal spectra replicas after sampling (see Figure 9). It is our desire to make this factor as small as possible, compatible with the requirements for the subsequent filtering tasks that the digital receiver has to handle. In a practical receiver usually 0 < Δf ≤ 2fIF - BW (2) It is most common to have quarter-rate sampling: fIF/ fs=1/4. Note that the case Δf >2fIF-BW corresponds

to a gap between the maximum frequency component of the signal, fmax, and fs/2 that is bigger than the gap between the zero frequency and the minimum signal component, fmin, in the first Nyquist zone. This hypothesis is commonly discarded because it implies a waste of bandwidth. When a two channel TI-ADC is used, the same sampling frequency fs0,1=fs/2 is used on each arm with a time shift of the initial sampling time in one of the arms equal to 1/fs. These sampling frequencies violate Nyquist sampling theorem and, as a consequence of that, the negative side of the replica that resides in the second Nyquist zone appears in the first Nyquist zone. This replica should be automatically suppressed at the output of the multiplexer if no mismatches are present in the structure. We specified before that when fIF/ fs=1/4, Δf/2 represents the gap between fmax, the maximum frequency of the input signal, and fs0,1. It also represents the gap between the zero frequency and the minimum frequency of the negative replica coming from the second Nyquist zone. In this case, the two replicas, the positive one belonging to the first Nyquist zone and the negative one belonging to the second Nyquist zone, will perfectly overlap on each other and it is difficult to visualize the mismatches caused by the time and gain offset. In the case in which Δf <2fIF-BW the negative side of the signal replicas belonging to the second Nyquist zone will partially overlap on the positive signal

TI-ADC Output Spectrum

Magnitude [dB]

20 0 -20 -40 -60 -80 -100 -0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency

Compensated TI-ADC Output Spectrum

Magnitude [dB]

0 -20 -40

Missing Tone

Missing Tone

-60 -80 -100 -0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

Normalized Frequency

Figure 10: Subplot 1: Spectrum at the Output of TI-ADC Affected by Gain and Time Mismatches; Subplot 2: Spectrum at the Output of the Identification and Correction Structure

18

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0.5


part belonging to the first Nyquist zone; it will be, in fact, closer to zero. It is clear that, for both the cases specified above, we will not have undesired energy between fmax, and fs0,1. This is exactly the spectral region in which the mismatching bandwidths have been defined and for which the current TI-ADC identification and correction structures have been designed. And this is also the reason for which the current architectures do not work for IF-sampling communication scenarios. Moreover, the location of the mismatching bandwidths becomes even more unpredictable when low-rate sampling is applied. Amplitude

LMS Error 0.1 0.05 0 -0.05 0

1000

2000

3000

4000

5000

6000

Number of Samples

0.08 0.06 0.04 0.02 0 -0.02 0

TECH ARTICLE

Transmitted Data

Uncompensated Results

Compensated Results

3

3

3

2

2

2

1

1

1

0

0

0

-1

-1

-1

-2

-2

-2

-3

-3

-2

0

2

-2

0

2

-3

-2

0

2

Figure 12: Subplot 1: Transmitted QPSK Constellation, Subplot 2: Effect of Gain and Timing Mismatches on the Transmitted QPSK Constellation; Subplot 3: Effect of the Correction Structure on the Output QPSK Constellation of the TI-ADC

external side (high frequencies) of the signal spectrum; by using the proposed estimation and compensation structure we are able to reduce its energy below 90dB. This value is indicated by the dotted red line in the figure.

Estimated Timing Error

In the first subplot of Figure 10 the spectrum of a QPSK signal processed by a two-channel TI-ADC with gain and time offsets is shown. The timing offsets for this example are r0=0 and r1=0.04 which corresponds to a 4% error on the overall sampling time. Note that this time offset is quite large if compared to a realistic scenario but, also for this extreme case, the identification and correction structure still provides good attenuation levels. The selected gain offsets for this example are g0=0 and g1=0.05 which corresponds to a 5% error on the second arm of the TI-ADC. Note that the QPSK signal replica that should belong to the second Nyquist zone appears in the first one. This replica is completely superimposed on the information signal and, for this reason, it is not possible to demonstrate its presence on this signal spectrum. In the second subplot of Figure 8 the signal spectrum at the output of the compensator is shown. In this figure, the tone we inserted for testing the functionality of the structure, is not present on the

In order to demonstrate the degree of mismatch suppression which we cannot see directly in the spectral plots, we compare in Figure 12 the demodulated QPSK constellation (after correction) with the transmitted one. The demodulation process is achieved by passing the signal through a Hilbert transform, which gives us access to the analytic signal and its complex envelope. The signal is then down converted by a complex heterodyne in a digital down converter. Finally, the matched filter, with the proper time alignment, but not phase correction, is applied to the complex baseband signal to maximize its signal to noise ratio. The constellation resulting from this process is shown in the third subplot of Figure 12 along with the transmitted QPSK constellation in the first subplot and the corrupted QPSK constellation at the output of TI-ADC in the second subplot. It is clearly shown that the TI-ADC mismatches result in an increased variance cloud around the matched filter output constellation points. The variance

Amplitude

We have developed a general solution that is independent of the modulation format, signal bandwidth and overall selected sampling frequency. By using our solution, we are able to push the level of the artifacts below 80dB which is a unique result in this field (see references at the end of this section).

Figure 11 shows the convergence behavior of the estimation process. The LMS error is minimized when the timing and gain errors converge to their correct values. The chosen step for the LMS algorithm in this example is Îź=0.04. Because the LMS algorithm has been applied to minimize the energy of a deterministic sine tone, the converged value of the error has zero mean with zero variance. In the second subplot of Figure 11, the convergence behavior of the weights associated with the timing error is shown. Similarly, the third subplot of Figure 11 shows the convergence process of the weights associated with the gain error estimation; the process converges after 200 samples to 0.025 which is the theoretical expected value corresponding to the average value of the ADCs gains.

1000

2000

3000

4000

5000

6000

4000

5000

6000

Number of Samples

Amplitude

Estimated Gain Error 0.04 0.02 0 0

1000

2000

3000 Number of Samples

Figure 11: Subplot 1: Convergence Behavior and Estimated LMS Error; Subplot 2: Estimated Gain Error; Subplot 3: Estimated Timing Error

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Magnitude [dB]

TI-ADC Output Spectrum with Filtering

0

-50

-100 -0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.3

0.4

0.5

Normalized Frequency

Magnitude [dB]

Compensated TI-ADC Output Spectrum 0

-50

-100 -0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

Normalized Frequency

Figure 13: Subplot 1: Sine Wave Spectrum at the Output of TI-ADC Affected by Gain and Time Mismatches with Superimposed Derivative and High-Pass Filters; Subplot 2: Sine Wave Spectrum at the Output of the Identification and Correction Structure

clouds are completely removed by using the proposed structure. In Figure 13 we generated 17 equally spaced sine waves spanning frequencies from 0.1 to 0.4 on the normalized frequency axis. The gain and time errors are the same as those used in the previous simulations. The combined effects of time and gain offsets can be visualized in the first subplot of Figure 13 where the folded spectrum, coming from the second Nyquist zone and unsuppressed at the output of the multiplexer, appear between the spectral line of the constructed information signal. The second subplot of Figure 13 shows the spectrum obtained after compensation. Here we can clearly recognize that the spectral artifacts are significantly reduced. We also note a residual

spectrum containing the artifact remnants that were not suppressed to the same degree as the probe signal. These artifacts are below -90dB as demonstrated by the dotted red line in the same picture. Note that before compensation, the maximum amplitude, on log scale, of the spurious peaks affecting the signal is -30.2dB; after compensation their maximum amplitude is -90dB. This result clearly demonstrates that our structure is capable of obtaining improvement of approximately 60dB. For completeness, Figure 14 shows the LMS convergence behavior, along with the time and gain offsets estimation for the sine waves spectrum case. The Îź value used for the LMS algorithm embedded in the identification structure is the same as in the simulation of Figure 10.

Amplitude

LMS Error 1 0 -1 0

1000

2000

3000

4000

5000

6000

4000

5000

6000

4000

5000

6000

Number of Samples

Amplitude

Estimated Timing Error 0.05 0 -0.05 -0.1 0

1000

2000

3000 Number of Samples

Amplitude

Estimated Gain Error 0.1 0 -0.1 -0.2 0

1000

2000

3000 Number of Samples

Figure 14: Subplot 1: Convergence Behavior and Estimated LMS Error for the Sine Wave Spectrum; Subplot 2: Estimated Gain Error; Subplot 3: Estimated Timing Error

20

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TECH ARTICLE

REFERENCES

About the Author

[1] fred harris, Multirate Signal Processing, Prentice Hall, 2004.

Elettra Venosa received the “Laurea” (BS/MS) degree (summa cum laude) in electrical engineering in January 2007 from Seconda Università degli Studi di Napoli, Italy. From January 2007 to November 2007 she was a researcher at the Italian National Inter-University Consortium for Telecommunications. In November 2010, she received the Ph.D. in Telecommunication/DSP from Seconda Università degli Studi di Napoli, Italy. From June 2008 to September 2008 she worked as a project manager for Kiranet s.r.l.- ICT Research Centre – to develop an advanced radio identification system for avionics, in collaboration with the Italian Center for Aerospace Research (CIRA). From April 2009 to September 2009 she worked at Communications and Signal Processing Laboratory (CSPL) in the department of Electrical and Computer Engineering at Drexel University, Philadelphia, PA, USA where she focused on sparse sampling techniques for software defined radio receivers. Currently, she is working, as a system engineer in IQ-Analog Corp., a semiconductor company located in San Diego, CA, USA. Currently, she is also working, as a postdoctoral researcher, on multirate signal processing techniques for software defined radio design in the department of Electrical and Computer Engineering at San Diego State University, San Diego, CA, USA. She is author of the book “Software Radio Sampling Rate Selection, Design and Synchronization.” ■

[2] S. Saleem and C. Vogel, “LMS-based identification and compensation of timing mismatches in a twochannel time interleaved analog-to-digital converter”, in Proc. IEEE Norchip Conf., pp. 14, November 2007. [3] C. Vogel, S. Saleem, and S. Mendel, “Adaptive blind compensation of gain and timing mismatches in M-channel time interleaved ADCs,” in Proc. 14th IEEE ICECS, pp. 4952, September 2008. [4] S. Huang, B. C. Levy, “Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 53, no. 6, pp. 1278-1288, June 2006. [5] P. Satarzadeh, B. C. Levy, and P.J. Hurst, “Adaptive Semi-blind Calibration of Bandwidth Mismatch for TwoChannel Time- Interleaved ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 56, no. 9, September 2009. [6] J. Goodman, B. Miller, M. Herman, G. Raz and J. Jackson, “Polyphase Nonlinear Equalization of TimeInterleaved Analog-to-Digital Converters,” IEEE Journal of Selected Topics in Signal Processing, vol. 3, no. 3, June 2009. [7] F. Palmieri, E. Venosa, A. Petropulu, G. Romano and P. Salvo Rossi, “Sparse Sampling for Software Defined Radio Receivers”, Proc. of SPAWC 2010 - 11th IEEE International Workshop on Signal Processing Advances in Wireless Communications, June 20-23 2010, Marrakech, Morocco. [8] E. Venosa, fred harris and F. Palmieri, “Software Radio: Sampling Rate Selection, Design and Synchronization,” Springer Science + Business Media, LLC 233 Spring Street, New York, NY 10013, USA, 2011. [9] F. Palmieri, E. Venosa, G. Romano, P. Salvo Rossi and A. Petropulu, “On Low-Rate Uniform Sampling of Digital Communication Signals,” submitted to EURASIP Journal on Wireless Communications and Networking. [10] Mikko Waltari and Kari Halonen, Circuit Techniques for Low-Voltage and High-Speed A/D Converters, Kluwer Academic Publishers, 2002.

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QS9000 • TS/ISO16949 • IS O 14001 • IS O 13485 • IS O 9001


INTERVIEW Get the Datasheet and Order Samples http://www.intersil.com

Single or Multiple Cell Li-ion Battery Powered 4-Channel and 6-Channel LED Drivers ISL97692, ISL97693, ISL97694A The ISL97692, ISL97693, ISL97694A are Intersil’s highly integrated 4- and 6-channel LED drivers for display backlighting . These parts maximize battery life by featuring only 1mA quiescent current, and by operating down to 2.4V input voltage, with no need for higher voltage supplies. The ISL97692 has 4 channels and provides 8-bit PWM dimming with adjustable dimming frequency up to 30kHz. The ISL97693 has 6 channels with Direct PWM dimming control. The ISL97694A has 6 channels and provides 8-, 10-, or 12-bit PWM dimming with adjustable dimming frequency up to 30kHz, 7.5kHz, or 1.875kHz, respectively, controlled with I2C or PWM input. ISL97692 and ISL97694A feature phase shifting that may be enabled optionally, with a phase delay between channels optimized for the number of active channels. In ISL97694A, phase shifting can multiply the effective dimming frequency by 6 allowing above-audio PWM dimming with 10-bit dimming resolution. The ISL97692/3/4A employ adaptive boost architecture, which keeps the headroom voltage as low as possible to maximize battery life while allowing ultra low dimming duty cycle as low as 0.005% at 100Hz dimming frequency in Direct PWM mode. The ISL97692/3/4A incorporate extensive protection functions including string open and short circuit detections, OVP, and OTP. The ISL97692/3 are offered in the 16 Ld 3mmx3mm TQFN package and ISL97694A is offered in the 20 Ld 3mmx4mm TQFN package. All parts operate in ambient temperature range of -40°C to +85°C.

Features • 2.4V Minimum Input Voltage, No Need for Higher Voltage Supplies • 4 Channels, up to 40mA Each (ISL97692) or 6 Channels, up to 30mA Each (ISL97693/4A) • 90% Efficient at 6P5S, 3.7V and 20mA (ISL97693/4A) • Low 0.8mA Quiescent Current • PWM Dimming Control with Internally Generated Clock - 8-bit Resolution with Adjustable Dimming Frequency up to 30kHz (ISL97692/4A) - 12-bit Resolution with Adjustable Dimming Frequency up to 1.875kHz (ISL97694A) - Optional Automatic Channel Phase Shift (ISL97692/4A) - Linear Dimming from 0.025%~100% up to 5kHz or 0.4%~100% up to 30kHz (ISL97692/4A) • Direct PWM Dimming with 0.005% Minimum Duty Cycle at 100Hz • ±2.5% Output Current Matching • Adjustable Switching Frequency from 400kHz to 1.5MHz

Applications • Tablet, Notebook PC and Smart Phone Displays LED Backlighting

Related Literature (Coming Soon) • AN1733 “ISL97694A Evaluation Board User Guide” • AN1734 “ISL97693 Evaluation Board User Guide” • AN1735 “ISL97692 Evaluation Board User Guide” 10

L1

VIN: 2.4V~5.5V

10µH

4.7µF

10

D1

VOUT: 24.5V, 6 x 20mA 4.7µF 4.7µF

1

VIN LX COMP

15nF 12k

100pF 470k

OVP 2.2nF

ISL97694A

ILED (mA)

1µF

23.7k

ISET 53k

AGND

PGND

0.1

0.01 fPWM: 200Hz

SDA/PWMI SCL

CH1

EN

CH2

FPWM 291k

143k

FSW

0.001

CH3 CH4 CH5

0.0001 0.001

CH6

FIGURE 1. ISL97694A TYPICAL APPLICATION DIAGRAM

July 19, 2012 FN7839.2

fPWM: 100Hz

0.01 0.1 1 INPUT DIMMING DUTY CYCLE (%)

10

FIGURE 2. ULTRA LOW PWM DIMMING LINEARITY

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

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F


TECH ARTICLE

FAB

POWER Looks like the scarling down road for the fabless

– foundry model is getting bumpier. First, the high cost of setting up new fabs made the earlier IDMs get into the “fab lite” model where they depend upon the pure-play foundries for the basic process capacity and do the specialized process add-ons in-house to get the competitive advantage. The fabless companies coupled with pure-play foundries and gained prominence. The industry seemed to have found a way out (at least temporarily) of the high cost challenges of scaling down coupled with the issues of designing multi-million gates chips with increasing features and decreasing time to market window.

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2011 Top 25 Fabless IC Suppliers ($M)

2011 2010 2009 Rank Rank Rank

Company

Headquarters

2009 ($M)

2010 % ($M) Change

2011 % ($M) Change

1

1

1

Qualcomm

United States

6,409

7,204

12%

9,910

38%

2

2

3

Broadcom

United States

4,271

6,589

54%

7,160

9%

3

3

2

AMD

United States

5,403

6,494

20%

6,568

1%

4

6

5

Nvidia

United States

3,151

3,575

13%

3,939

10%

5

4

6

Marvell

United States

2,690

3,592

34%

3,445

-4%

6

5

4

MediaTek

Taiwan

3,500

3,590

3%

2,969

-17%

7

7

7

Xilinx

United States

1,699

2,311

36%

2,269

-2%

8

8

10

Altera

United States

1,196

1,954

63%

2,064

6%

9

9

8

LSI Corp.

United States

1,422

1,616

14%

2,042

26%

10

10

11

Avago

Singapore

858

1,187

38%

1,341

13%

11

13

12

MStar

Taiwan

838

1,065

27%

1,220

15%

12

11

13

Novatek

Taiwan

819

1,149

40%

1,198

4%

13

15

16

CSR

Europe

601

801

33%

845

5%

14

12

9

ST-Ericsson*

Europe

1,263

1,146

-9%

825

-28%

15

16

15

Realtek

Taiwan

615

706

15%

742

5%

16

17

17

HiSilicon

China

572

652

14%

710

9%

17

27

67

Spreadtrum

China

105

346

230%

674

95%

18

19

19

PMC-Sierra

United States

496

635

28%

654

3%

19

18

14

Himax

Taiwan

693

643

-7%

633

-2%

20

21

-

Lantiq

Europe

0

550

N/A

540

-2%

21

33

30

Dialog

Europe

218

297

36%

527

77%

22

22

21

Silicon Labs

United States

441

494

12%

492

0%

23

29

20

MegaChips

Japan

445

337

-24%

456

35%

24

23

24

Semtech

United States

254

403

59%

438

9%

25

24

23

SMSC

United States

283

397

40%

415

5%

Top 25 Total

–––

–––

38,242

47,733

25%

52,076

9%

Non-Top 25 Fabless

–––

–––

11,091

14,781

33%

12,811

-13%

Total Fabless

–––

–––

49,333

62,514

27%

64,887

4%

* Represents the 50% share no accounted for by ST. Source: Company reports, IC Insights’ Strategic Reviews Database

But now the speed breakers on this road are getting frequent and higher. Take the last couple of examples. FD-SOI is one of the new transistor architectures thrown up by ST/ST-Ericsson for scaling down 28nm and below. The process is reported to give a 35% power performance gain and that was also by a simpler process transition from the typical CMOS. However, ST lacks the capacity and hence is exploring options with GlobalFoundries. The latter is reportedly insisting that it will use ST’s process to make parts for all other parties too, in exchange for this extra capacity – leading to ST/ ST-E potentially losing on a big competitive edge of sole access to a proprietary process through its FDSOI process. The second recent example is of Qualcomm. The world’s largest fabless company uses TSMC‘s 28nm process to manufacture its Snapdragon S4. The world’s largest pure play foundry has also had yield/capacity issues on this node. TSMC’s 28nm foundry capacity woes have put a dampener in the presently exclusive run of Qualcomm – the sole provider of integrated multimode 3G/4G LTE baseband chips. It ripples further down the chain causing distress to LTE smart-phone vendors. Shortage

26

is not expected to cease before Q4’12. Qualcomm is now planning a 23% increase in operating expenses this year and looking for alternative (apart from TSMC) suppliers. It has very recently signed up UMC and Samsung as second suppliers for 28nm. Incidentally, TSMC’s sales hit an all-time high (9.1% annual revenue growth) in April’12 – with much of the strong growth attributed to 28nm demand! So where does this leave the fabless-foundry model? And how does this affect the IDMs? One thing for sure is that the model will need to be tweaked in order to stand up to the sub 28nm/20nm challenges. Some pointers: • Cost advantage of scaling down is diminishing for the foundries. The cost-per-transistor has been about 29% per node leading to cheaper scaled down chips. 28nm and sub has seen that leveling off for the foundries. Intel still has a relatively big lead in the process race. If the fabless companies do not see a steady decline in the cost-per-transistor in their foundries’ scaling, it certainly puts a spoke in their wheel continuing down on the scaling path with this model.

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• The prohibitive high cost of setting up a new fab and the related R&D and yield challenges just does not make sense for a fabless company—even Qualcomm— to start one. Owning a pre-planned and negotiated capacity or even production means with an existing foundry is viable, but a fab from scratch does not appear to be reasonable. • With the increasing yield issues at smaller geometries pitched along with capacity shortage and uncertain market demand, a stronger vertical integration of supply chain may become the order of the day to sustain the fabless model – one which accounted for $64.9 billion in 2011. While expecting to resolve 28nm capacity shortage by Q4, TSMC has raised this year’s capex 42% to USD 8.5 billion to ride the market opportunities. • Rewinding to one of my earlier blog posts (Jan 2008) in “Travelling on the Silicon Road,” I had cited a remark by Infineon’s CEO, Ziebart in an interview to EE Times’ Rick Merritt, “The major thing giving semiconductor makers a competitive advantage has evaporated. Today everyone has access to the same process technology at roughly the same time. This access used to be what differentiated the best from the worst semiconductor companies, but now it has evaporated. What’s replacing process technology as a differentiator is systems knowhow, and it must be specific to a market area”. My comment to that, as also mentioned in the same post, was: Yes, the differentiator has moved from process technology; but it is due to access to the process technology. This access has become cost prohibitive for any single semiconductor company (perhaps leaving aside a couple with really deep pockets) and hence the scramble to find an alternate place in the value chain to survive. That access to the process technology is now morphing, if not under threat. • GlobalFoundties’ SVP Mojy Chian mentioned that “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the timeto-market”. Now, does this mean that foundries will transition towards virtual IDMs? Rewind to another earlier blog post (Dec 2007): “Over the last couple of years, we have seen IDMs going towards fablite and fabless models, and the emerging dominance of the original pure play foundries. I say “original” as lately, these foundries have been paving their way into newer territories like climbing up the design support value chain by increasing their IP portfolio, collaborating with EDA vendors for providing yield related data/information to the designers and reference design flows, and others – just short of coming up with their own ASSPs. So will

TECH ARTICLE

we see the re-emergence of real IDMs albeit in the form of a morphed foundry? IDMs, foundries, fabless… they are all morphing from their original identities and are reshaping the industry with their redefined (work in progress) grey and diffused boundaries. However, one thing stands tall amidst all this and that is “The “Fab power’ is increasingly getting honed into the semiconductor eco-system lately.” Fab matters.

About the Author Ms. Meenu Sarin is a microelectronics professional with a career spanning over 22 years and traversing across all aspects of the Semi-custom Business including Library Design & management, Program Management, Technical Marketing & Business Development, Consulting, Market and Technology trends research and analysis - and across geographies like Europe, India, Singapore, Greater China and Australia. After working with STMicroelectronics for around 14 years, she registered her company, VLSI Consultancy, in Singapore from where she consults offering technocommercial services to the semiconductor industry. This includes Training (corporate and public), Market & Technology intelligence (research & analysis) and Business Development Support (Technical Marketing, Social Media Marketing). She is also a founding member and an Executive Board Member of the Singapore Semiconductor Industry Association. From 1997-2002, Meenu was a Technical Marketing Manager in STMicroelectronics (STM)/Singapore with focus on Telecom segment. In this role, she was responsible for Business Development and Program Management for STM’s semicustom ASIC projects in Asia Pacific. Meenu also worked as a Program Manager in charge of managing various semi-custom projects with customers in the Asia-Pacific Region. Before her move to STM Singapore, Meenu worked at STM India from 1991 to 1997. As a Design Manager for Library Design Group, she was responsible for growing and managing a 30 member strong team involved in design and development of semi-custom digital libraries in various technologies across different platforms as per the market requirements and to support designers in STM’s worldwide locations. Prior to this, Meenu had been a Design Engineer for digital library design and development at STM Italy for several years after she received her engineering degree (Computer Engineering) from Delhi Institute of Technology, India in 1988. ■

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EEWeb Pulse - Issue 61  

Brad Cleveland - CEO of Proto Labs; Time-Interleaved ADCs for Digital Communication Receivers; Fab Power; RTZ - Return to Zero Comic

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